Three Bit Subtraction Circuit Via Field Programmable Gate Array (FPGA).
THREE BIT SUBTRACTION CIRCUIT VIA FIELD PROGRAMMABLE GATE
ARRAY (FPGA)
NOORAISYAH BINTI ARASID
B021010227
A report submitted in partial fulfillment of requirements for the award of the
Degree of Bachelor of Electronic Engineering (Computer Engineering)
FACULTY OF ELECTRONICS AND COMPUTER ENGINEERING
UNIVERSITI TEKNIKAL MALAYSIA MELAKA
JUNE 2013
DECLARATION
"I admit that this report is the result of my own work except summary and excerpt of
each of them I have already explained the source."
Signature: ……………………………….
Student Name: Nooraisyah Binti Arasid
Date: 07/06/2013
DECLARATION
“I hereby declared that I have read through this report entitle “Three Bit Subtraction
Circuit via Field Programmable Gate Array (FPGA) ” and found that it has comply the
partial fulfillment for awarding the Degree of Bachelor of Electronic Engineering
(Computer Engineering)”
Signature: ……………………………….
Supervisor’s Name: Encik Anuar Bin Jaafar
Date:
For father and mother dearest
Specially dedicated to my beloved parent, En Arasid bin Mohd Yasin and Pn. Siti
Noraini binti Omar and also to my siblings who give the encouragement and support for
me to completely this thesis. Not forgotten to my supervisor En Anuar bin Jaafar who
gave me a lot of guidance and advices throughout this project until successful. I also
want to thank to En Sani Irwan bin Md Salim who supported me a lot in finishing my
final year project. Thank you very much to all of you.
ACKNOWLEDGEMENT
Alhamdulillah, thanks to Allah S.W.T this project is completed. I hereby would
like to take this opportunity to thank all persons who has involved generously in helping
me and assisting me while I was completing the Final Year Report which is a
compulsory to all Universiti Teknikal Malaysia Melaka (UTeM) students in order to
complete our degree.
I would firstly to express my gratitude and thanks to my project supervisor, Mr
Anuar Bin Jaafar for his undivided support, guidance, tolerance, which proved to be
invaluable as to completion my Final Year Project.I also would like to thank the panel;
Miss Nur Aisyah bin Anas and Mr Hamzah Asyrani Bin Sulaiman whose give me a
good comment during my presentation. I also would like to take this opportunity to
express my appreciation to my family and friends for their patients, understanding and
also for their undivided support that they had gave me throughout the completion of my
project.
Last but not least, I also would like to thank all those helping and supporting
me during this project. Special thanks to En Sani Irwan bin Md Salim because guard
and help in all aspects to finish this project.
ABSTRACT
This project is about to design the software and hardware simulator for a Three
Bit subtraction Circuit via FPGA. By design the Three bit subtraction circuit are
involved in performing the subtraction for each bit by performs operation the arithmetic
and logic unit, called the Arithmetic Logic Unit (ALU). All this operation is to display
at seven segment using FPGA board by using Verilog language. A FPGA is a
semiconductor device containing programmable logic components called "logic
blocks", and programmable interconnects. Logic blocks can be programmed to perform
the function of basic logic gates such as AND, and XOR, or more complex
combinational functions such as decoders or simple mathematical functions such as
additional, subtraction, multiplication, and divisions (+, -, x, ÷). In most FPGAs, the
logic blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memories. Combination of FPGA and ALU will produce the design
of three bit subtraction circuit via FPGA.
ABSTRAK
Projek ini adalah untuk mereka bentuk perisian dan perkakasan untuk Tiga Bit
penolakan melalui FPGA. Rekabentuk litar yang dihasilkan akan melaksanakan
operasi penolakan yang melibatkan operasi aritmetik dan logik unit, yang dipanggil
Unit Aritmetik logik (UAL). Semua operasi ini adalah untuk dipaparkan pada tujuh
segmen menggunakan papan FPGA dengan menggunakan bahasa Verilog. FPGA
adalah peranti semikonduktor yang mengandungi komponen logik boleh atur cara
yang dipanggil "blok logik", dan diprogramkan. Blok logik boleh diprogramkan
untuk melaksanakan fungsi get asas logik seperti logic DAN atau bahasa sintefiknya
adalah “AND Gate”, dan juga menggunakan logic ATAU bahasa sintefiknya “XOR”,
atau fungsi gabungan yang lebih kompleks seperti pengekod atau fungsi matematik
yang mudah contohnya operasi penambahan, penolakan, darab dan operasi bahagi
(+, -, x, ÷). Dalam kebanyakan FPGA, blok logik juga merangkumi elemen-elemen
memori, yang mungkin mudah flip-flop atau lebih blok lengkap kenangan. Gabungan
FPGA dan ALU akan menghasilkan reka bentuk tiga bit penolakan litar melalui
FPGA.
vii
TABLE OF CONTENTS
Page
TITLE
DECLARATION
i
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vii
TABLE OF CONTENT
viii
LIST OF TABLE
x
LIST OF FIGURES
xi
LIST OF ABBREVIATIONS
xiv
LIST OF APPENDIX
xv
CHAPTER I: INTRODUCTION
1.1 Project overview
1
1.2 Problem Statement
1
1.3 Objectives
2
1.4 Scope of project
3
1.5 Chapter overview
3
viii
CHAPTER II: LITERATURE REVIEW
2.1
Introduction
5
2.2
Literature Review
5
2.2.1
Applications of FPGA
6
2.2.2
FPGA Architecture
7
2.2.3
FPGA design and programming
9
2.3
Xilinx Tools
10
2.3.1
Xilinx Spartan II FPGA
10
2.3.2
Design Implementation using Xilinx ISE
11
2.4 Subtraction
12
2.5 Summary
15
CHAPTER III: METHODOLOGY
3.1
Introduction
16
3.2
Methodology
16
3.3
Methodology flowchart
18
3.4
Setting up Xilinx software
22
3.5
Functional Simulation of Combinational Designs
29
3.5.1 Adding the test vectors
29
3.5.2 Simulating and Viewing the Output Waveforms
30
3.5.3 Assigning Pins with Constraints
32
Summary
35
3.6
ix
CHAPTER IV: RESULT AND ANALYSIS
4.1
Introduction
36
4.2
Design three bit subtraction
36
4.3
Result and Analysis
41
4.4
Summary
45
CHAPTER V: CONCLUSION AND RECOMMENDATIONS
5.1
Conclusion
46
5.2
Recommendation
47
REFERENCES
50
APPENDICES
52
x
LIST OF TABLES
TABLE
TITLE
PAGES
NO.
2.1
Truth Table
14
4.1
The Truth For The Half Adder
38
4.2
Full Adder
40
xi
LIST OF FIGURES
FIGURE
TITLE
PAGES
NO.
2.1
Internal Architecture of FP
10
2.2
The Spartan-II FPGA platform
11
2.3
Xilinx Integrated Software Environment (ISE)
12
2.4
Example design a subtraction circuit
15
2.5
Example Verilog coding
15
3.1
Methodology flowchart
19
3.2
Step-by-step through the design process
20
3.3
The simulation flow
21
3.4
Window Form of Xilinx ISE 10.1
22
3.5
New Project Initiation window (snapshot from Xilinx ISE
23
software)
3.6
Device and Design Flow of Project (snapshot from Xilinx ISE
24
software)
3.7
Create new source window (snapshot from Xilinx ISE
25
software)
3.8
Creating Verilog-HDL source file
26
xii
3.9
Define Verilog Source window (snapshot from Xilinx ISE
27
software)
3.10
New Project Information window (snapshot from Xilinx ISE
28
software)
3.11
Language Templates Verilog (from Xilinx ISE software)
29
3.12
Adding test vectors to the design (snapshot from Xilinx ISE
30
software)
3.13
Simulating the design
31
3.14
Simulation Results
32
3.15
Construct the pin input output
32
3.16
iMPACT Welcome Dialog Box
33
3.17
Download of the bit stream to the FPGA
34
3.18
Progress of the bit stream download
34
3.19
Succeeded message
35
4.1
Block diagram for three bit subtraction circuit design
37
4.2
Implementation of Half-Adder
39
4.3
Implement of Full – Adder with two half adders and an OR
41
gate
4.4
RTL schematic for top module three bits
42
4.5
Full RTL schematic
43
4.6
Simulation result of three bit subtraction
44
4.7
Simulation result of three bit subtraction
44
4.8
Simulation result of three bit subtraction
45
xiii
5.1
Block diagram for communication between the XILINK ISE
and the SPARTAN BOARD
48
xiv
LIST OF ABBREVIATIONS
FPGA -
Field Programmable Gate Array
ASIC -
Application-Specific Integrated Circuit
UCF
-
User Constraints File
ISE
-
Integrated Software Environment
DSP
-
Digital Signal Processor
SOC
-
Systems on Chips
CLBs -
Configurable Logic Blocks
LUT
Lookup Table
-
xv
LIST OF APPENDIX
FIGURE
NO.
TITLE
PAGES
6.1
RTL schematic for first complement
53
6.2
RTL schematic for second complement
54
6.3
RTL schematic Full Adder
55
6.4
RTL schematic Half Adder
55
1
CHAPTER I
INTRODUCTION
1.1
Project Overview
This chapter will cover the introduction of the project. The chapter starts with a
brief background of the project. Then, it provides the problem statements that are
addressed by this project, followed by the objectives and scope. Finally, the organization
of this thesis is given.
1.2
Problem Statement
This project is to design the software and a hardware simulator for a Three Bit
subtraction Circuit Via FPGA. By design the Three bit subtraction circuit are involved
in performing the subtraction for each bit by performs operation the arithmetic and logic
unit, called the Arithmetic Logic Unit (ALU) example Addition, Subtraction,
Multiplication and Division.
2
All this operation is to display at seven segment using FPGA board by using
Verilog language. A FPGA is a semiconductor device containing programmable logic
components called "logic blocks", and programmable interconnects. Logic blocks can be
programmed to perform the function of basic logic gates such as AND, and XOR, or
more complex combinational functions such as decoders or simple mathematical
functions (+, -, x, ÷). In most FPGAs, the logic blocks also include memory elements,
which may be simple flip-flops or more complete blocks of memories. Combination of
FPGA and ALU will produce the design of three bit subtraction circuit via FPGA.
The purpose of designing three bit subtraction is because if we want to do
operation of subtraction we need three bit example 2 – 0 = 2 the integer is representing
as bits. These three bits will be implemented as logic gates in order to obtain the result
of subtraction. The process of subtraction will be latter discuss in chapter III.
The problem before this was FPGAs are usually slower than their applicationspecific integrated circuit (ASIC) counterparts, as they cannot handle as complex a
design, and draw more power. If we represent two bits for subtraction it will not give
any result. Therefore to obtain the result the minimum number of bits to be used is three
bits.
1.3
Objectives
The main objective of this project is to design the three bit subtraction circuit via
field programmable gate array (FPGA). To develop Verilog program for doing basic
arithmetic instruction concept and basic information about the FPGA. Moreover, to
design the Three bit subtraction involved in performing the subtraction for each bit by
performs operation the arithmetic and logic unit, called the Arithmetic Logic Unit
(ALU).
3
1.4
Scope of project
The main goal of this project is design Three Bit Subtraction Circuit Via FPGA.
There is two scope will be cover in this project.
Firstly is to design circuit using structure model of verilog. Then simulation
design with is to develop the coding of three bit subtraction circuit using the Verilog
language. Simulate design will be run whether coding successful or not.
Secondly is to testing on the board which is trainer board FPGA Spartan II.
Once coding of three bit subtraction is fully finish. The coding will be testing on board
FPGA.
1.5
Chapter overview
This thesis comprises five chapters and that is Introduction, Literature Review,
Methodology, Result and Analysis, and Conclusion and Recommendations.
Introduction has been provided in this chapter whereby it serves as the
background for understanding the project described in this thesis.
Next, Chapter II reviews the theory on subtraction and research about work
related to the project.
For, Chapter III discusses about the methodology that was followed during the
course of this project.
4
Experimental results and analysis is presented in Chapter IV and finally, this
thesis ends with Chapter V that concludes the project followed by a number of
recommendations for future research.
5
CHAPTER II
LITERATURE REVIEW
2.1
Introduction
In this chapter, reviews of the previous researches project that are related with
this project will be discussed. The information becomes additional source for the project
in becoming more successful.
To have a brief understanding of the researches related to the project, a few
literature reviews had been done. This chapter will describe the related literature
reviews.
2.2
Literature Review
A field-programmable gate array is a semiconductor device containing
programmable logic components called "logic blocks", and programmable interconnects
[1]. Logic blocks can be programmed to perform the function of basic logic gates such
as AND, and XOR, or more complex combinational functions such as decoders or
simple mathematical functions [2].
6
In most FPGAs, the logic blocks also include memory elements, which may be
simple flip-flops or more complete blocks of memories. A hierarchy of programmable
interconnects allows logic blocks to be interconnected as needed by the system designer,
somewhat like a one-chip programmable breadboard. Logic blocks and interconnects
can be programmed by the customer or designer, after the FPGA is manufactured, to
implement any logical function hence the name "field-programmable"[1].
FPGAs are usually slower than their application-specific integrated circuit
(ASIC) counterparts, as they cannot handle as complex a design, and draw more power.
But their advantages include a shorter time to market, ability to re-program in the field
to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less
flexible versions of their FPGAs which cannot be modified after the design is
committed. The designs are developed on regular FPGAs and then migrated into a fixed
version that more resembles an ASIC. Another alternative are complex programmable
logic devices (CPLDs). For this project, I have used the Xilinx Sparta-II FPGA.
2.2.1
Applications of FPGA
Applications of FPGAs include digital signal processor DSP, software-defined
radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer
vision, speech recognition, cryptography, bioinformatics, computer hardware emulation
and a growing range of other areas. FPGAs originally began as competitors to CPLDs
and competed in a similar space, that of glue logic for PCBs. As their size, capabilities,
and speed increased, they began to take over larger and larger functions to the state
where some are now marketed as full systems on chips (SOC).FPGAs especially find
applications in any area or algorithm that can make use of the massive parallelism
offered by their architecture. One such area is code breaking, in particular brute-force
attack, of cryptographic algorithms.
7
FPGAs are increasingly used in conventional High Performance Computing
applications where computational kernels such as FFT or Convolution are performed on
the FPGA instead of a microprocessor. The use of FPGAs for computing tasks is known
as reconfigurable computing [1].
The inherent parallelism of the logic resources on the FPGA allows for
considerable compute throughput even at a sub-500MHz clock rate. For example, the
current (2007) generation of FPGAs can implement around 100 single precision floating
point units, all of which can compute a result every single clock cycle. The flexibility of
the FPGA allows for even higher performance by trading off precision and range in the
number format for an increased number of parallel arithmetic units. This has driven a
new type of processing called reconfigurable computing, where time intensive tasks are
offloaded from software to FPGAs. The adoption of FPGAs in high performance
computing is currently limited by the complexity of FPGA design compared to
conventional software and the extremely long turn-around times of current design tools,
where 4-8 hours wait is necessary after even minor changes to the source code [2].
2.2.2
FPGA Architecture
The typical basic architecture consists of an array of configurable logic blocks
(CLBs) and routing channels. Multiple I/O pads may fit into the height of one row or the
width of one column in the array. Generally, all the routing channels have the same
width (number of wires).
An application circuit must be mapped into an FPGA with adequate resources. A
classic FPGA logic block consists of a 4-input lookup table (LUT), and flip-flop, as
shown below. In recent years, manufacturers have started moving to 6-input LUTs in
their high performance parts, claiming increased performance.
ARRAY (FPGA)
NOORAISYAH BINTI ARASID
B021010227
A report submitted in partial fulfillment of requirements for the award of the
Degree of Bachelor of Electronic Engineering (Computer Engineering)
FACULTY OF ELECTRONICS AND COMPUTER ENGINEERING
UNIVERSITI TEKNIKAL MALAYSIA MELAKA
JUNE 2013
DECLARATION
"I admit that this report is the result of my own work except summary and excerpt of
each of them I have already explained the source."
Signature: ……………………………….
Student Name: Nooraisyah Binti Arasid
Date: 07/06/2013
DECLARATION
“I hereby declared that I have read through this report entitle “Three Bit Subtraction
Circuit via Field Programmable Gate Array (FPGA) ” and found that it has comply the
partial fulfillment for awarding the Degree of Bachelor of Electronic Engineering
(Computer Engineering)”
Signature: ……………………………….
Supervisor’s Name: Encik Anuar Bin Jaafar
Date:
For father and mother dearest
Specially dedicated to my beloved parent, En Arasid bin Mohd Yasin and Pn. Siti
Noraini binti Omar and also to my siblings who give the encouragement and support for
me to completely this thesis. Not forgotten to my supervisor En Anuar bin Jaafar who
gave me a lot of guidance and advices throughout this project until successful. I also
want to thank to En Sani Irwan bin Md Salim who supported me a lot in finishing my
final year project. Thank you very much to all of you.
ACKNOWLEDGEMENT
Alhamdulillah, thanks to Allah S.W.T this project is completed. I hereby would
like to take this opportunity to thank all persons who has involved generously in helping
me and assisting me while I was completing the Final Year Report which is a
compulsory to all Universiti Teknikal Malaysia Melaka (UTeM) students in order to
complete our degree.
I would firstly to express my gratitude and thanks to my project supervisor, Mr
Anuar Bin Jaafar for his undivided support, guidance, tolerance, which proved to be
invaluable as to completion my Final Year Project.I also would like to thank the panel;
Miss Nur Aisyah bin Anas and Mr Hamzah Asyrani Bin Sulaiman whose give me a
good comment during my presentation. I also would like to take this opportunity to
express my appreciation to my family and friends for their patients, understanding and
also for their undivided support that they had gave me throughout the completion of my
project.
Last but not least, I also would like to thank all those helping and supporting
me during this project. Special thanks to En Sani Irwan bin Md Salim because guard
and help in all aspects to finish this project.
ABSTRACT
This project is about to design the software and hardware simulator for a Three
Bit subtraction Circuit via FPGA. By design the Three bit subtraction circuit are
involved in performing the subtraction for each bit by performs operation the arithmetic
and logic unit, called the Arithmetic Logic Unit (ALU). All this operation is to display
at seven segment using FPGA board by using Verilog language. A FPGA is a
semiconductor device containing programmable logic components called "logic
blocks", and programmable interconnects. Logic blocks can be programmed to perform
the function of basic logic gates such as AND, and XOR, or more complex
combinational functions such as decoders or simple mathematical functions such as
additional, subtraction, multiplication, and divisions (+, -, x, ÷). In most FPGAs, the
logic blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memories. Combination of FPGA and ALU will produce the design
of three bit subtraction circuit via FPGA.
ABSTRAK
Projek ini adalah untuk mereka bentuk perisian dan perkakasan untuk Tiga Bit
penolakan melalui FPGA. Rekabentuk litar yang dihasilkan akan melaksanakan
operasi penolakan yang melibatkan operasi aritmetik dan logik unit, yang dipanggil
Unit Aritmetik logik (UAL). Semua operasi ini adalah untuk dipaparkan pada tujuh
segmen menggunakan papan FPGA dengan menggunakan bahasa Verilog. FPGA
adalah peranti semikonduktor yang mengandungi komponen logik boleh atur cara
yang dipanggil "blok logik", dan diprogramkan. Blok logik boleh diprogramkan
untuk melaksanakan fungsi get asas logik seperti logic DAN atau bahasa sintefiknya
adalah “AND Gate”, dan juga menggunakan logic ATAU bahasa sintefiknya “XOR”,
atau fungsi gabungan yang lebih kompleks seperti pengekod atau fungsi matematik
yang mudah contohnya operasi penambahan, penolakan, darab dan operasi bahagi
(+, -, x, ÷). Dalam kebanyakan FPGA, blok logik juga merangkumi elemen-elemen
memori, yang mungkin mudah flip-flop atau lebih blok lengkap kenangan. Gabungan
FPGA dan ALU akan menghasilkan reka bentuk tiga bit penolakan litar melalui
FPGA.
vii
TABLE OF CONTENTS
Page
TITLE
DECLARATION
i
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vii
TABLE OF CONTENT
viii
LIST OF TABLE
x
LIST OF FIGURES
xi
LIST OF ABBREVIATIONS
xiv
LIST OF APPENDIX
xv
CHAPTER I: INTRODUCTION
1.1 Project overview
1
1.2 Problem Statement
1
1.3 Objectives
2
1.4 Scope of project
3
1.5 Chapter overview
3
viii
CHAPTER II: LITERATURE REVIEW
2.1
Introduction
5
2.2
Literature Review
5
2.2.1
Applications of FPGA
6
2.2.2
FPGA Architecture
7
2.2.3
FPGA design and programming
9
2.3
Xilinx Tools
10
2.3.1
Xilinx Spartan II FPGA
10
2.3.2
Design Implementation using Xilinx ISE
11
2.4 Subtraction
12
2.5 Summary
15
CHAPTER III: METHODOLOGY
3.1
Introduction
16
3.2
Methodology
16
3.3
Methodology flowchart
18
3.4
Setting up Xilinx software
22
3.5
Functional Simulation of Combinational Designs
29
3.5.1 Adding the test vectors
29
3.5.2 Simulating and Viewing the Output Waveforms
30
3.5.3 Assigning Pins with Constraints
32
Summary
35
3.6
ix
CHAPTER IV: RESULT AND ANALYSIS
4.1
Introduction
36
4.2
Design three bit subtraction
36
4.3
Result and Analysis
41
4.4
Summary
45
CHAPTER V: CONCLUSION AND RECOMMENDATIONS
5.1
Conclusion
46
5.2
Recommendation
47
REFERENCES
50
APPENDICES
52
x
LIST OF TABLES
TABLE
TITLE
PAGES
NO.
2.1
Truth Table
14
4.1
The Truth For The Half Adder
38
4.2
Full Adder
40
xi
LIST OF FIGURES
FIGURE
TITLE
PAGES
NO.
2.1
Internal Architecture of FP
10
2.2
The Spartan-II FPGA platform
11
2.3
Xilinx Integrated Software Environment (ISE)
12
2.4
Example design a subtraction circuit
15
2.5
Example Verilog coding
15
3.1
Methodology flowchart
19
3.2
Step-by-step through the design process
20
3.3
The simulation flow
21
3.4
Window Form of Xilinx ISE 10.1
22
3.5
New Project Initiation window (snapshot from Xilinx ISE
23
software)
3.6
Device and Design Flow of Project (snapshot from Xilinx ISE
24
software)
3.7
Create new source window (snapshot from Xilinx ISE
25
software)
3.8
Creating Verilog-HDL source file
26
xii
3.9
Define Verilog Source window (snapshot from Xilinx ISE
27
software)
3.10
New Project Information window (snapshot from Xilinx ISE
28
software)
3.11
Language Templates Verilog (from Xilinx ISE software)
29
3.12
Adding test vectors to the design (snapshot from Xilinx ISE
30
software)
3.13
Simulating the design
31
3.14
Simulation Results
32
3.15
Construct the pin input output
32
3.16
iMPACT Welcome Dialog Box
33
3.17
Download of the bit stream to the FPGA
34
3.18
Progress of the bit stream download
34
3.19
Succeeded message
35
4.1
Block diagram for three bit subtraction circuit design
37
4.2
Implementation of Half-Adder
39
4.3
Implement of Full – Adder with two half adders and an OR
41
gate
4.4
RTL schematic for top module three bits
42
4.5
Full RTL schematic
43
4.6
Simulation result of three bit subtraction
44
4.7
Simulation result of three bit subtraction
44
4.8
Simulation result of three bit subtraction
45
xiii
5.1
Block diagram for communication between the XILINK ISE
and the SPARTAN BOARD
48
xiv
LIST OF ABBREVIATIONS
FPGA -
Field Programmable Gate Array
ASIC -
Application-Specific Integrated Circuit
UCF
-
User Constraints File
ISE
-
Integrated Software Environment
DSP
-
Digital Signal Processor
SOC
-
Systems on Chips
CLBs -
Configurable Logic Blocks
LUT
Lookup Table
-
xv
LIST OF APPENDIX
FIGURE
NO.
TITLE
PAGES
6.1
RTL schematic for first complement
53
6.2
RTL schematic for second complement
54
6.3
RTL schematic Full Adder
55
6.4
RTL schematic Half Adder
55
1
CHAPTER I
INTRODUCTION
1.1
Project Overview
This chapter will cover the introduction of the project. The chapter starts with a
brief background of the project. Then, it provides the problem statements that are
addressed by this project, followed by the objectives and scope. Finally, the organization
of this thesis is given.
1.2
Problem Statement
This project is to design the software and a hardware simulator for a Three Bit
subtraction Circuit Via FPGA. By design the Three bit subtraction circuit are involved
in performing the subtraction for each bit by performs operation the arithmetic and logic
unit, called the Arithmetic Logic Unit (ALU) example Addition, Subtraction,
Multiplication and Division.
2
All this operation is to display at seven segment using FPGA board by using
Verilog language. A FPGA is a semiconductor device containing programmable logic
components called "logic blocks", and programmable interconnects. Logic blocks can be
programmed to perform the function of basic logic gates such as AND, and XOR, or
more complex combinational functions such as decoders or simple mathematical
functions (+, -, x, ÷). In most FPGAs, the logic blocks also include memory elements,
which may be simple flip-flops or more complete blocks of memories. Combination of
FPGA and ALU will produce the design of three bit subtraction circuit via FPGA.
The purpose of designing three bit subtraction is because if we want to do
operation of subtraction we need three bit example 2 – 0 = 2 the integer is representing
as bits. These three bits will be implemented as logic gates in order to obtain the result
of subtraction. The process of subtraction will be latter discuss in chapter III.
The problem before this was FPGAs are usually slower than their applicationspecific integrated circuit (ASIC) counterparts, as they cannot handle as complex a
design, and draw more power. If we represent two bits for subtraction it will not give
any result. Therefore to obtain the result the minimum number of bits to be used is three
bits.
1.3
Objectives
The main objective of this project is to design the three bit subtraction circuit via
field programmable gate array (FPGA). To develop Verilog program for doing basic
arithmetic instruction concept and basic information about the FPGA. Moreover, to
design the Three bit subtraction involved in performing the subtraction for each bit by
performs operation the arithmetic and logic unit, called the Arithmetic Logic Unit
(ALU).
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1.4
Scope of project
The main goal of this project is design Three Bit Subtraction Circuit Via FPGA.
There is two scope will be cover in this project.
Firstly is to design circuit using structure model of verilog. Then simulation
design with is to develop the coding of three bit subtraction circuit using the Verilog
language. Simulate design will be run whether coding successful or not.
Secondly is to testing on the board which is trainer board FPGA Spartan II.
Once coding of three bit subtraction is fully finish. The coding will be testing on board
FPGA.
1.5
Chapter overview
This thesis comprises five chapters and that is Introduction, Literature Review,
Methodology, Result and Analysis, and Conclusion and Recommendations.
Introduction has been provided in this chapter whereby it serves as the
background for understanding the project described in this thesis.
Next, Chapter II reviews the theory on subtraction and research about work
related to the project.
For, Chapter III discusses about the methodology that was followed during the
course of this project.
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Experimental results and analysis is presented in Chapter IV and finally, this
thesis ends with Chapter V that concludes the project followed by a number of
recommendations for future research.
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CHAPTER II
LITERATURE REVIEW
2.1
Introduction
In this chapter, reviews of the previous researches project that are related with
this project will be discussed. The information becomes additional source for the project
in becoming more successful.
To have a brief understanding of the researches related to the project, a few
literature reviews had been done. This chapter will describe the related literature
reviews.
2.2
Literature Review
A field-programmable gate array is a semiconductor device containing
programmable logic components called "logic blocks", and programmable interconnects
[1]. Logic blocks can be programmed to perform the function of basic logic gates such
as AND, and XOR, or more complex combinational functions such as decoders or
simple mathematical functions [2].
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In most FPGAs, the logic blocks also include memory elements, which may be
simple flip-flops or more complete blocks of memories. A hierarchy of programmable
interconnects allows logic blocks to be interconnected as needed by the system designer,
somewhat like a one-chip programmable breadboard. Logic blocks and interconnects
can be programmed by the customer or designer, after the FPGA is manufactured, to
implement any logical function hence the name "field-programmable"[1].
FPGAs are usually slower than their application-specific integrated circuit
(ASIC) counterparts, as they cannot handle as complex a design, and draw more power.
But their advantages include a shorter time to market, ability to re-program in the field
to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less
flexible versions of their FPGAs which cannot be modified after the design is
committed. The designs are developed on regular FPGAs and then migrated into a fixed
version that more resembles an ASIC. Another alternative are complex programmable
logic devices (CPLDs). For this project, I have used the Xilinx Sparta-II FPGA.
2.2.1
Applications of FPGA
Applications of FPGAs include digital signal processor DSP, software-defined
radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer
vision, speech recognition, cryptography, bioinformatics, computer hardware emulation
and a growing range of other areas. FPGAs originally began as competitors to CPLDs
and competed in a similar space, that of glue logic for PCBs. As their size, capabilities,
and speed increased, they began to take over larger and larger functions to the state
where some are now marketed as full systems on chips (SOC).FPGAs especially find
applications in any area or algorithm that can make use of the massive parallelism
offered by their architecture. One such area is code breaking, in particular brute-force
attack, of cryptographic algorithms.
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FPGAs are increasingly used in conventional High Performance Computing
applications where computational kernels such as FFT or Convolution are performed on
the FPGA instead of a microprocessor. The use of FPGAs for computing tasks is known
as reconfigurable computing [1].
The inherent parallelism of the logic resources on the FPGA allows for
considerable compute throughput even at a sub-500MHz clock rate. For example, the
current (2007) generation of FPGAs can implement around 100 single precision floating
point units, all of which can compute a result every single clock cycle. The flexibility of
the FPGA allows for even higher performance by trading off precision and range in the
number format for an increased number of parallel arithmetic units. This has driven a
new type of processing called reconfigurable computing, where time intensive tasks are
offloaded from software to FPGAs. The adoption of FPGAs in high performance
computing is currently limited by the complexity of FPGA design compared to
conventional software and the extremely long turn-around times of current design tools,
where 4-8 hours wait is necessary after even minor changes to the source code [2].
2.2.2
FPGA Architecture
The typical basic architecture consists of an array of configurable logic blocks
(CLBs) and routing channels. Multiple I/O pads may fit into the height of one row or the
width of one column in the array. Generally, all the routing channels have the same
width (number of wires).
An application circuit must be mapped into an FPGA with adequate resources. A
classic FPGA logic block consists of a 4-input lookup table (LUT), and flip-flop, as
shown below. In recent years, manufacturers have started moving to 6-input LUTs in
their high performance parts, claiming increased performance.