Design And Characterization Of Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket By Using TCAD Tools.

(1)

DESIGN AND CHARACTERIZATION OF VERTICAL STRAINED SILICON MOSFET INCORPORATING DIELECTRIC POCKET BY USING TCAD TOOLS

NAZIRAH BINTI MAKHTAR

This Report Is Submitted In Partial Fulfilment of Requirements for the Bachelor Degree of Electronic Engineering (Computer Engineering)

Faculty of Electronic and Computer Engineering Universiti Teknikal Malaysia Melaka

(2)

1 2 / 1 3

UNIVERSTI TEKNIKAL MALAYSIA MELAKA

FAKULTI KEJURUTERAAN ELEKTRONIK DAN KEJURUTERAAN KOMPUTER

BORANG PENGESAHAN STATUS LAPORAN PROJEK SARJANA MUDA II

Tajuk Projek :

Sesi Pengajian :

DESIGN AND CHARACTERIZATION OF VERTICAL STRAINED SILICON MOSFET INCORPORATING DIELECTRIC POCKET BY USING TCAD TOOLS.

Saya NAZIRAH BINTI MAKHTAR mengaku membenarkan Laporan Projek Sarjana Muda ini disimpan di Perpustakaan dengan syarat-syarat kegunaan seperti berikut:

1. Laporan adalah hakmilik Universiti Teknikal Malaysia Melaka.

2. Perpustakaan dibenarkan membuat salinan untuk tujuan pengajian sahaja.

3. Perpustakaan dibenarkan membuat salinan laporan ini sebagai bahan pertukaran antara institusi pengajian tinggi.

4. Sila tandakan ( √ ) :

SULIT*

*(Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972)

TERHAD** **(Mengandungi maklumat terhad yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan)

TIDAK TERHAD

Disahkan oleh:

(TANDATANGAN PENULIS) (COP DAN TANDATANGAN PENYELIA)

ALAMAT: LOT 744 KAMPUNG KUKANG JALAN PEROL

16010 KOTA BHARU KELANTAN

(3)

“I declare that this thesis is the result of my own work except for quotes as cited in the references”.

Signature : ……….

Author : NAZIRAH BINTI MAKHTAR

(4)

“I declare that I have been reading this thesis in view of our work is sufficient from the scope and quality for the award of Bachelor of Electronic Engineering (Computer

Engineering)”.

Signature : ………

Supervisor’s Name : MR. ZUL ATFYI FAUZAN BIN MOHAMMED NAPIAH

(5)

Dedicated to my beloved family To my father and mother To my respected lecturer/supervisor

To all my friends

And thanks to Allah for nurturing me spiritually and helping me see the world in the right perspective.

(6)

ACKNOWLEDGEMENT

Alhamdulillah, thank you to Allah for giving the author blessing for health, strengths and earnestness to complete this report despite the challenges faced and emergence of many unwanted circumstances.

The author would like to take this opportunity to convey the highest appreciation to Mr. Zul Atfyi Fauzan bin Mohammed Napiah as supervisor for giving her the chance to work under his supervision and giving full support in all guidance, advice and commitment upon the effort to settle this report also for spending his time and efforts in evaluating the work. The special thanks also to Mr. Muhammad Idzdihar bin Idris as 2nd supervisor for assisting the author to finish this report.

The author would also like to thanks to Industrial Training Committee Faculty of Electronic and Computer University Technical Malaysian Malacca for organizing it systematically and flawlessly.

Thanks to our greatest family for their support and blessing and also to all beloved friends for their helps, support, comment or criticisms.

(7)

vii

ABSTRACT

This project is about to design and characterize the Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket (SDP-VMOSFET) by using SILVACO Technology Computer Aided Design (TCAD) tools. SILVACO TCAD tool is a program, which allow for creation, fabrication, and simulation of semiconductor devices. The structure of the vertical MOSFET leads to a double channel width that is increasing the packaging density. The strained silicon MOSFET is introduced to modify the carrier transport properties of silicon in order to enhance transport of both electrons and holes within strained layer. Dielectric pocket is act to control encroachment of the drain doping into the channel and reduce short channel effects (SCE). Overall, SDP- VMOSFET, which is combining Vertical MOSFET, Strained Silicon and Dielectric Pocket can overcome the short channel effect in term of leakage current, threshold voltage roll-off also Drain Induce Barrier Lowering (DIBL). As a result, SDP- VMOSFET produces a better threshold voltage and DIBL compared to related structures. Meanwhile, it gives slightly increased for leakage current compared to Vertical MOSFET Incorporating Dielectric Pocket. The characteristics of the SDP- VMOSFET are analysed in order to optimize the performance of the device and leading to the next generation of IC technology.

(8)

ABSTRAK

Projek ini adalah untuk mereka dan mengenal pasti ciri-ciri MOSFET Menegak Terikan Silikon Mengandungi Poket Dielektrik (SDP-VMOSFET) menggunakan perisian SILVACO TCAD. Perisian SILVACO TCAD adalah program yang membolehkan rekacipta, fabrikasi dan simulasi peranti semikonduktor. Struktur MOSFET Menegak membawa kepada saluran yang lebih lebar untuk meningkatkan ketumpatan dalam pembungkusan. MOSFET Terikan Silicon diperkenalkan untuk mengubahsuai ciri-ciri pengangkutan pembawa silicon dalam usaha untuk meningkatkan pengangkutan kedua-dua elektron dan lubang di dalam terikan lapisan. Pocket Dielektrik pula bertindak untuk mengawal pencerobohan ke dalam saluran dan mengurangkan Kesan Saluran Pendek (SCE). Secara kesuluruhannya, SDP-VMOSFET, hasil gabungan MOSFET menegak, Terikan Silikon dan Poket Dielektrik boleh mengatasi SCE seperti kebocoran arus, voltan ambang dan juga Drain Induce Barrier Lowering (DIBL). Keputusannya, SDP-VMOSFET menghasilkan nilai voltan ambang dan DIBL yang lebih baik banding struktur yang berkaitan. Ciri-ciri SDP-VMOSFET dianalisis untuk mengoptimumkan prestasi peranti dan seterusnya membawa kepada generasi IC teknologi yang mendatang.

(9)

TABLE OF CONTENT

CHAPTER TITLE

PROJECT TITLE

PAGE i

STATUS CONFIRMATION REPORT FORM ii

AUTHOR’S DECLARATION iii

SUPERVISOR’S DECLARATION iv

DEDICATION v

ACKNOWLEDGEMENT vi

ABSTRACT ABSTRAK

TABLE OF CONTENT LIST OF TABLES

vii viii ix xii LIST OF FIGURES

LIST OF ABBREVIATIONS LIST OF APPENDIXES

xiii xvii xviii

I INTRODUCTION

1.1 Background 1

1.2 Problem Statement 2

1.3 Objectives 3

1.4 Scope of Project 3

1.4.1 Introduction to TCAD 4

1.4.2 ATHENA 4

1.4.3 ATLAS 4

1.4.4 DevEdit 5

1.5 Methodology 5

(10)

1 0

II LITERATURE REVIEW

2.1 Conventional MOSFET 7

2.2 Vertical MOSFET 9

2.2.1 Advantages of Vertical MOSFET: 11

2.2.2 Disadvantages of Vertical MOSFET: 11

2.3 Dielectric pocket 12

2.4 Strained Silicon, SiGe (Silicon Germanium) 13

2.5 Short Channel Effects (SCE) 14

2.5.1 Threshold Voltage (VTH) 15

2.5.2 Leakage Current (IOFF) 16

2.5.3 Active Current (ION) 16

2.5.4 Drain-Induced Barrier Lowering (DIBL) and Punchthrough 17

III METHODOLOGY

3.1 Summary of Project Flows 18

3.2 Introduction to SILVACO TCAD Tools 21

3.3 Creating Vertical Strained Silicon MOSFET Incorporating

Dielectric Pocket Structure Using DevEdit 22

3.4 Creating Vertical Strained Silicon MOSFET Incorporating

Dielectric Pocket Structure Using ATHENA 45

3.5 Device Simulation Using ATLAS 60

IV RESULT AND DISCUSSIONS

4.1 Vertical Strained Silicon MOSFET Incorporating Dielectric

Pocket (SDP-VMOSFET) Structure by Using DevEdit. 66

4.11 Vertical MOSFET 66

4.1.3 Vertical Strained Silicon MOSFET 70

4.1.4 Vertical MOSFET Incorporating Dielectric Pocket 73 4.1.5 Vertical Strained Silicon MOSFET Incorporating Dielectric

(11)

1 1

Pocket 76

4.1.5.1 Comparison of Vertical MOSFET, Vertical Strained Silicon MOSFET and Vertical MOSFET

Incorporating Dielectric Pocket 79

4.1.5.2 Comparison of Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket for various channel

length 82

4.1 Vertical Strained Silicon MOSFET Incorporating Dielectric

Pocket (SDP-VMOSFET) Structure by Using ATHENA 84

V CONCLUSION AND RECOMMENDATION

5.1 Conclusion 87

5.2 Recommendation 88

REFERENCES 89

APPENDIX A 91

APPENDIX B 93

(12)

xii

LIST OF TABLES

NO TITLE PAGE

4.1 Threshold Voltage for various structures 79

4.2 Threshold Voltage of SDP-VMOSFET for various 82

(13)

LIST OF FIGURES

NO TITLE PAGE

1.1 Figure Scope of Project Work 3

1.2 Flow Chart of the Project 5

2.1 Conventional MOSFET 8

2.2 Vertical MOSFET 10

2.3 Vertical MOSFET incorporating Dielectric Pocket 13

2.4 Threshold Voltage 16

2.5 Leakage Current 16

2.6 Drain Induced Barrier Lowering 17

3.1 Methodology of the Project 20

3.2 Resize Work Area 22

3.3 Resized Area 23

3.4 Drawing the Region 24

3.5 Setting the Base Impurity 25

3.6 The Silicon Region 25

3.7 Adding a Silicon Oxide Region 26

3.8 Silicon Oxide Region 27

3.9 Adding Source Electrode 28

3.10 Setting the Base Impurity 29

3.11 Source Electrode Region 29

(14)

3.13 Setting the Base Impurity 31

3.14 Drain Electrode Region 31

3.15 Substrate Electrode Panel 32

3.16 Adding Gate Electrode 32

3.17 Setting the Base Impurity 33

3.18 The Polysilicon Gate Region 34

3.19 Adding the Silicon Germanium Region 34

3.20 The Silicon Germanium Region 35

3.21 Add Impurity 36

3.22 User Add Impurity 37

3.23 Adding Impurity 38

3.24 User Added Impurity 39

3.25 Adding the Dielectric Pocket Region 40

3.26 Dielectric Pocket Region 40

3.27 Refinement on Quantities 41

3.28 Mesh Parameter 42

3.29 Mesh Example 42

3.30 SDP-VMOSFET Structure 43

3.31 SDP-VMOSFET with Mesh 44

3.32 SDP-VMOSFET with Net Doping 44

3.33 SDP-VMOSFET with Mesh and Net Doping 45

3.34 Creating Non-Uniform Grid in 0.39 µm by 0.67 µm Simulation Area 46

3.35 Initial Triangular Grid 47

3.36 Codes for Etching 47

3.37 Etching the Silicon 48

3.38 Etching to Locate Dielectric Pocket 48

3.39 Silicon Deposit and Etching 49

3.40 Conformal Deposition of Oxide Layer 49

3.41 Etching of Oxide Layer 50

3.42 Codes for Depositing SiGe, Depositing Silicon, Gate Oxidation and 51 Threshold Voltage Adjust Implant

(15)

3.43 Conformal Deposition of Silicon Germanium Layer 51

3.44 Conformal Deposition of Silicon Layer 52

3.45 Deposition of Oxide Layer 52

3.46 Codes for Deposition of Polysilicon 53

3.47 Conformal Deposition of Polysilicon Layer 53

3.48 Code for Etching of Polysilicon 54

3.49 Etching of Polysilicon Structure 54

3.50 Codes for Performing Oxidation and Doping Of the Polysilicon 54 3.51 Net Doping Contour Plot after Polysilicon Implantation Step 55

3.52 Codes for Spacer Oxide Deposition 55

3.53 Structure of Spacer Oxide Deposition 56

3.54 Source and Drain Annealing 56

3.55 Codes for Handling and Metallization Part 57

3.56 Half of the SDP-VMOSFET 57

3.57 Net Doping Of the Half SDP-VMOSFET 58

3.58 Codes for Mirror the Structure and Declare the Electrode 58

3.59 Structure of Full SDP-VMOSFET 59

3.60 Net Doping For the Full SDP-VMOSFET 59

3.61 Codes to Load the .str File from DevEdit or ATHENA 60

3.62 Code for the Recombination Model 61

3.63 Codes for Specifying the Contact Characteristic and Interface Properties 61

3.64 Codes for the Method Statement 62

3.65 codes to obtain ID-VG curve 63

3.66 ID-VG curve for VD = 0.1 V 63

3.67 ID-VG curve for VD = 1.0 V 64

3.68 Codes to Obtain ID-VD curve 64

3.69 Overlay of ID-VD curve 65

4.1 Vertical MOSFET Structure 67

4.2 The Threshold Voltage for 90 nm Vertical MOSFET Structure 68 4.3 The Leakage Current and Active Current for 90 nm Vertical MOSFET 69

(16)

4.4 The DIBL for 90 nm Vertical MOSFET Structure 70

4.5 Vertical MOSFET with SiGe Structure 71

4.6 The Threshold Voltage for 90 nm Vertical Strained Silicon MOSFET 71 Structure

4.7 The Leakage Current and Active Current For 90 Nm Vertical Strained 72 Silicon MOSFET Structure

4.8 The DIBL for 90 nm Vertical Strained Silicon MOSFET Structure 72

4.9 Vertical MOSFET Incorporating Dielectric Pocket 73

4.10 The Threshold Voltage for 90 Nm Vertical MOSFET Incorporating 74 Dielectric Pocket Structure

4.11 The Leakage Current and Active Current for 90 nm Vertical MOSFET 74 Incorporating Dielectric Pocket Structure

4.12 The DIBL for 90 nm Vertical MOSFET Incorporating Dielectric Pocket 75 Structure

4.13 SDP-VMOSFET Structure 76

4.14 The Threshold Voltage for 90 nm SDP-VMOSFET Structure 77

4.15 The Leakage Current and Active Current for 90 Nm SDP-VMOSFET 77 Structure

4.16 The DIBL for 90 nm SDP-VMOSFET Structure 78

4.17 Various Structure of Vertical MOSFET 79

4.18 Log ID-VG Curve for Various Structures 80

4.19 ID-VD Curve for Various Structures 81

4.20 ID-VG Curve for Various Channel Length 82

4.21 Log ID-VG Curve for Various Channel Length 83

4.22 ID-VD Curve for Various Channel Length 84

4.23 Structure of SDP-VMOSFET 85

4.24 The Threshold Voltage for SDP-VMOSFET Structure 85

4.25 The Leakage Current and Active Current for SDP-VMOSFET Structure 86

(17)

xvii

LIST OF ABBREVIATIONS

SDP-VMOSFET - Vertical Strained Silicon MOSFET Incorporating Pocket

Dielectric

MOSFET - Metal-Oxide Semiconductor Field Effect Transistor

TCAD - Technology Computer Aid Design

SiGe - Silicon Germanium

DIBL - Drain-Induced Barrier Lowering

SCE - Short Channel Effects

FET - Field Effect Transistor

FILOX - Fillet local oxidation ID

Ioff

tOx

VDS

VGS

VTH

HDD

- Drain Leakage - Leakage Current - Channel Length

- Oxide Thickness - Drain-Source Voltage - Gate-Source Voltage - Threshold Voltage - Highly Doped Junctions

(18)

xviii

LIST OF APPENDIXES

NO TITLE PAGE

A Example for ATLAS Device Analysing SDP-VMOSFET structure

from DevEdit 89

B C

Example for Creating SDP-VMOSFET using ATHENA

Example for ATLAS Device Analysing SDP-VMOSFET structure from ATHENA

(19)

CHAPTER I

INTRODUCTION

1.1 Background

The metal oxide semiconductor field effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. The MOSFET consist of four- terminal device with source (S), gate (G), drain (D), and body (B) terminals. The MOSFET has common transistor in both digital and analogue circuits. The relatively small size of the MOSFET causes thousands of devices that can be fabricated into a single integrated circuit design.

Moore's law is the observation that over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years. The period often quoted as 18 months is due to Intel executive David House, who predicted that period for a doubling in chip performance. The law is named after Intel co- founder Gordon E. Moore, who described the trend in his 1965 paper. In 1958 until

(20)

2 1965, the paper noted that the number of components in integrated circuits had doubled every year from the invention of the integrated circuit and predicted that the trend would continue for at least ten years. His prediction has proven to be uncannily accurate, in part because the law is now used in the semiconductor industry to guide long-term planning and to set targets for research and development [1].

Nowadays, research is focused on obtaining higher speed, low power consumption and low cost devices as the MOSFET undergoes scaling down of the size. Due to this specifications, possible solutions and new devices structure like Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket has been discovered.

1.2 Problem Statement

An integrated circuit (IC) consist of passive and active components including transistor, diode, capacitor and resistor. Since the transistor could be made much smaller so that it was much more convenient to use. As a result, the transistor became the main amplifying devices in almost all electronic devices. The recent development of MOSFET has reached the progress that channel length goes shorter into nanometre scale.

Scaled MOSFETs must simultaneously satisfy following performances requirement such as suppression of the short-channel effect, small threshold voltage and increasing packaging density. As a result the improvement of MOSFET, Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket has been created to satisfy this requirement.

(21)

1.3 Objectives

The objectives of this project are:

(i) To design SDP-VMOSFET device by using TCAD tools (ATHENA, DevEdit and ATLAS).

(ii) To characterize the current-voltage of SDP-VMOSFET.

(iii) To compare the performance of SDP-VMOSFET with other MOSFET devices.

1.4 Scope of Project

Today much of the development of semiconductor devices and processes is done by computer modelling. The approach is called TCAD (Technology-Computer Aided Design). Use of TCAD tools reduce the development cost and shorten the development time. In a teaching environment, TCAD tools present unique possibilities in term of visualization of processing steps, description of the physical changes and understanding of the interrelation of the process variables as shown in Figure 1.1. Modelling of processes provides a way to interactively explore the fabrication process and study the effects of process. This tool will help to understand the semiconductor physics.

DevEdit

Structure files Runtime Output

ATHENA

ATLAS Device

Command File

Log Files

Solution Files

Tonyplot

Deckbuild

(22)

1.4.1 Introduction to TCAD

TCAD (Technology Computer Aided Design) is a branch of electronic design automation that models semiconductor fabrication and semiconductor device operation. The modelling of the fabrication is termed Process TCAD, while the modelling of the device operation is termed Device TCAD. Included are the modelling of process steps (such as diffusion and ion implantation) and modelling of the behaviour of the electrical devices based on fundamental physics.

1.4.2 ATHENA

ATHENA is a group of process simulation products that enables process and integration engineers to develop and optimize semiconductor manufacturing processes. ATHENA provides a platform for simulating ion implantation, diffusion, etching, deposition, lithography, oxidation, and silicidation of semiconductor materials.

1.4.3 ATLAS

ATLAS is a group of device simulation products enables device technology engineers to simulate the electrical, optical, and thermal behaviour of semiconductor devices. It provides a physics-based, modular, and extensible platform to analyse DC, AC, and time domain responses for all semiconductor based technologies in 2 and 3 dimensions.

(23)

1.4.4 DevEdit

DevEdit can be used to either create a device from scratch or to remesh or edit an existing device. DevEdit creates standard Silvaco structures that are easily integrated into Silvaco 2D or 3D simulators and other support tools.

1.5 Methodology

Start

Determine title, objectives, problem statement and scope of the project

Conduct literature study and collect the relevant information

Learn SILVACO TCAD tools (DevEdit, ATHENA and ATLAS)

Design the structure of vertical strained silicon incorporating with dielectric pocket (DevEdit &ATHENA)

Improvement and optimization

Device simulation (ATLAS)

Comparison analysis

No Accept

Yes Analysis

End

(24)

1.6 Project Structure Overview

This thesis consists of five chapters. The first chapter provides an introduction to this project to readers. This includes the objectives and importance of this project. The second chapter contains theories and information about other relevant researches conducted by research institutes and universities around the world.

The research activities and methods employed in this project will be discussed in detail in Chapter III. This chapter shows the flow of this project from the very beginning of the data collection until the acceptable results. It also introduced the TCAD tools to readers. Step by step explanations on the development of the Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket device structure are provided for extra information and knowledge.

Chapter IV shows the results that obtained from the process simulation of the device structure using the ATLAS tools. The data and results from the process are analysed and discussed in this chapter. The effects of the tested parameters are discussed and opinions are brought forward in this chapter. Comparison of various structures which is Vertical MOSFET, Vertical Strained Silicon MOSFET and Vertical MOSFET Incorporating Dielectric Pocket are also discussed.

Finally, Chapter V is the conclusion for this project and incorporates the overview of the results in this project. More importantly, this chapter compares the results analysis with the objectives of this research in order to determine the achievement of this research. Some suggestions to improve the MOSFET are discussed in this chapter for future improvement.

(1)

CHAPTER I

INTRODUCTION

1.1 Background

(2)

1965, the paper noted that the number of components in integrated circuits had doubled every year from the invention of the integrated circuit and predicted that the trend would continue for at least ten years. His prediction has proven to be uncannily accurate, in part because the law is now used in the semiconductor industry to guide long-term planning and to set targets for research and development [1].

1.2 Problem Statement

(3)

1.3 Objectives

The objectives of this project are:

(i) To design SDP-VMOSFET device by using TCAD tools (ATHENA, DevEdit

and ATLAS).

(ii) To characterize the current-voltage of SDP-VMOSFET.

(iii) To compare the performance of SDP-VMOSFET with other MOSFET devices.

1.4 Scope of Project

DevEdit

Structure files Runtime Output

ATHENA

ATLAS Device

Command File

Log Files

Solution Files

Tonyplot

Deckbuild

(4)

1.4.1 Introduction to TCAD

1.4.2 ATHENA

1.4.3 ATLAS

(5)

1.4.4 DevEdit

1.5 Methodology

Start

Determine title, objectives, problem statement and scope of the project

Conduct literature study and collect the relevant information

Learn SILVACO TCAD tools (DevEdit, ATHENA and ATLAS)

Design the structure of vertical strained silicon incorporating with dielectric pocket (DevEdit &ATHENA)

Improvement and optimization

Device simulation (ATLAS)

Comparison analysis

No Accept

Yes Analysis

End

(6)

1.6 Project Structure Overview

Design And Characterization Of Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket By Using TCAD Tools.

Dokumen yang terkait

Improving the Dielectric Properties of High Density Polyethylene by Incorporating Clay-Nanofiller

Design And Characterization Of 20NM SOI MOSFET Doping Abruptness Dependent.

Characterization And Optimization Of Planar Power MOSFET Device.

Compatibility Analysis of Silicon Nitride and Silicon Dioxide on HCI induced LDD MOSFET.

Characterization Of Silicon On Insulator (SOI) Mosfet Using TCAD Tools.

Virtual Fabrication Process Of Planar Power MOSFET Using Silvaco TCAD Tools.

Design And Characterization Of Vertical MOSFET.

Design And Characterization Of Biaxial Strained Silicon N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor (Mosfet).

Design And Characterization Of Silicon-On-Insulator (SOI) Metal - Oxide- Semiconductor Field Effect Transistor (MOSFET).

Bohr strained silicon 102703

Dukungan

Links

Design And Characterization Of Vertical Strained Silicon MOSFET Incorporating Dielectric Pocket By Using TCAD Tools.

Dokumen yang terkait

Improving the Dielectric Properties of High Density Polyethylene by Incorporating Clay-Nanofiller

Design And Characterization Of 20NM SOI MOSFET Doping Abruptness Dependent.

Characterization And Optimization Of Planar Power MOSFET Device.

Compatibility Analysis of Silicon Nitride and Silicon Dioxide on HCI induced LDD MOSFET.

Characterization Of Silicon On Insulator (SOI) Mosfet Using TCAD Tools.

Virtual Fabrication Process Of Planar Power MOSFET Using Silvaco TCAD Tools.

Design And Characterization Of Vertical MOSFET.

Design And Characterization Of Biaxial Strained Silicon N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor (Mosfet).

Design And Characterization Of Silicon-On-Insulator (SOI) Metal - Oxide- Semiconductor Field Effect Transistor (MOSFET).

Bohr strained silicon 102703

Dokumen yang Anda mencari sudah siap untuk unduhkan