ASMs, Implicit Verilog and One-hot Designs: The VITO approach

  Outline Outline

  Structure and Behavior

  ASMs, Implicit Verilog and

  Algorithmic State Machines

  One-hot Designs:

  Basic Intro to Verilog

  The VITO approach

   Portlist, input and output always for (C-like) behavioral code

  Mark G. Arnold

   Implicit Verilog Blocking (=) and Nonblocking Assignment (<=) Wait for clock event @(posedge sysclk)

  University of Manchester Institute of Science and Technology

  One-hot controllers Verilog Implicit To One-hot (VITO) preprocessor Examples _{Copyright by Mark Arnold, 2002 Copyright by Mark Arnold, 2002} Silly

  Y

   Power (X )

  Structure and Behavior Structure and Behavior Algorithmic State Machine (ASM) Algorithmic State Machine (ASM)

  Structure How to build system? Ex: Unit A is connected to Unit B Rectangles describe states. System clock (sysclk)

  Unit A Unit B

STATE_NAME

  determines when transitions occur. Nice to give the state a name. Behavior What does system do? Ex: What algorithm does unit A use? Algorithmic State Machine is one way. Behavioral HDLs are another: Verilog or

  VHDL

  … … _{Copyright by Mark Arnold, 2002 Copyright by Mark Arnold, 2002} other states Algorithmic State Machine (ASM) Algorithmic State Machine (ASM) Algorithmic State Machine (ASM) Algorithmic State Machine (ASM)

  Inside of rectangle are

STATE_NAME

  Moore commands that happen Moore action anytime the state is entered action

  (Moore)

  1 Diamond comes after cond

  rectangle. It says go to different states depending on condition indicated by hardware status signal (perhaps a comparator)

  … … … … other states other states _{Copyright by Mark Arnold, 2002 Copyright by Mark Arnold, 2002}

STATE_NAME

STATE_NAME

1 Moore

  Silly Example Silly Example Silly Machine sysclk reset

   Two states:

  cond

   Two input ports: sysclk is the system clock reset (ignored for the moment) Two output ports: a (two bits wide) b (two bits wide)

  2 Structure

  2

  / a / b

  Copyright by Mark Arnold, 2002

  Silly Example Silly Example a <= b b <= a a <= 1 b <= 3

  Verilog and VHDL several kinds of assignment: Evaluate b Change a Blocking assignment Now Now a = b; Nonblocking assignment Now Future a <= b; Nonblocking assignment is a better model of how clocked flip flops work. Let’s use this in an ASM chart:

  Copyright by Mark Arnold, 2002

  Let’s ignore ovals, and concentrate on Moore machines.

  Algorithmic State Machine (ASM) Algorithmic State Machine (ASM) … … other states

  1 Moore action

  cond

  Optional oval comes after diamond. It says commands that happen anytime only when the state is entered and the condition is true. (Mealy) _{Copyright by Mark Arnold, 2002}

  Algorithmic State Machine (ASM) Algorithmic State Machine (ASM) … … other states

  action Mealy action

  Kinds of Assignments Kinds of Assignments Copyright by Mark Arnold, 2002

INIT SWAP

INIT SWAP

  Silly Machine sysclk reset

  / a / b

  2

  2 What is the output ?

   a b

  INIT x x

  INIT initializes a and b SWAP interchanges them Copyright by Mark Arnold, 2002

  2

  / a / b

2 Behavior:

  Copyright by Mark Arnold, 2002 Silly Example Silly Example a <= b b <= a a <= 1 b <= 3

  Silly Machine sysclk reset Copyright by Mark Arnold, 2002 Silly Example Silly Example a <= b b <= a a <= 1 b <= 3

  INIT SWAP Silly Machine sysclk reset

  2 Blocking = doesn’t work:

  INIT x x SWAP 1 3

  INIT

  3

  3

  3 SWAP 3 3 3 ...

  Copyright by Mark Arnold, 2002 Silly Example Silly Example a = b b = a a = 1 b = 3

  INIT SWAP Silly Machine sysclk reset

  / a / b

  2

   a b

  2 Blocking = doesn’t work:

  INIT x x SWAP 1 3

  INIT

  3

  3

  3 SWAP 3 3 3 ...

  VITO requires <= not = _{Copyright by Mark Arnold, 2002} module example(sysclk,reset,a,b); endmodule Start with the structure.

  The portlist shows all the inputs and outputs Silly Example in Implicit Silly Example in Implicit Verilog Verilog

  Silly Machine sysclk reset

  / a / b

  2

   a b

  2

  / a / b

   a b

  2

  2 What is the output ?

   a b

  INIT x x SWAP 1 3 Copyright by Mark Arnold, 2002

  Silly Example Silly Example a <= b b <= a a <= 1 b <= 3

  INIT SWAP Silly Machine sysclk reset

  / a / b

  2

  2 What is the output ?

  INIT x x SWAP 1 3

  / a / b

  INIT 3 1 Copyright by Mark Arnold, 2002

  Silly Example Silly Example a <= b b <= a a <= 1 b <= 3

  INIT SWAP Silly Machine sysclk reset

  / a / b

  2

  2 What is the output ?

   a b

  INIT x x SWAP 1 3

  INIT 3 1 SWAP 1 3 ... _{Copyright by Mark Arnold, 2002} Silly Example Silly Example a = b b = a a = 1 b = 3

  INIT SWAP Silly Machine sysclk reset

  2 Copyright by Mark Arnold, 2002

  module example(sysclk,reset,a,b); input sysclk,reset; endmodule Have to specify which ones are inputs...

  2 _{Copyright by Mark Arnold, 2002}

  Sequential execution means implicit state transitions always handles the loop at the bottom Silly Example in Implicit Silly Example in Implicit Verilog Verilog

   end endmodule

   @(posedge sysclk); //INIT @(posedge sysclk); //SWAP

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; always begin

  INIT Copyright by Mark Arnold, 2002

  In implicit style, each state starts with @(posedge sysclk) Silly Example in Implicit Silly Example in Implicit Verilog Verilog

   end endmodule

   @(posedge sysclk); //INIT

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; always begin

  Copyright by Mark Arnold, 2002

  always is a infinite loop used for behavioral modeling of hardware; begin end similar to { } in C Silly Example in Implicit Silly Example in Implicit Verilog Verilog

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; always begin end endmodule

  2

  Silly Example in Implicit Silly Example in Implicit Verilog Verilog Silly Machine sysclk reset

  / a / b

  Silly Example in Implicit Silly Example in Implicit Verilog Verilog Silly Machine sysclk reset

  The outputs are generated in registers that are local to the state machine .

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; endmodule

  2 Copyright by Mark Arnold, 2002

  2

  / a / b

  Silly Example in Implicit Silly Example in Implicit Verilog Verilog Silly Machine sysclk reset

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; endmodule and outputs. The [1:0] means two bits wide.

  2 _{Copyright by Mark Arnold, 2002}

  2

  / a / b

INIT SWAP

INIT SWAP

INIT SWAP

  Ports :

   always begin c =0; p =1; p =1; while( while( c!=y c!=y ) ) begin begin c =c+1; p =p*x; p =p*x; end end while(1) while(1) begin begin end end end Example of machine needing WHILE

   = x * x * … * x using a loop y times For implicit Verilog, Need an always begin end to start behavioral code

  y

  Compute x

  Copyright by Mark Arnold, 2002

   = x * x * … * x using a loop y times Here’s this algorithm in C:

  y

  Compute x

   { c =0; p =1; p =1; while( while( c!=y c!=y ) ) { { c =c+1; p =p*x; p =p*x; } } while(1) while(1) { { } } } Example of machine needing WHILE

  Example of machine needing WHILE Copyright by Mark Arnold, 2002

  c local loop counter

  Internal register:

  x,y input values (8 bits each) p output product (8 bits) sysclk system clock reset resetting signal

  Copyright by Mark Arnold, 2002

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; always begin

  y

   Compute x

  Goal:

  The wonderful WHILE The wonderful WHILE Copyright by Mark Arnold, 2002

  For many mathematical algorithms, WHILE is natural Same condition tested from two states: From entry state From bottom state of loop Advantage: don't describe condition twice

  Copyright by Mark Arnold, 2002

  Non-blocking assignment allows the parallel swap that takes effect at the next clock Silly Example in Implicit Silly Example in Implicit Verilog Verilog a <= b b <= a a <= 1 b <= 3

  end endmodule

   @(posedge sysclk); //INIT a <= 1; b <= 3; @(posedge sysclk); //SWAP a <= b; b <= a;

  module example(sysclk,reset,a,b); input sysclk,reset; output [1:0] a,b; reg [1:0] a,b; always begin

  Copyright by Mark Arnold, 2002

  The <= means non-blocking assignment: 1 goes into a and 3 goes into b at the rising edge of next clock Silly Example in Implicit Silly Example in Implicit Verilog Verilog a <= 1 b <= 3

  end endmodule

   @(posedge sysclk); //INIT a <= 1; b <= 3; @(posedge sysclk); //SWAP

   = x * x * … * x using a loop y times Special case: x = 1 taken care of by WHILE Copyright by Mark Arnold, 2002 always begin @(posedge sysclk) c =0; @( @( posedge sysclk posedge sysclk ) ) p =1; p =1; while( while( c!=y c!=y ) ) begin begin @( @( posedge sysclk posedge sysclk ) ) c =c+1; c =c+1; @( @( posedge sysclk posedge sysclk ) ) p =p*x; p =p*x; end end while(1) while(1) begin begin @( @( posedge sysclk posedge sysclk ) ) end end end Example of machine needing WHILE

  Compute x

  1 c <=c+1 p <= p*x Example of machine needing WHILE always begin @(posedge sysclk) c<=0; @( @( posedge sysclk posedge sysclk ) ) p<=1; p<=1; while( while( c!=y c!=y ) ) begin begin @(posedge sysclk) c<=c+1; @( @( posedge sysclk posedge sysclk ) ) p<=p*x; p<=p*x; end end while(1) while(1) begin begin @( @( posedge sysclk posedge sysclk ) ) end end end

  1 c <=c+1 p <= p*x

  \/ D Q \/ D Q Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  With the one-hot method, each state gets a flip flop ^{Copyright by Mark Arnold, 2002}

  1 c <=c+1 p <= p*x

  Copyright by Mark Arnold, 2002 \/ D Q Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  Here’s where VITO comes in

  1 c <=c+1 p <= p*x Example of machine needing WHILE always begin @(posedge sysclk) c<=0; @( @( posedge sysclk posedge sysclk ) ) p<=1; p<=1; while( while( c!=y c!=y ) ) begin begin @(posedge sysclk) c<=c+1; @( @( posedge sysclk posedge sysclk ) ) p<=p*x; p<=p*x; end end while(1) while(1) begin begin @( @( posedge sysclk posedge sysclk ) ) end end end _{Copyright by Mark Arnold, 2002} GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  y

  Copyright by Mark Arnold, 2002 GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

   = x * x * … * x using a loop y times For implicit Verilog, Need an always begin end to start behavioral code Need @(posedge …) for each state Need <= rather than = (careful: <= not same as = )

  y

  Compute x

   always begin @(posedge sysclk) c<=0; @( @( posedge sysclk posedge sysclk ) ) p<=1; p<=1; while( while( c!=y c!=y ) ) begin begin @( @( posedge sysclk posedge sysclk ) ) c<=c+1; c<=c+1; @( @( posedge sysclk posedge sysclk ) ) p<=p*x; p<=p*x; end end while(1) while(1) begin begin @( @( posedge sysclk posedge sysclk ) ) end end end Example of machine needing WHILE

   = x * x * … * x using a loop y times For implicit Verilog, Need an always begin end to start behavioral code Need @(posedge …) for each state _{Copyright by Mark Arnold, 2002}

  The D input represents the transition from the last state Copyright by Mark Arnold, 2002 \/ D Q \/ D Q Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  1 c <=c+1 p <= p*x

  1 c <=c+1 p <= p*x

  1 c <=c+1 p <= p*x

  c!=y \/ D Q \/ D Q \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  BLUE follows unconditionally from WHITE; DEMUX shared by RED and BLUE because of OR ^{Copyright by Mark Arnold, 2002}

  1 c <=c+1 p <= p*x

  Copyright by Mark Arnold, 2002 c!=y \/ D Q \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  When cond true, start loop

   1 1 0 1 _{Copyright by Mark Arnold, 2002} c!=y \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  Joining of two possible transitions require OR gate ^{Copyright by Mark Arnold, 2002}

  Truth Table for Demux in c!=y out0 out1 0 0 1 0 0 1 1 0

  Decision uses a demux: no more than one output active

  1 c <=c+1 p <= p*x

  Copyright by Mark Arnold, 2002 c!=y \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  Decision uses a demux:

  1 c <=c+1 p <= p*x

  c!=y \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  Get trapped in state GREEN when c = = y

  ( ( c!=y c!=y ) ) begin @(posedge... c<=c+1; c<=c+1; @(posedge... p<=p*x; p<=p*x; end while(1) begin @(posedge... end end

  1 y compare y y!=c Example Example datapath datapath always begin @(posedge... c<=0; c<=0; @(posedge... p<=1; p<=1; while

  1 MUX

  1 p MUX

  BLUE new_p D Q >

• * RED RED

• * RED RED

  1

  1 MUX

  BLACK WHITE new_c D Q > c MUX

  ( ( c!=y c!=y ) ) begin @(posedge... c<=c+1; c<=c+1; @(posedge... p<=p*x; p<=p*x; end while(1) begin @(posedge... end end _{Copyright by Mark Arnold, 2002}

  1 y compare y y!=c Example Example datapath datapath always begin @(posedge... c<=0; c<=0; @(posedge... p<=1; p<=1; while

  1 MUX

  1 p MUX

  BLUE new_p D Q >

  1

  BLACK WHITE new_c D Q > c MUX

  1 MUX

  Copyright by Mark Arnold, 2002

  RED,BLACK,BLUE, WHITE are mutually exclusive; they control datapath c!=y output from datapath

  1 c <=c+1 p <= p*x sysclk sysclk reset reset

  c!=y \/ D Q \/ D Q \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  RED,BLACK,BLUE, WHITE are mutually exclusive; they control datapath ^{Copyright by Mark Arnold, 2002}

  1 c <=c+1 p <= p*x sysclk sysclk reset reset

  Copyright by Mark Arnold, 2002 c!=y \/ D Q \/ D Q \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  Set BLACK, clear others with async reset signal

  1 c <=c+1 p <= p*x sysclk sysclk reset reset

  c!=y \/ D Q \/ D Q \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

  Anything else needed? ^{Copyright by Mark Arnold, 2002}

  1 c <=c+1 p <= p*x sysclk sysclk All 5 flip flops need sysclk.

  Copyright by Mark Arnold, 2002 c!=y \/ D Q \/ D Q \/ D Q \/ D Q \/ D Q DEMUX 0 1 Example one-hot controller Example one-hot controller GREEN p <= 1 c <= 0 c!=y BLACK RED WHITE BLUE

• + 1
• + 1

• * RED RED
• * RED RED
• + 1
• + 1

  / M / M

  1 y compare y y!=c Example Example datapath datapath always begin @(posedge... c<=0; c<=0; @(posedge... p<=1; p<=1; while

  ( ( c!=y c!=y ) ) begin @(posedge... c<=c+1; c<=c+1; @(posedge... p<=p*x; p<=p*x; end while(1) begin @(posedge... end end _{Copyright by Mark Arnold, 2002}

  BLACK WHITE new_c D Q > c MUX

  1 MUX

  1

  RED BLUE new_p D Q >

  

1

p MUX

  1 MUX

  1

y

compare y y!=c Example Example datapath datapath

  / M

  1 p MUX

• * RED
• * RED

  / M

  / M

  / M

  / M

  / M

  The busses are M bits wide

  Copyright by Mark Arnold, 2002 module vito_power(sysclk,reset,x,y,p); input sysclk,reset; input [`M:0] x,y; output [`M:0] p; wire [`M:0] x,y; reg [`M:0] p,c; always begin @(posedge sysclk); //BLACK c <= 0; @( @( posedge sysclk posedge sysclk ); //RED ); //RED p <= 1; p <= 1; while ( while ( c != y c != y ) ) begin begin @(posedge sysclk); //WHITE c <= c + 1; @( @( posedge sysclk posedge sysclk ); //BLUE ); //BLUE p <= p * x; p <= p * x; end end forever forever begin begin @( @( posedge sysclk posedge sysclk ); //GREEN ); //GREEN end end end endmodule ^{Copyright by Mark Arnold, 2002}

  Verilog Implicit To One-hot Verilog synthesis preprocessor Works with any synthesis tool Accepts implicit and explicit style Leaves explicit block(s) alone Converts implicit block(s) to one-hot Vendor independent, freely available

  1 MUX

  1

  RED BLUE new_p D Q >

  BLACK WHITE new_c D Q > c MUX

  Copyright by Mark Arnold, 2002

  BLACK WHITE new_c D Q > c MUX

  1 MUX

  1

  BLUE new_p D Q >

  1 p MUX

  1 MUX

  1 y compare y y!=c Example Example datapath datapath always begin @(posedge... c<=0; c<=0; @(posedge... p<=1; p<=1; while

  ( ( c!=y c!=y ) ) begin @(posedge... c<=c+1; c<=c+1; @(posedge... p<=p*x; p<=p*x; end while(1) begin @(posedge... end end _{Copyright by Mark Arnold, 2002}

  1 MUX

  1

  BLUE new_p D Q >

  

1

p MUX

  1 MUX

  1

y

compare y y!=c Example Example datapath datapath always begin @(posedge... c<=0; c<=0; @(posedge... p<=1; p<=1; while

  ( ( c!=y c!=y ) ) begin @(posedge... c<=c+1; c<=c+1; @(posedge... p<=p*x; p<=p*x; end while(1) begin @(posedge... end end

• + 1
• + 1

  Copyright by Mark Arnold, 2002

  BLACK WHITE new_c D Q > c MUX

  1 MUX

  Where is VITO? Where is VITO? www.verilog.vito.com What is VITO? What is VITO?

  Copyright by Mark Arnold, 2002 Verilog to synthesize Verilog source synthesis tool generate architecture unchanged statements and comments implicit always parser generate controller

  VITO merge

  VITO

  VITO Organization Organization Copyright by Mark Arnold, 2002

  Synthesis tool often successful in optimizing VITO

  Comparison of different implicit design flows

  Implicit tool Synopsys

  VITO Synthesis tool Synopsys Synopsys Optimization tool MINC MINC Technology Vantis Vantis CLBs 363 345

  Comparison of explicit versus implicit for Power (x

  y

  )

  Style explicit implicit Design entry graphic ASM textual Verilog Tool VeriBest

  VITO Synthesis tool VeriBest VeriBest Technology Xilinx Xilinx CLBs 337 323 Using VITO in Synthesis