Professor Mike Schulte Computer Architecture ECE 201
Lecture 9: Single Cycle Control Professor Mike Schulte Computer Architecture ECE 201 A Single Cycle Datapath underlined ) ° We have everything except control signals (
- Today’s lecture will look at how to generate the control signals
Instruction<31:0>
<21:25> <16:20> <11:15> nPC_sel
<0:15> Instruction Fetch Unit
Rd Rt Clk
RegDst
1 Mux Rt Rs Rd Imm16
Rs Rt
RegWr ALUctr
5
5
5 MemtoReg busA
Zero MemWr
Rw Ra Rb
ALU
busW
32
32 32-bit
32 Registers Mux busB
32 Mux Clk
32
32 Extender
1 WrEn Adr
1 Data In
32 Data imm16
32
16 Memory Clk
ALUSrc ExtOp
RTL: The Add Instruction
31
26
21
16
11
6
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
° add rd, rs, rt Fetch the instruction
- mem[PC]
from memory The actual operation
- R[rd] <- R[rs] + R[rt]
Calculate the next
- PC <- PC + 4
instruction’s address Instruction Fetch Unit at the Beginning of Add ° Fetch the instruction from Instruction memory:
Instruction <- mem[PC] ° Done for all instructions => Don’t need special control bits
Inst
Instruction<31:0>
Memory
Adr
nPC_sel
4 Adder
00 Mux PC Adder PC
Clk
Ext imm16
Clk
<21:25> <16:20> <11:15> <0:15>
The Single Cycle Datapath during Add/Sub
Zero
Instruction<31:0>
° R[rd] <- R[rs] op R[rt]
1
1
1
Imm16 Rd Rs Rt
32 MemWr = 0
op rs rt rd shamt funct
6
11
16
21
26
31
ALU Instruction Fetch Unit
Data Memory
° PC <- PC + 4
32 32-bit Registers
32 ALUctr = Add Clk busW
RegWr = 1
32
32 busA 32 busB
5
5
5 Rw Ra Rb
Rs Rt
32 Adr
Rt Rd
RegDst = 1 Extender Mux Mux
32
16 imm16
ALUSrc = 0 ExtOp = x Mux
MemtoReg = 0
Clk Data In
WrEn
nPC_sel= +4 Instruction Fetch Unit at the End of Add
- This is the same for all instructions except Branch and Jump
Adr
Inst Memory Adder Adder PC
Clk
4 nPC_sel = +4 imm16
Instruction<31:0>
00 Mux
The Single Cycle Datapath during Or Immediate
31
26
21
16
op rs rt immediate ° R[rt] <- R[rs] or ZeroExt[Imm16]
Instruction<31:0>
nPC_sel= +4 <21:25> <16:20> <11:15> <0:15>
Instruction Fetch Unit
Rd Rt Clk
RegDst = 0
1 Mux Rt Rs Rd Imm16
Rs Rt
ALUctr = Or RegWr = 1
5
5
5 MemtoReg = 0 busA Zero MemWr = 0
Rw Ra Rb busW ALU
32
32 32-bit
32 Registers
Mux
busB
32 Mux Clk
32
32 Extender
1 WrEn Adr
1 Data In
32 Data imm16
32
16 Memory Clk
ALUSrc = 1 ExtOp = 0 The Single Cycle Datapath during Load
31
26
21
16
op rs rt immediate ° R[rt] <- Data Memory {R[rs] + SignExt[imm16]}
Instruction<31:0>
<21:25> <16:20> <11:15> nPC_sel= +4
<0:15> Instruction Fetch Unit
Rd Rt Clk
RegDst = 0
1 Mux Rt Rs Rd Imm16
Rs Rt
RegWr = 1 = Add
5
5
5 MemtoReg = 1 busA
Zero MemWr = 0
Rw Ra Rb
ALU
busW
32
32 32-bit
32 Registers Mux busB
32 Mux Clk
32 Extender
1 WrEn Adr
1 Data In
32 Data imm16
32
32
16 Memory Clk
ALUSrc = 1 ExtOp = 1
The Single Cycle Datapath during Store
31
26
21
16
op rs rt immediate ° Data Memory {R[rs] + SignExt[imm16]} <- R[rt]
Instruction<31:0>
nPC_sel= +4 <21:25> <16:20> <11:15> <0:15>
Instruction Fetch Unit
Rd Rt Clk
RegDst = x
1 Mux ALUctr
Rt Rs Rd Imm16 Rs Rt
RegWr = 0
= Add
5
5
5 MemtoReg = x busA Zero MemWr = 1
Rw Ra Rb busW ALU
32
32 32-bit
32 Registers
Mux
busB
32 Mux Clk
32
32 Extender
1 WrEn Adr
1 Data In
32 Data imm16
32
16 Memory Clk
ALUSrc = 1 ExtOp = 1 The Single Cycle Datapath during Branch
31
26
21
16
op rs rt immediate ° if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0
Instruction<31:0>
<21:25> <16:20> <11:15> nPC_sel= “Br”
<0:15> Instruction Fetch Unit
Rd Rt Clk
RegDst = x
1 Mux Rt Rs Rd Imm16
Rs Rt RegWr = 0
Subtract
5
5
5 MemtoReg = x busA Zero MemWr = 0
Rw Ra Rb
ALU
busW
32
32 32-bit
32 Registers Mux busB
32 Mux Clk
32
32 Extender
1 WrEn Adr
1 Data In
32 Data imm16
32
16 Memory Clk
ALUSrc = 0 ExtOp = x
Instruction Fetch Unit at the End of Branch
31
26
21
16
op rs rt immediate ° if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ;
Inst else PC = PC + 4
Memory Instruction<31:0>
Adr
nPC_sel See book for what the datapath and control looks like for jump instructions.
4 Adder
Compared to book our processor also
00 Mux supports the ORI instructions. PC Adder
Clk
imm16 Step 4: Given Datapath: RTL -> Control
Instruction<31:0>
<26:31> <0:5> <21:25> <16:20> <11:15> <0:15>
Inst Memory
Adr
Op Fun
Rt Rs Rd Imm16
Control nPC_sel ALUctr MemWr MemtoReg RegWr RegDst ExtOp ALUSrc
Equal DATA PATH
A Summary of the Control Signals add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr<2:0>
1 Add x 1 x
The Concept of Local Decoding R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Jump ExtOp ALUop<N:0>
1
1 x “R-type”
1
1 Or
1
1
1
1
I-type J-type add, sub ori, lw, sw, beq jump func op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
1 Add x x x
Subtract x x x 1 x xxx
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 Main Control
op
6 ALU
Control (Local)
func N
6 ALUop ALUctr
Appendix A See 10 0000 10 0010 We Don’t Care :-)
op rs rt
immediate
R-type1
1 Add x 1 x
1 x Add
1
1 x Subtract
1
1 Or
1
1
1
1
31
1 Add x x
1 x Subtract x x x 1 x xxx
op target address op rs rt rd shamt funct
6
11
16
21
26
3 ALU
The Encoding of ALUop
func
ALU
op
6 ALUctr
Main Control
ALUop
6 Control
3
(Local)
N
° In this exercise, ALUop has to be N=2 bits wide to represent:
- (1) “R-type” instructions
- “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, and (4) Subtract
° To implement the full MIPS ISA, ALUop has to be 3 bits to represent:
- (1) “R-type” instructions
- “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, (4) Subtract (5) And (6) Set on <
R-type ori lw sw beq jump
ALUop (Symbolic) “R-type” Or Add Add Subtract xxx ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxxThe Decoding of the “func” Field
func
ALU
op
6 ALUctr
Main Control
ALUop
Control
6
3
(Local)
N
R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
31
26
21
16
11
6 R-type op rs rt rd shamt funct Our processor only implements subset of
Get func from back of book for R-type operations
funct<5:0> Instruction Operation ALUctr<2:0> ALU Operation 10 0000 add
000 Add
10 0010 subtract
001 Subtract
10 0100 and
010 And
10 0101 or
110 Or
10 1010 set-on-less-than
111 Set-on-less-than
The Truth Table for ALUctr<2> funct<3:0> Instruction Op.
0000 add
R-type ori lw sw beq 0010 subtract ALUop
“R-type” Or Add Add 0100 and
(Symbolic) Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 0101 or
0 01 1010 set-on-less-than
ALUop func ALU ALUctr
Operation
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>x x x x Add
1
x 1 x x x x Subtract
1
1 1 x x x x x Or 1 1 x x Add
1
1 x x
1 Subtract
1
1 1 x x
1 And 1 x x
1
1 Or
1
1 x x
1
1 Set on <
1
1
1 This control is for more R-type instructions than our processor, but fewer than the entire MIPS ISA.
The Logic Equation for ALUctr<2> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2> x 1 x x x x
1 1 x x
1
1 1 x x
1
1
1 !ALUop<2> & ALUop<0>
° ALUctr<2> =
- + ALUop<2> & func<1>
1 ° ALUctr<1> = !ALUop<2> & !ALUop<1>
1
1
1
1 1 x x
1
1 1 x x
1 1 x x
1 ALUctr<1> x 1 x x x x
ALUop func bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> bit<3> x x x x
1 The Logic Equation for ALUctr<1>
1
1
1 Set on <
1
1 x x
1 Or
The Truth Table for ALUctr <1> ALUop func bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> bit<3> x x x x
1
ALUctr ALU
Operation
Add
1 bit<2> bit<1> bit<0> x 1 x x x x Subtract
1
1
1 x x x x x Or
1 x x Add
1
1 1 x x
1 Subtract
1
1
1 x x
1 And 1 x x
- + ALUop<2> & func<2>
The Truth Table for ALUctr<0> ALUop func bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> bit<3>
1 Or
!ALUop<2> & ALUop<1> + ALUop< 2> & func<2> & func<0> + ALUop<2> & func<3>
1 ° ALUctr<0> =
1
1
1 1 x x
1
1
1 1 x x
1 x x x x x
1 The Logic Equation for ALUctr<0> ALUop func bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> bit<3> ALUctr<0>
1
1
1
1 1 x x
1
x x x x
1 x x x x x Or
ALUctr ALU Operation Add
1
bit<2> bit<1> bit<0>
x 1 x x x x Subtract
1
1
1
1 x x
1 x x Add
1 1 x x
1 Subtract
1
1 1 x x
1 And
1 Set on <
The ALU Control Block
func
ALU
6 ALUctr
Control
ALUop
3
(Local)
3
!ALUop<2> & ALUop<0> ° ALUctr<2> =
- + ALUop<2> & func<1> !ALUop<2> & !ALUop<1>
° ALUctr<1> = ALUop<2> & func<2> + !ALUop<2> & ALUop<1>
° ALUctr<0> = ALUop< 2> & func<2> & func<0> + + ALUop<2> & func<3> The “Truth Table” for the Main Control
RegDst func ALUSrc ALUctr
ALU
op
6 Main
3
: Control Control
6 ALUop
(Local)
3
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst
1 x x x
ALUSrc
1
1 1 x
MemtoReg
1 x x x
RegWrite
1
1
1 MemWrite
1 Branch
1 Jump
1 ExtOp x
1 1 x x
ALUop (Symbolic) “R-type” Or Add Add Subtract xxx ALUop <2>
1 x
ALUop <1>
1 x
ALUop <0>
1 x
The “Truth Table” for RegWrite op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump
RegWrite
1
1
1
° RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw)
op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . . . . . . .
<0> <0> <0> <0> <0> op<0>
R-type ori lw sw beq jump RegWrite PLA Implementation of the Main Control
op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . . . . . . .
<0> <0> <0> <0> <0> op<0>
R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0>
Putting it All Together: A Single Cycle Processor
ALUop
ALU
ALUctr
3 RegDst func
Control
op
3 Main Instr<5:0>
6 ALUSrc
Control
6 Instr<31:26>
:
Instruction<31:0> nPC_sel <21:25> <16:20> <11:15>
<0:15> Instruction Fetch Unit
Rd Rt Clk
RegDst
1 Mux Rt Rs Rd Imm16
Rs Rt RegWr ALUctr
5
5
5 MemtoReg busA Zero MemWr
Rw Ra Rb busW ALU
32
32 32-bit
32 Registers
Mux
busB
32 Mux Clk
32
32 Extender
1 WrEn Adr
1 Data In
32 Data imm16
32
16 Memory Instr<15:0>
Clk ALUSrc
ExtOp
An abstract view of the critical path - load instruction Critical Path (Load Operation) =
PC’s Clk-to-Q +
Instruction Memory’s Access Time +Ideal Register File’s Access Time + Instruction Instruction
ALU to Perform a 32-bit Add + Memory Data Memory Access Time + Rd Rs Rt Imm
Setup Time for Register File Write +
5
5
5
16 Instruction
Clock Skew Address
A Data
32 Rw Ra Rb Address
32 ALU
Ideal
32
32 32-bit Data PC Registers
Data
Memory
B In
Next Address
Clk Clk
32 Clk
Worst case delay for load is much longer than needed for all other instructions, yet this sets the cycle time.