DMA (Direct Memory Access) CONTROLLER

Basics & Features Of DMA

  >> The activity involved in transferring a byte or word over the system bus is called a bus cycle.

  >> During bus cycle one component must be the master – which will have complete control over the bus. Taking control of the bus for a bus cycle is called cycle stealing.

  Steps to Perform DMA

1) Interface of the external Device (DMA requesting I/O device)

  activates the DREQ line high to send a request for DMA service to the controller.

  

2) If the input of the DMA controller is unmasked, the DMA controller

sends a bus request to the microprocessor through its HOLD pin.

  

3) After the current bus cycle is complete the microprocessor will

  4) After receiving HLDA, DMA controller sends out a signal and takes the full control of Data, Address and Control buses. 5) DMA controller puts the content of the address register on the address bus.. 6) DMA controller sends a DACK signal to the interface to tell it to put data on data bus. 7) At the same time DMA controller asserts appropriate signals to IOR/IOW and MEMW/MEMR pins. 8) Bytes of data are transferred to the memory location indicated by

  Block Diagram of DMA controller (Ref. D.V. Hall)

DMA controller

• A DMA controller is capable of becoming the bus master and supervising a transfer between an I/O interface and memory.
• A DMA controller is designed to service one or more I/O interfaces and each interface is connected to the controller by a set of conductors.
• A portion of a DMA controller for servicing a single interface is called a channel.

  

Description of the parts of 8237

Mode Register: >>Bit 5: indicates whether the content of address register are to be

incremented (0) or decremented (1) after each transfer .Thus it determines

the order in which data are stored in memory. >> Bit 4: If 1 auto-initialization is enabled. (When the controller is initialized, the address register is filled with the

  

Description of the parts of 8237

Control Register: >>Bit 0: Set to 1 to enable memory to memory transfer.

  In this case if Bit 1=1 , the source address is held constant. >> Bit 2: It is used for enabling (0) and disabling (1) controllers to accept DMA request.

  

>> Bit 4: Determine whether the priority is fixed or rotating.(If Bit 4 is 1 and

  Description of the parts of 8237 Status Register:

Lower 4 bits indicates the states of the terminal count of the four channels

and upper 4 bits indicates the current presence or absence of DMA request. For the lower 4 bits, a 1 in bit n indicates that channel n is active. For the upper 4 bits, a 1 in bit n+4 indicates the presence of request on

  Description of the parts of 8237 Request Flag & Mask Flag: Setting the Request flag for a channel has the same effect as the DREQ pin becoming active and it is cleared when EOP goes active.

  If the mask flag is set, it disables the channel so that DMA requests are

not recognized. If a channel is not programmed for auto-initialization, then

  

Memory to memory transfers

Temporary Register:

  Channel 0 ‘s current address and count registers are used as • source addressing and counting Channel 1’s current address and count registers are used for • destination address and counting Bytes are brought in from the source memory area into the • temporary register in 8237 and then outputting it to destination memory area.

  

Description of the parts of 8237

The addressing of these various registers is done via CS, IOR,IOW and A3-A0 lines.

  ¾ CS=0 indicates that the controller is being accessed. ¾ A3=0 when address or count register is addressed. ¾ A3=1 when control or status is being accessed.

  What’s going on..

  8237-

  When the controller is master it must supply the address. • >>It puts lower order address byte on A7-A0 >> the higher address byte on DB7-DB0 >> and sets AEN to high Shortly after AEN is 1 (when active) a pulse is sent out over ADSTB • pin.This pulse is used to strobe the upper byte of the address into the 8282 address latch connected to A15-A8 lines. It also disables the latches connected to CPU’s A19-A8 and AD7- •

  Other features… EOP: is bidirectional. •

  >>The count going zero causes a negative pulse on EOP which can be used either as an interrupt request or by the device interface.

  >>Again the interface can send a low on this pin to 8237 to suspend the block transfer.

  >> In either case, a Low on the EOP will result in the block transfer being suspended.After the suspension the block transfer may

Modes (determined by mode register of each channel)

• Single : After each transfer controller releases bus to CPU for at least one bus cycle. Then tests DREQ and as soon as DREQ active steals another bus cycle.
• Block :The bus is released only after entire block transfer.

  Flowchart of 8237 DMA controller activity by states The 8237 timing can be divided into SI,S0,S1,S2,S3,S4 and SW states. >> Between transfers the controller is in idle SI states.

>> during each SI state the DREQ lines are tested to determine if a channel

is requesting DMA transfer.

  

>> If there is an active DREQ input, HRQ is activated and S0 state is

entered.

  

>> S0 states are repeated until a HLDA signal is returned and then a