lecture 03 sequential logic

Building a Modern Computer From First Principles
www.nand2tetris.org

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 1

Sequential VS combinational logic

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 2

Lecture plan
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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 3

The Clock

HW

simulator
demo

tock

tick

clock
signal

tick

tick

cycle

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 4

Flip-flop

HW
simulator
demo
in

DFF

out

out(t) = in(t-1)

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in

sequential
chip

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out

=

in

sequential
chip

out

(notation)

clock
signal
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 5

1-bit register (we call it “Bit”)
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load

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in

1

Bit

out

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if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)

in

DFF

out

in

DFF

out

out(t) = in(t-1)
Basic building block

out(t) = out(t-1) ?
out(t) = in(t-1) ?
Won’t work

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 6

Bit register (cont.)

HW
simulator
demo

Interface

Implementation
load

load
Bit

out

in
MUX

in

DFF

out

if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 7

Multi-bit register

HW
simulator
demo

load

load
in

out

Bit

in

...

Bit

w

out

if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)

if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)

1-bit register

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w

Bit Bit

w-bit register

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 8

Aside: Hardware Simulation
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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 9

Random Access Memory (RAM)

HW
simulator
demo

load

register 0
register 1
register 2

in

..
.

(word)

register n-1

out
(word)

RAM n
address
Direct Access Logic

(0 to n-1)

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 10

RAM interface

load

in
out

16 bits

RAMn
address

16 bits

log 2 n
bits

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 11

RAM anatomy
RAM 64

RAM8

..
.

RAM 8

8

register

..
.

Register
Bit Bit

...

8

RAM8

register
Bit

register

...

Recursive ascent

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 12

Counter
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inc

in

load reset

out

PC (counter)
w bits

w bits

If reset(t-1) then out(t)=0
else if load(t-1) then out(t)=in(t-1)
else if inc(t-1) then out(t)=out(t-1)+1
else out(t)=out(t-1)

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 13

Recap: Sequential VS combinational logic
Combinational chip

in

comb.
logic

out

out = some function of (in)

Sequential chip

in

(optional)

time delay

(optional)

comb.
logic

DFF
gate(s)

comb.
logic

out

out(t) = some function of (in(t-1), out(t-1))

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 14

Time matters
tock

tick

clock
signal

tick

cycle

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tick

cycle

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Reg1

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out

b

Reg2

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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 15

Perspective
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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 16

End notes: some poetry about the limits of logic ...
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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic

slide 17