RANCANG BANGUN OKSIMETER DIGITAL BERBASIS MIKROKONTROLER ATMEGA16 Repository - UNAIR REPOSITORY

   LAMPIRAN 1 : GAMBAR ALAT

Gambar 1. Spo2 Mindrey PM50

  

Gambar 2. Oksimeter

Gambar 3. Oksimeter

  LAMPIRAN 2 : LISTING PROGRAM CodeWizardAVR V1.25.5 Professional © Copyright 1998-2007 Pavel Haiduc, HP InfoTech s.r.l.

  Date : 05/06/2012 Author : Ook Company : UNAIR Chip type : ATmega16 Program type : Application Clock frequency : 4,000000 MHz Memory model : Small External SRAM size : 0 Data Stack size : 256

  • / #include <mega16.h> // Alphanumeric LCD Module functions #asm .equ __lcd_port=0x18 ;PORTB #endasm

  #include <lcd.h> #include <stdio.h> #include <delay.h> #define led PORTC.0 #define ir PORTC.1

  #define sample_IR PORTC.3 bit t_count; unsigned char lcd_buffer[33],lcd_buffer2[33],lcd_buffer3[33]; unsigned long temp,tempa,spo,v,vy,vin,vx,r,r1; char pul1,sat1,kom1,pul,sat,kom,; interrupt [TIM1_OVF] void timer1_ovf_isr(void) { // Reinitialize Timer 1 value TCNT1H=0xF5; TCNT1L=0x00; if (t_count==1) { led=1; sample_led=1; ir=0; sample_IR=0; t_count=0; } else { led=0; sample_led=0; sample_IR=1; ir=1; t_count=1; } }

  #define ADC_VREF_TYPE 0x00 // Read the AD conversion result unsigned int read_adc(unsigned char adc_input) { ADMUX=adc_input | (ADC_VREF_TYPE & 0xff); delay_us(10); ADCSRA|=0x40; while ((ADCSRA & 0x10)==0); ADCSRA|=0x10; return ADCW; } void tampilan_awal() { lcd_gotoxy(0,0); lcd_putsf(" LapanTech "); delay_ms(1500); lcd_gotoxy(6,1); lcd_putsf("Present "); delay_ms(1500); lcd_clear(); lcd_gotoxy(0,1); lcd_putsf("PULSE OXYMETRI"); delay_ms(1500); lcd_clear(); }

  { //===========ADC Sample LED=========// temp=read_adc(0); vx=temp*50; //vy=vx/1024; vy=temp/2; pul=(vy/100)%10; sat=(vy/10)%10; kom=vy%10; lcd_gotoxy(0,0); lcd_putsf("LED:"); //sprintf(lcd_buffer,"%d%d,%d",pul,sat,kom); sprintf(lcd_buffer,"%d",vy); lcd_gotoxy(0,1); lcd_puts(lcd_buffer); delay_ms(300); //===========ADC Sample IR==========// tempa=read_adc(1); vin=tempa*50; //v=vin/1024; v=tempa/20; pul1=(v/100)%10; sat1=(v/10)%10; kom1=v%10; lcd_putsf("IR:"); //sprintf(lcd_buffer2,"%d%d,%d",pul1,sat1,kom1); sprintf(lcd_buffer2,"%d",v); lcd_gotoxy(5,1); lcd_puts(lcd_buffer2); delay_ms(300); //==========rumus===== r=vy/v; r1=r*20; spo=1100-r1; //===========buzzer======= if (spo<850) {PORTD.0=1; } else {PORTD.0=0; }; } // Declare your global variables here void main(void) { // Port A initialization PORTA=0x00; DDRA=0x00; // Port B initialization PORTB=0x00; DDRB=0x00;

  PORTC=0x00; DDRC=0xff; // Port D initialization PORTD=0x00; DDRD=0xff; // Timer/Counter 0 initialization // OC0 output: Disconnected TCCR0=0x00; TCNT0=0x00; OCR0=0x00; TCCR1A=0x00; TCCR1B=0x05; TCNT1H=0xD5; TCNT1L=0xD0;

  ICR1H=0x00;

  ICR1L=0x00; OCR1AH=0x00; OCR1AL=0x00; OCR1BH=0x00; OCR1BL=0x00; ASSR=0x00; TCCR2=0x00; TCNT2=0x00; OCR2=0x00;

  MCUCSR=0x00; // Timer(s)/Counter(s) Interrupt(s) initialization TIMSK=0x04; ACSR=0x80; SFIOR=0x00; ADMUX=ADC_VREF_TYPE & 0xff; ADCSRA=0x82; // LCD module initialization lcd_init(16); // Global enable interrupts #asm("sei") t_count=0; //tampilan_awal(); while (1) { // Place your code here baca_adc(); //spo=vy/v; pul=(spo/100)%10; sat=(spo/10)%10; kom=spo%10; lcd_gotoxy(10,0); sprintf(lcd_buffer3,"%d%d,%d",pul,sat,kom); //sprintf(lcd_buffer3,"%d",r); lcd_gotoxy(10,1); lcd_puts(lcd_buffer3); delay_ms(1000); }; }

  LF353 LF353 Wide Bandwidth Dual JFET Input Operational Amplifier

  Literature Number: SNOSBH3D Skripsi Rancang Bangun Oksimeter Digital Berbasis

  Mikrokontroler ATMega16 Guruh Hariyanto

  December 2003 W ide LF353 Bandwidth Wide Bandwidth Dual JFET Input Operational Amplifier General Description Features

  10 mV These devices are low cost, high speed, dual JFET input n Internally trimmed offset voltage: operational amplifiers with an internally trimmed input offset

  50pA n Low input bias current: ™

  √ voltage (BI-FET II technology). They require low supply 25 nV/ Hz n Low input noise voltage: current yet maintain a large gain bandwidth product and fast

  √ 0.01 pA/ Hz n Low input noise current: slew rate. In addition, well matched high voltage JFET input

  Dual

  4 MHz n Wide gain bandwidth: devices provide very low input bias and offset currents. The

  13 V/µs n High slew rate: LF353 is pin compatible with the standard LM1558 allowing

  3.6 mA n Low supply current: designers to immediately upgrade the overall performance of 12

  10 n High input impedance: existing LM1558 and LM358 designs.

  JFET ≤0.02% n Low total harmonic distortion :

  These amplifiers may be used in applications such as high

  50 Hz n Low 1/f noise corner: speed integrators, fast D/A converters, sample and hold

  2 µs circuits and many other circuits requiring low input offset n Fast settling time to 0.01%: Input voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift.

  Operational Typical Connection Connection Diagram Dual-In-Line Package Amplifier 00564914 Top View 00564917 Order Number LF353M, LF353MX or LF353N See NS Package Number M08A or N08E Simplified Schematic 1/2 Dual BI-FET II ™ is a trademark of National Semiconductor Corporation.

  00564916

  Absolute Maximum Ratings (Note 1)

  Amplifier to Amplifier Coupling T A =25˚C, f=1 Hz−20 kHz −120 dB

(Input Referred)

SR Slew Rate

  V CM Input Common-Mode Voltage

  V S

= ±

  15V ± 11 +15

  V Range −12

  V CMRR Common-Mode Rejection Ratio R S ≤ 10kΩ 70 100 dB PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB

  I S Supply Current 3.6 6.5 mA

  AC Electrical Characteristics (Note 5) Symbol Parameter Conditions LF353 Units Min Typ Max

  V S = ±

  15V, R L =10kΩ ± 12 ±

  15V, T A =25˚C

  8.0

  13 V/µs GBW Gain Bandwidth Product

  V S = ±

  15V, T A =25˚C

  2.7

  4 MHz e n Equivalent Input Noise Voltage T A

=25˚C, R

S =100Ω,

  16 f=1000 Hz i n Equivalent Input Noise Current T j =25˚C, f=1000 Hz

  13.5 V

  V S

= ±

  If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

  V OS Input Offset Voltage R S =10kΩ, T A =25˚C

  Supply Voltage ±

  18V Power Dissipation (Note 2) Operating Temperature Range 0˚C to +70˚C T j (MAX) 150˚C Differential Input Voltage ±

  30V Input Voltage Range (Note 3) ±

  15V Output Short Circuit Duration Continuous Storage Temperature Range −65˚C to +150˚C Lead Temp. (Soldering, 10 sec.) 260˚C Soldering Information Dual-In-Line Package

  Soldering (10 sec.) 260˚C Small Outline Package Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C

  See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. ESD Tolerance (Note 8) 1000V θ JA M Package TBD Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Elec- trical Characteristics state DC and AC electrical specifications under particu- lar test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guar- anteed for parameters where no limit is given, however, the typical value is a good indication of device performance.

  DC Electrical Characteristics (Note 5)

  Symbol Parameter Conditions LF353 Units MIn Typ Max

  5 10 mV Over Temperature 13 mV ∆V OS /∆T Average TC of Input Offset Voltage R S =10 kΩ 10 µV/˚C

  V O Output Voltage Swing

  I OS Input Offset Current T j =25˚C, (Notes 5, 6) 25 100 pA T

j ≤70˚C

4 nA

  I B Input Bias Current T j =25˚C, (Notes 5, 6) 50 200 pA T

j ≤70˚C

8 nA R IN Input Resistance T j

=25˚C

  10 12 Ω A VOL Large Signal Voltage Gain

  V S

= ±

  15V, T A =25˚C 25 100 V/mV

  V O

= ±

  10V, R L =2 kΩ Over Temperature

  15 V/mV

  0.01 LF353

  (Continued) AC Electrical Characteristics

  (Note 5) Symbol Parameter Conditions LF353 Units Min Typ Max

  THD Total Harmonic Distortion A =+10, RL=10k, < V 0.02 % V =20Vp−p, O Note 2: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115˚C/W typ junction to ambient for the N package, BW=20 Hz-20 kHz Note 5: These specifications apply for V ± ≤+70˚C. V Note 4: The power dissipation limit, however, cannot be exceeded. Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. and 158˚C/W typ junction to ambient for the H package. Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, T S A OS B OS CM = 15V and 0˚C≤T , I and I are measured at V =0. j . Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P D . T j =T A +θ jA P D where θ jA is the thermal resistance from junction to ambient. Use of a heat sink is Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. V recommended if input bias current is to be kept to a minimum. S = ± Note 8: Human body model, 1.5 kΩ in series with 100 pF.

  6V to ± 15V.

  Typical Performance Characteristics Input Bias Current Input Bias Current 00564918 00564919

  Supply Current Positive Common-Mode Input Voltage Limit 00564920 00564921

  Typical Performance Characteristics (Continued)

  

Negative Common-Mode Input Voltage Limit Positive Current Limit

00564922 00564923

  Negative Current Limit Voltage Swing 00564924 00564925

  Output Voltage Swing Gain Bandwidth 00564926 00564927

  LF353

  Typical Performance Characteristics

(Continued)

  Bode Plot Slew Rate

  00564928 00564929 Distortion vs. Frequency Undistorted Output Voltage Swing

  00564930 00564931 Open Loop Frequency Response Common-Mode Rejection Ratio

  00564932 00564933

  (Continued) Typical Performance Characteristics LF353 Power Supply Rejection Ratio Equivalent Input Noise Voltage 00564934

  00564935 Open Loop Voltage Gain (V/V) Output Impedance

  00564936 00564937 Inverter Settling Time

  00564938

  Pulse Response Small Signaling Inverting 00564904

  Large Signal Inverting 00564906

  Small Signal Non-Inverting 00564905

  Large Signal Non-Inverting 00564907

  Current Limit (R

L

= 100) 00564908

  Application Hints These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current.

  The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit.

  Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur

  Application Hints (Continued) since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode.

  Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within

  3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±

  6V power sup- plies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kΩ load resistance to ±

  10V over the full temperature range of 0˚C to +70˚C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both posi- tive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feed- back pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feed- back pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.

  Detailed Schematic 00564909

  LF353

  Typical Applications Three-Band Active Tone Control 00564939 Note 4: Mid boost, bass and treble flat. Note 3: Bass and treble cut, mid flat. Note 2: Bass and treble boost, mid flat. Note 1: All controls flat.

  00564940 Note 5: Mid cut, bass and treble flat.

  • All potentiometers are linear taper
  • Use the LF347 Quad for stereo applications

  (Continued) Typical Applications LF353 Improved CMRR Instrumentation Amplifier

  00564941 Fourth Order Low Pass Butterworth Filter

  00564942

  (Continued) Typical Applications Fourth Order High Pass Butterworth Filter

  00564943

  (Continued) Typical Applications LF353

  Ohms to Volts Converter 00564944 inches (millimeters) unless otherwise noted Physical Dimensions Order Number LF353M or LF353MX NS Package Number M08A

  Molded Dual-In-Line Package Order Number LF353N NS Package N08E

  Notes

LIFE SUPPORT POLICY

  

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

  1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

  2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

  

National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products

Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification

(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208

  English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LF353 W ide Bandwidth Dual JFET Input Operational Amplifier

IMPORTANT NOTICE

  

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Copyright

  © 2011, Texas Instruments Incorporated

CMOS QUAD BILATERAL SWITCH

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

15-V Digital or ±7.5-V Peak-to-Peak Matched Control-Input to Signal-Output

  D D

  Switching Capacitance: Reduces Output Signal Transients 125-Typical On-State Resistance for 15-V

  D Operation

  Frequency Response, Switch On = 40 MHz D

  Typical Switch On-State Resistance Matched to D

  Within 5 Over 15-V Signal-Input Range 100% Tested for Quiescent Current at 20 V D

  

On-State Resistance Flat Over Full 5-V, 10-V, and 15-V Parametric Ratings

D

  D Peak-to-Peak Signal Range Meets All Requirements of JEDEC Tentative

  D High On/Off Output-Voltage Ratio: 80 dB Standard No. 13-B, Standard Specifications

  D Typical at f = 10 kHz, R = 1 kfor Description of “B” Series CMOS is L

  Devices High Degree of Linearity: <0.5% Distortion

  D Typical at f = 1 kHz, V = 5 V p-p, Applications: is is D

  

V – V 10 V, R = 10 k– Analog Signal Switching/Multiplexing:

DD SS L Signal Gating, Modulator, Squelch Extremely Low Off-State Switch Leakage,

  D Control, Demodulator, Chopper, Resulting in Very Low Offset Current and Commutating Switch High Effective Off-State Resistance: 10 pA – Digital Signal Switching/Multiplexing Typical at V – V = 10 V, T = 25°C DD SS A – Transmission-Gate Logic Implementation Extremely High Control Input Impedance

  D

  • – Analog-to-Digital and Digital-to-Analog (Control Circuit Isolated From Signal Conversion

12 Circuit): 10 Ω Typical – Digital Control of Frequency, Impedance, Low Crosstalk Between Switches: –50 dB

  D Phase, and Analog-Signal Gain

  Typical at f = 8 MHz, R = 1 kis L

  

E, F, M, NS, OR PW PACKAGE

(TOP VIEW)

SIG A IN/OUT

  1

  14 V DD

  2

  13 SIG A OUT/IN CONTROL A SIG B OUT/IN

  3

  12 CONTROL D SIG B IN/OUT

  4

  11 SIG D IN/OUT CONTROL B

  5

  10 SIG D OUT/IN CONTROL C

  6

  9 SIG C OUT/IN

  V

  7

  8 SIG C IN/OUT SS description/ordering information The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.

  It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to V (when the switch

  SS is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range.

  The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended.

  Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Products conform to specifications per the terms of Texas Instruments PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated

CMOS QUAD BILATERAL SWITCH

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003 description/ordering information (continued)

  

ORDERING INFORMATION

TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING

  • –55 C to 125 C CDIP – F Tube of 25 CD4066BF3A CD4066BF3A
  • –55 C to 125 C PDIP – E Tube of 25 CD4066BE CD4066BE
  • –55 C to 125 C SOIC – M Tube of 50 CD4066BM CD4066BM
  • –55°C to 125°C SOIC – M Reel of 2500 CD4066BM96 CD4066BM
  • –55°C to 125°C Reel of 250 CD4066BMT SOP – NS Reel of 2000 CD4066BNSR CD4066B TSSOP – PW Tube of 90 CD4066BPW CM066B TSSOP – PW

  Reel of 2000 CD4066BPWR CM066B

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

  † All control inputs are protected by the CMOS protection network. NOTES: A. All p substrates are connected to VDD.

  B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS

  C. Signal-level range: VSS ≤ Vis ≤ VDD Control

  VC†

  VDD

  

VSS

  VSS n n p Out Vos Control Switch In

  92CS-29113

n

p Vis

  

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

CMOS QUAD BILATERAL SWITCH

  • –0.5 V to V

  Package thermal impedance, θ JA (see Note 1): E package 80°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  18 V TA Operating free-air temperature

  3

  VDD Supply voltage

  

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions

  Storage temperature range, T stg –65°C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  M package 86°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 76°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PW package 113°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature (during soldering):

At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265°C . . . . . . . . . . . . . . . . . . . . . . .

  IN (any one input) ±10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  DC input current, I

  DD + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  (all inputs)

  Input voltage range, V is

  (voltages referenced to V SS terminal) –0.5 V to 20 V . . . . . . . . . . . . . . . . . . . .

  DC supply-voltage range, V DD

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)

MIN MAX UNIT

  • –55 125 °C

CMOS QUAD BILATERAL SWITCH

VIN (V)

  VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ

  VC(A) = VDD = 5 V,

  VC = 0 V, Vis = 0 V, Vos = 18 V 18 ±0.1 ±0.1 ±1 ±1 ±10–5 ±0.1 µA

  VC = 0 V, Vis = 18 V, Vos = 0 V; and

  1 MHz Iis Input/output leakage current (switch off) (max)

  VC = VSS = –5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ

  40 MHz

  VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 10 kΩ, fis = 1-kHz sine wave 0.4 %

  8 MHz t Propagation delay RL = 200 kΩ, VC = VDD,

  5 THD Total harmonic distortion

  15

  10 10 Ω on any two switches L C DD

  15 ∆ron On-state resistance difference between any two switches RL = 10 kΩ, VC = VDD

  5

  R = 10 k V = V

  VC(B) = VSS = –5 V, Vis(A) = 5 Vp-p, 50-Ω source, RL = 1 kΩ

  VSS = GND, CL = 50 pF,

  2 10 310 330 500 550 180 400 Ω to , Vis = VSS to VDD

  7

  VDD = 5 V, VC = VSS = –5 V 0.5 pF

  Feedthrough

  VDD = 5 V, VC = VSS = –5 V 8 pF Cios

  Output capacitance

  VDD = 5 V, VC = VSS = –5 V 8 pF Cos

  15 Cis Input capacitance

  15

  5

  10 20 ns signal output) (square wave centered on 5 V), tr, tf = 20 ns

  10

  VSS = GND, CL = 50 pF, Vis = 10 V (square wave centered on 5 V),

  (signal input to signal output)

  40 ns tpd Propagation delay

  20

  2 15 200 210 300 320 125 240 r On-state resistance

  Ǔ

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003 electrical characteristics PARAMETER TEST CONDITIONS LIMITS AT INDICATED TEMPERATURES UNIT PARAMETER TEST CONDITIONS

  7.5

  0.5

  0.5

  10

  IDD Quiescent device 0, 10

  0.25 A

  0.01

  7.5

  15

  0.25

  0.25

  5

  I Quiescent device 0, 5

  VDD (V) –55°C –40°C 85°C 125°C TYP MAX

  VDD –55°C –40°C 85°C 125°C 25°C UNIT

  VIN

  15

  0.01

  V DD

  20

  ǒ

  On-state resistance (max) RL = 10 k returned to ,

  VC = VDD, RL = 10 kΩ returned 5 800 850 1200 1300 470 1050 ron

  5 Signal Inputs (Vis) and Outputs (Vos) r On-state resistance

  0.02

  5 5 150 150

  1 µA 0, 20

  0.5 µA

  0.01

  30

  30

  1

  1

  15

  IDD Quiescent device current 0, 15

  • V SS
    • –3-dB cutoff frequency (switch on)
    • –50-dB feedthrough frequency (switch off)
    • –50-dB crosstalk frequency

CMOS QUAD BILATERAL SWITCH

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003 electrical characteristics (continued) CHARACTERISTIC TEST CONDITIONS LIMITS AT INDICATED TEMPERATURES UNIT CHARACTERISTIC TEST CONDITIONS

  

VDD

  

VDD

(V)

  • –55°C –40°C 85°C 125°C 25°C UNIT
  • –55°C –40°C 85°C 125°C TYP MAX Control (VC)

  5

  0.64

  5 5 –0.64 –0.61 –0.51 –0.42 –0.36

  0.4

  0.36

  0.42

  0.51

  

0.61

  5

  10

  VDD (V) Vis (V) Iis (mA) OUTPUT, Vos (V) (V) is (V) –55°C –40°C 25°C 85°C 125°C MIN MAX

  VDD SWITCH INPUT SWITCH OUTPUT, Vos

  9.5 CI Input capacitance 5 7.5 pF switching characteristics

  15

  9 MHz repetition rate centered on 5 V), tr, tf = 20 ns, Vos = 1/2 Vos at 1 kHz

  10

  4.6

  1.6

  6 MHz Maximum control input repetition rate RL = 1 kΩ to GND, CL = 50 pF,

  

4

  13.5

  15 15 –4.2 –4 –3.4 –2.8 –2.4

  1.5

  2.4

  2.8

  3.4

  4.2

  

1.5

  15

  9.5

  10 10 –1.6 –1.5 –1.3 –1.1 –0.9

  0.5

  0.9

  1.1

  1.3

  VC = 10 V (square wave centered on 5 V), tr, tf = 20 ns,

  5

  1

  2

  2

  15

  ILC low voltage (max) is SS OS DD Vis = VDD, VOS = VSS

  2 V

  2

  2

  2

  2

  10

  Vis = VSS, VOS = VDD, and V = V , V = V

  VILC Control input, low voltage (max) |Iis| < 10 µA,

  1 V

  1

  1

  1

  2

  2

  30 Maximum control input Vis = VDD, VSS = GND, RL = 1 kΩ to GND, CL = 50 pF,

  35

  15

  V Control input, |Iis| < 10 µA,

  20 40 ns propagation delay CL = 50 pF, RL = 1 kΩ

  10

  VIN = VDD, tr, tf = 20 ns, CL = 50 pF, RL = 1 kΩ

  70 ns Turn-on and turn-off propagation delay

  5

  2 V Control input, See Figure 6 5 3.5 (MIN)

  VIN = VDD, tr, tf = 20 ns,

  VC = 10 V (square wave), tr, tf = 20 ns, RL = 10 kΩ 10 50 mV Turn-on and turn-off

  VCC ≤ VDD – VSS 18 ±0.1 ±0.1 ±1 ±1 ±10–5 ±0.1 µA Crosstalk (control input to signal output)

  IIN Input current (max) Vis ≤ VDD, VDD – VSS = 18 V,

  V IHC high voltage 15 11 (MIN)

  10 7 (MIN)

  V VIHC Control input, high voltage See Figure 6

  15

CMOS QUAD BILATERAL SWITCH

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

INPUT SIGNAL VOLTAGE (ALL TYPES) 300 250 200 150 100

INPUT SIGNAL VOLTAGE (ALL TYPES)

4 TYPICAL ON-STATE RESISTANCE vs

  7.5

  92CS-27330RI – Channel On-State Resistance – onr

  10 V –15 V

  10 Supply Voltage (VDD – VSS) = 5 V TA = 125°C

  7.5

  5

  2.5

  INPUT SIGNAL VOLTAGE (ALL TYPES) 600 500 400 300 200 100 –10 –7.5 –5 –2.5

  Vis – Input Signal Voltage – V Figure 5 TYPICAL ON-STATE RESISTANCE vs

  92CS-27329RI – Channel On-State Resistance – onr

  5

  Vis – Input Signal Voltage – V 600 500 400 300 200 100 –4 –3 –2 –1

  2.5

  50 –10 –7.5 –5 –2.5

  INPUT SIGNAL VOLTAGE (ALL TYPES) Figure 4 300 250 200 150 100

  92CS-27327RI – Channel On-State Resistance – onr Vis – Input Signal Voltage – V TYPICAL ON-STATE RESISTANCE vs

  10 Supply Voltage (VDD – VSS) = 10 V TA = 125°C Vis – Input Signal Voltage – V +25°C –55°C

  7.5

  5

  2.5

  50 –10 –7.5 –5 –2.5

  Figure 3 TYPICAL ON-STATE RESISTANCE vs

  92CS-27326RI Figure 2 TA = 125°C +25°C –55°C Supply Voltage (VDD – VSS) = 5 V – Channel On-State Resistance – onr

  3

  2

  1

10 Supply Voltage (VDD – VSS) = 15 V TA = 125°C +25°C –55°C

CMOS QUAD BILATERAL SWITCH

  SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

CD4066B

  6

  2

  6

  4

  2

  2

  4

  6

  2

  4

  5 V

  92C-30920

  6

  10 V

  VSS

  VDD

  5

  6

  13

  12

  7 CD4066B

P –

  14 Supply Voltage (VDD) = 15 V

  4

  2

  

1 of 4 Switches

Iis Vis

  1

  Vos

  92CS-30966 |Vis – Vos| |Iis| ron = Figure 6. Determination of r on as a Test Condition for Control-Input High-Voltage (V

  IHC ) Specification X-Y Plotter 1-kRange

  TG On Keithley 160 Digital Multimeter H. P. Moseley 7030A

  X VSS

  VDD 10 k

  92CS-22716 Y

Figure 7. Channel On-State Resistance Measurement Circuit

Figure 8 TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS

  3

  2

  1 –1 –2 –3 –3 –2 –1

  2

  4

  3

  92CS-30919 Output V oltage – V V –

  VDD

  VC = VDD Vis Vos RL

  VSS All unused terminals are connected to VSS CD4066B 1 of 4 Switches

  O Figure 9 10 102 103

  10 101 102 103 104 f – Switching Frequency – kHz POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY TA = 25°C

Power Dissipation Per Package – W

D

µ

  6

  4

  2

  6