TEKNIK DIGITAL (A) (TI 2104)

  

TEKNI K DI GI TAL (A) TEKNI K DI GI TAL (A)

(TI 2104)

(TI 2104)

  Mat er i Mat er i Kuliah Kuliah ke ke - -

  10

  10 Count ers Count ers

Overview

Overview

n n Ripple Count er Ripple Count er n n

  Synchr onous Binar y Count er s Synchr onous Binar y Count er s n n Design wit h D Flip Design wit h D Flip - - Flops Flops n n Design wit h J Design wit h J - - K Flip K Flip - - Flops Flops n n Ser ial Vs. Par allel Count er s Ser ial Vs. Par allel Count er s n n

  Up Up - - down Binar y Count er down Binar y Count er n n

  Binar y Count er wit h Par allel Load Binar y Count er wit h Par allel Load n n BCD Count er , Ar bit r ar y sequence Count er s BCD Count er , Ar bit r ar y sequence Count er s n n

  Count er s in VHDL Count er s in VHDL

  

Count ers

Count ers

count er count er n n

  

A A is a r egist er t hat goes t hr ough a is a r egist er t hat goes t hr ough a

pr edet er mined sequence of st at es upon t he pr edet er mined sequence of st at es upon t he

applicat ion of clock pulses. applicat ion of clock pulses. n n

  Count er s ar e cat egor ized as: Count er s ar e cat egor ized as: n n Ripple Count er s: Ripple Count er s:

  The FF out put t r ansit ion ser ves as a sour ce f or The FF out put t r ansit ion ser ves as a sour ce f or t r igger ing ot her FFs. No common clock. t r igger ing ot her FFs. No common clock. n n Synchr onous Count er : Synchr onous Count er :

  All FFs r eceive t he common clock pulse, and t he All FFs r eceive t he common clock pulse, and t he change of st at e is det er mined f r om t he pr esent change of st at e is det er mined f r om t he pr esent st at e. st at e.

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  3 Example: A 4 - bit Upward

  Example: A 4 - bit Upward

Count ing Ripple Count er

  

Count ing Ripple Count er

Less Signif icant Bit out put is Clock f or Next Signif icant Bit ! (Clock is act ive low)

  Recall...

  4- Feb - 09

  5 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  

Example (cont . )

Example (cont . )

n n The out put of each FF is connect ed t o t he The out put of each FF is connect ed t o t he

C input of t he next FF in sequence. C input of t he next FF in sequence. n n

  

The FF holding t he least signif icant bit The FF holding t he least signif icant bit

r eceives t he incoming clock pulses. r eceives t he incoming clock pulses. n n The J and K input s of all FFs ar e connect ed The J and K input s of all FFs ar e connect ed t o a per manent logic 1. t o a per manent logic 1.

n n The bubble next t o t he C label indicat es The bubble next t o t he C label indicat es

t hat t he FFs r espond t o t he negat ive t hat t he FFs r espond t o t he negat ive - - going going t r ansit ion of t he input . t r ansit ion of t he input .

  

Example (cont . )

Example (cont . )

  Oper at ion: Oper at ion: n n The least signif icant bit (Q The least signif icant bit (Q ) is ) is complement ed wit h each complement ed wit h each negat ive negat ive - - edge clock pulse input . edge clock pulse input . n n Ever y t ime t hat Q Ever y t ime t hat Q goes f r om 1 goes f r om 1 t o 0, Q t o 0, Q

  1

  1 is complement ed. is complement ed. n n Ever y t ime t hat Q Ever y t ime t hat Q

  1

  1

goes f r om 1 goes f r om 1

t o 0, Q t o 0, Q

  2

  2 is complement ed. is complement ed. n n Ever y t ime t hat Q Ever y t ime t hat Q

  2

  2

goes f r om 1 goes f r om 1

t o 0, Q t o 0, Q

  3

  3 is complement ed, and so is complement ed, and so on. on.

  A 4 A 4 bit Downward bit Downward - -

Count ing Ripple Count er Count ing Ripple Count er

n n Use dir ect Set (S) signals inst ead of Use dir ect Set (S) signals inst ead of dir ect Reset (R), in or der t o st ar t at 1111. dir ect Reset (R), in or der t o st ar t at 1111. n n Alt er nat ive designs: Alt er nat ive designs: n n

• Change edge Change edge t r igger ing t o posit ive (det ails in t r igger ing t o posit ive (det ails in -

  class) class) n n

  Connect t he complement out put of each FF Connect t he complement out put of each FF

t o t he C out put of t he next FF in t he t o t he C out put of t he next FF in t he

sequence… (homewor k!) sequence… (homewor k!)

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  7 Using D Flip-Flops

  Replace each J K f lip- f lop wit h t he above D f lip- f lop and it s cor r esponding combinat ional logic.

  Synchr onous Binar y Count er s Synchr onous Binar y Count er s

n n The design pr ocedur e f or a binar y count er is The design pr ocedur e f or a binar y count er is

t he same as any ot her synchr onous sequent ial t he same as any ot her synchr onous sequent ial cir cuit . cir cuit .

n n The pr imar y input s of t he cir cuit ar e t he CLK The pr imar y input s of t he cir cuit ar e t he CLK

and any cont r ol signals (EN, Load, et c). and any cont r ol signals (EN, Load, et c). n n The pr imar y out put s ar e t he FF out put s The pr imar y out put s ar e t he FF out put s (pr esent st at e). (pr esent st at e). n n

  Most ef f icient implement at ions usually use T - Most ef f icient implement at ions usually use T -

• FFs or J K FFs or J K FFs. We will examine J K and D f lip FFs. We will examine J K and D f lip f lop designs. f lop designs.

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  9 Synchronous Binary Count ers:

  J -K Flip Flop Design of a 4-bit Binar y Up Count er

  Synchronous Binary Count ers: J -K Flip Flop Design of a Binar y Up Count er (cont .)

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  11 Synchronous Binary Count ers:

  J -K Flip Flop Design of a Binar y Up Count er (cont .)

  4- Feb - 09

  1 K Q 2

  2 Q

  1 Q

  CLK logic 1 Q Q

  2 J K C J K C J K C J K C

  1 Q

  = Q Q

  2 K Q 3

  1 Q

  = Q Q

  1 J Q 3

  = Q Q

  = Q Q

  13 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  Q 2

  = Q J

  Q 1

  = Q K

  Q 1

  = 1 J

  Q 0

  = 1 K

  Q 0

  J

  J -K Flip Flop Design of a Binar y Up Count er (cont .) Synchronous Binary Count ers: J -K Flip Flop Design of a Binar y Up Count er (cont .) Synchronous Binary Count ers:

  3

  Synchronous Binary Count ers: J -K Flip Flop Design of a Binar y Up Count er wit h EN and CO

  EN = enable cont r ol signal, when 0 count er r emains in t he same st at e, when 1 it count s CO = car r y out put signal, used t o ext end t he count er t o mor e st ages J = 1 · EN

  Q 0

  K = 1 · EN

  Q 0

  J = Q · EN

  Q 1

  K = Q · EN

  Q 1

  J = Q Q · EN

  Q 2

  1 K = Q Q · EN Q 2

  1 J = Q Q Q · EN Q 3

  1

  2 K = Q Q Q · EN Q 3

  1

  2 C0 = Q Q Q Q · EN

  1

  2

  3 4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  15 Synchr onous binar y count er s Synchr onous binar y count er s

  using D f lip using D f lip f lops - - f lops D = Q EN

• Q0
• D = Q ( Q · EN)

  ⊗

  ⊗ Q 1

1 J K-FF equat ions

  D = Q ⊗ • ( Q Q · EN ) Q2

  2

  1

• D = Q ⊗ ( Q Q Q · EN )

  Q3

  3

  1

2 C0 = Q Q Q • Q · EN

  1

  2

  3 See Figur e 5- 11… compar e wit h Figur e 5- 11: J K- based design calls f or 4 AND gat es

  

D- based design calls f or 4 AND and 4 XOR gat es

  

Serial Vs Parallel Count ers

Serial Vs Parallel Count ers

n n I f I f serial gat ing serial gat ing (chain of gat es, inf o r ipples (chain of gat es, inf o r ipples t hr ough) is used t hr ough) is used

• ser ial count er ( ser ial count er ( ex. Fig. 5 ex. Fig. 5 11a) 11a)

  à à parallel parallel n n I f ser ial gat ing is r eplaced wit h I f ser ial gat ing is r eplaced wit h

• gat ing gat ing
• (t his is analogous wit h r ipple (t his is analogous wit h r ipple logic l
• r eplaced wit h car r y r eplaced wit h car r y lookeahead lookeahead - logic in our logic in our adder designs) adder designs)

  par allel count er (ex. Fig. 5 - par allel count er (ex. Fig. 5 11b) 11b) - à à n n

  Advant age of par allel over ser ial count er : Advant age of par allel over ser ial count er : f ast er in cer t ain occasions (1111 f ast er in cer t ain occasions (1111 0000) 0000) à à

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  17 Down Binar y Count er - Up

• - Up Down Binar y Count er

  clock Q n-bit Q

  Up-Down

  1 Counter UD

• Q

  n-1 UD = 0: count up UD = 1: count down

  4- Feb - 09

  19 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0

  UD Q2 Q1 Q0 Q2.D Q1.D Q0.D 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0

  UD Q2 Q1 Q0 Q2.D Q1.D Q0.D

Up-Counter Down-Counter

Up-Down Binary Counter (cont.)

  UD Q2 Q1 Q0

  00

  01

  11

  10

  00

  01

  11

10 Fill- in t he Kar naugh maps f or Q2.D, Q1.D, and Q0.D,

  simplif y, and der ive t he logic diagr am using (a) D-FFs and (b) T -FFs Up Up - - Down Binar y Count er (cont . ) Down Binar y Count er (cont . )

  

Binary Count er wit h Parallel Load Binary Count er wit h Parallel Load

(Nex t slide) gives t he logic diagr am and (Nex t slide) gives t he logic diagr am and

n n

• symbol of a 4 symbol of a 4 bit synchr onous binar y bit synchr onous binar y count er wit h par allel load capabilit y. count er wit h par allel load capabilit y. The f unct ion t able f or t his binar y The f unct ion t able f or t his binar y count er is count er is

  Load Load Count Count Oper at ion Oper at ion Not hing Not hing

1 Count Count

  

1

  1

1 x x Load Load

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  21

  

BCD count er

BCD count er

n n The binar y count er The binar y count er wit h par allel load can wit h par allel load can be conver t ed int o a be conver t ed int o a synchr onous BCD synchr onous BCD count er by count er by connect ing an connect ing an ext er nal AND gat e ext er nal AND gat e t o it . t o it .

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  23 BCD count er (cont . )

  BCD count er (cont . ) - - n n The count er st ar t s wit h an all The count er st ar t s wit h an all zer o out put . zer o out put . n n As long as t he out put of t he AND gat e is 0, each As long as t he out put of t he AND gat e is 0, each posit ive clock pulse t r ansit ion incr ement s t he count er posit ive clock pulse t r ansit ion incr ement s t he count er by one. by one.

n n When t he out put r eaches t he count of 1001, bot h Q When t he out put r eaches t he count of 1001, bot h Q

and Q and Q become 1, making t he out put of t he AND gat e become 1, making t he out put of t he AND gat e

  3 equal t o 1. This condit ion makes Load act ive, so on t he equal t o 1. This condit ion makes Load act ive, so on t he next clock t r ansit ion, t he count er does not count , but next clock t r ansit ion, t he count er does not count , but is loaded f r om it s f our input s. is loaded f r om it s f our input s. n n The value loaded t hen is 0000. The value loaded t hen is 0000.

  3

  

Ar bit r ar y Sequence Count er

Ar bit r ar y Sequence Count er

n n Given an ar bit r ar y sequence, design a count er Given an ar bit r ar y sequence, design a count er

t hat will gener at e t his sequence. t hat will gener at e t his sequence. n n Pr ocedur e: Pr ocedur e: n n Der ive st at e t able/ diagr am based on give sequence Der ive st at e t able/ diagr am based on give sequence

• - - n n Simplif y (using K Simplif y (using K maps, et c) maps, et c)

  n n Dr aw logic diagr am Dr aw logic diagr am n n Example: Use D Example: Use D FFs t o dr aw t he logic FFs t o dr aw t he logic - - diagr am f or sequence gener at or (count er ) diagr am f or sequence gener at or (count er ) f or : 0 f or : 0

  7

  7

  6

  6

  1 1 (000 (000 111 111 110 110 à à à à à à à à à à à à à à 001 001 000) 000)

  à à

  4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7)

  25