128 x 40 Mono OLED Column Row Driver with Controller
LD7032
128 x 40 Mono OLED Column / Row
Driver with Controller
1. REVISION HISTORY
Ver CONTENS DATE
1.0 Jun. 2008
- First version an addition : page7. or floating -
2.0 Dec. 2008
- deleted "When IXS=H, CSB must be Low" in page7
- AC Table : VDD = 1.65 ~ 3.5V (page24,26,27)
PART 1 CONTENTS
1. REVISON HISTORY ................................................................................................................................................................2
2. FEATURES ................................................................................................................................................................................4
3. BLOCK DIAGRAM .................................................................................................................................................................5
4. PIN DESCRIPTION ................................................................................................................................................................6
5. FUNCTIONAL DESCRIPTION .........................................................................................................................8 5.1. MPU Interface .....................................................................................................................................................
5.2. Dot Memory Map .........................................…..........................................................................................
5.3. Correspondence Memory and Display ......................................................................................................
5.4. Output Arrange ..........................................................................................................................................
5.5. Data Write / Read Sequence ....................................................................................................................
5.6. Dot Matrix Output Wave Form .................................................................................................................
5.7. Pre-charge ..................................................................................................................................................
5.8. Power Save... ... ..................................................................................................................................
5.9. Reset...................................................................................................................................................
5.10. OSC ....................................................... . .. ..................................................................................................................
5.11. Frame Sync Signal(F_SYNC) . .. .... ... .. ..... .............. .. ...... ......................................................................................
5.12. Interface Mode
6. Referential Set-up Flow ....................................................................................................................................................20 6.1. Power ON-OFF .........................................................................................................................................
7. ELECTRICAL CHARACTERISTICS ..........................................................................................................................20 7.1. MAXIMUM RATINGS ............................................................................................................................
7.2. DC CHARCTERISTICS ..........................................................................................................................
7.3. AC Characteristics .................................................................................................................................... 7.3.1.1(2) Parallel Interface ............................................................................................................................................. 7.3.2.1(2) Serial Interface .............................................................................................................................................
7.3.3. I2C Interface ......... .. ....................................................................................................................................
7.3.4. Driver OUTPUT .... ..... ............................................................................................................................................ ...
7.3.5. Reset .... .......................................................................................................................................................... ...
2. FEATURES Power Supply
VDD : 1.65 ~ 3.5V
VCC_C : 8.0 ~ 16.0V for Column
VCC_R : 8.0 ~ 16.0V for Row
Display Area
Max 128 x 40 Line
Graphics RAM
Dot matrix : 128 x 1 Bit x 40 = 5,120 Bit
Column Driver
Max 128 Outputs Mono Maximum Output Current = 255 uA (1 uA Step) Next Pin to Pin Current Deviation ± 2.0 (Iout = 50uA) Current Deviation at 1Chip Max-Min ± 4.0 (Iout = 50uA)
％
Average Current Deviation against absolute level ± 6.0 (Iout = 50uA)
％
5 Times Peak boot Current Driving
Row Driver
Max 40 Outputs Variable duty ratio (1 to 40) ON resistance typical 25ohm
CPU Interface
8080 or 6800 series parallel interface
Serial Peripheral Interface
I2C Serial Interface
Screen Saver Screen Saver Function. Oscillator
On-chip RC oscillator
Frame Rate
Variable Frame Rate (60,75,90,105,120,135)Hz
Crosstalk
Crosstalk enhancement function
Internal regulator for row driver
Selectable Voltage Function. ( 0.8*VCC_C or 0.7*VCC_C )
3. BLOCK DIAGRAM
PRE
Co D lu riv m
C0 ~ C127
er n
RSTB A0
G R
RDB/E
A M
WRB/RW PS CSB C80
D
F_SYNC
o D Co t M Ro
D7 R0-R39
riv In w n at M
D6
er st tr P o rix ru
Re U In
D5
T lle ct st r
I g im io
D4 n
ru n is in te D te ct g
D3
rf r io n ec ac
D2
o d e /
D1(SDIN,SDA)
er
D0(SCLK,SCL)
VCC_R
ID2
ID1
ID0
IXS EXT_CLK
O S CA
4. PIN DESCRIPTION
I PS H : I2C is selected, L : I2C is not selected
OELD Dot Matrix Power Supply for Column Driver
VCC_C Power Ground pin.
VSS (AVSS/AVSS) Analog and digital voltage supply.
VDD OELD Dot Matrix Power Supply for Row Driver If Internal Regulator for Row Scan is active, this pin is the power output pin of internal row power regulator. A 4.7uF capacitor is recommended to connect between VCC_R and
VSS. If internal row power regulator is disabled, it must be connected to the external high voltage source or VCC_C.
VCC_R Function TYPE Signal
4.2. System Interface Control Pins
H: Parallel L: Serial
4. 1. Power Supply Pins
I IXS
H: 68CPU L: 80CPU
I C80 Function TYPE Signal
- . Interface Mode Table
IXS PS Interface Mode
1 Parallel
X
1 Serial I2C Serial SPI
4.3. MPU Interface Pins Signal TYPE Function
CSB
I Chip Select ( Active Low)
RDB/E
I Read ( Active Low, 80 Interface) Enable (68 Interface)
WRB/RW
I Write ( Active Low, 80 Interface) H:Read L:Write (68 Interface)
RSTB
I Reset (Active Low) A0
I Address ( L: command, H: Parameter) D7~D0 I/O These are 8-bit bi-directional data bus to be connected to t he microprocessor’s data bus.
When I2C interface mode is selected, D1 will be the I2C d ata input (SDA) and D0 will be the I2C bus clock input (S CL), and D2 ~ D7 should be tied VDD or VSS. When serial interface mode is selected, D1 will be the seria l data input (SDIN), D0 will be the serial clock input (SCL K), and D2 ~ D7 should be tied VDD or VSS or floating .
2 ID2~ID0
I These pins configure I C interface address. Using these
2
pins, I C Address can be selected.This pin is the dot output current reference pin. I is O
DOT
derived from Iref. A resister should be connected between
IREF this pin and VSS .
( Current Setting. Typ Resistance = 39 k Ω )
( Current adjustable range ±30％）
PRE O Pre-Charge Voltage F_SYNC O Frame Sync Signal EXT_CLK I Test Pin.
This pin should be tied VDD or VSS in normal operation.
4.4. OLED Driver Pins Signal TYPE Function
R0 to R39 O OELD Dot Matrix Row Output C0 to C127 O OELD Dot Matrix Column Output
5. FUNCTIONAL DESCRIPTION
5.1 MPU Interface 5.1.1. 80 Series Interface
Parameter or Data H H L Read Parameter or Data Parameter or Data H H L Write Parameter or Data Command L H L Write Command
D[7:0] A0 RDB WRB CSB Function Command
1’st Parameter/Data 2’nd Parameter/Data CSB A0 WRB/RDB D[7:0]
※
NOTE :
↑ stands for rising edge of signal.
L stands for low in signal. H stands for high in signal.
5.1.2. 68Series Interface Function CSB RW E A0 D[7:0]
Write Command L L L Command
↓
Write Parameter/Data L L H Parameter or Data
↓
Read Parameter/Data L H H Parameter or Data
↓
1’st Parameter/Data Command
2’nd Parameter/Data A0 CSB RW E
D[7:0]
5.1.3. Serial Interface Function CSB CLOCK A0 DATA
Write Command L D[0] L D[1] Write Parameter/Data L D[0] H D[1]
CSB Command Parameter/Data
A0 SID(D1)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 SCLK(D0)
Data Latch Data Latch
5.1.4. I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1 ). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2 ). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1 ). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P
Start Condition Stop Condition
Figure 1. Definition of Start and Stop Conditions SDA SCL
Data Line Change Stable; of Data
Data Valid Allowed Figure 2. Bit Transfer
Data output by Transmitter NACK
Data output by Receiver ACK
SCL From S
1
2
8
9 Master Figure 3. Acknowledgement on I2C Bus
- I2C Device ID Address Following a START condition, the bus master must output the address of the slave it is accessing. The address is shown in Figure 4 . To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.
slave address
1
1 ID2
ID1
ID0 R/W Fixed programmable
Figure 4. Device ID Address The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.
MSB bit is first transfered.
- I2C Bus Transactions SCL write acknowledge acknowledge form slave form slave
S
1 2 3 4
5
6
7 A
1
2
3
4
5
6
7
8 A
1
2
3
4
5
6
7
8 A P SDA Slave Address Command byte Data to
Parameter register Stop or Repeat Start
Figure 5. Write Single Parameter Command SCL acknowledge acknowledge write form slave form slave
S
1 2 3 4
5
6
7 A
1
2
3
4
5
6
7
8 A
1
2
3
4
5
6
7
8 A
1
2
3
4
5
6
7
8 A P SDA Figure 7. Read From SRAM
A
2
A
8
7
6
5
4
3
1 A
P
1
7
6 5 3 4
2
1 S Slave Address Data from SRAM
(first byte) acknowledge form slave read
(cont.) (repeated)
Start acknowledge form master
SDA (cont.)
1 not acknowledge form master
8
6 5 3 4
7
6
5
4
3
2
1 A
7
2
3
1 S Slave Address Command byte acknowledge form slave write
8
6
4
2 N
A
7
5
Data from SRAM (last byte)
5.2 Dot Memory Map Column
Memory X Address
00h 01h 02h
0Eh
0Fh 00h (00,00) (01,00) (02,00) (0E,00) (0F,00) ss
01h (00,01) (01,01) (02,01) (0E,01) (0F,01) re d d A w Y o ry R o
26h (00,26) (01,26) (02,26) (0E,26) (0F,26) m e
27h (00,27) (01,27) (02,27) (0E,27) (0F,27) M
Memory Size = 16 x 8Bit 40 = 5,120 Bit
ｘ
- “Data Writing Box” command indicate memory writing area.
- “Writing direction” command indicate writing direction (auto address increment or decrement)
C D A B Momory Display
S ca n D ir ec tio n
Left Scroll
Ac ti ve R ow
CDEFGAB
Active Column Ac ti ve R ow
ABCDEFG
A ct iv e R o w
Display Size Active Column
Memory Display
(XS,YS) (XE,YE )
Memory Data Write
Rmax Display Direction
⇔
- The column outputs out of active area always pre- charge level.
- The row outputs out of active area always VCC_R excluding display off.
- Scan is repeated within active area.
- Rows out of active row are VCC_R.
- “DispSize” command don’t use during panel display. Display Size - “DispDirection” command indicate Row scan direction.
- Row R0
- “DispStart” command fix the relation of memory and display coordinates.
Scroll Area - “DispSize” command indicate active outputs.
Memory Reading Start Address
5.3. Correspondence Memory and Display
- In scroll mode, display all memory area regardless display size.
5.4. Output Arrange
R0 R1 R2 R3
20 Display Face
20 R38
R39 128
C0•••••••••••••••••••••••••••••••••••••••••••••••C127 R39•••R1 R0•••R38
Bumps Face Up
INTERFACE
5.5. Data Write / Read Sequence
Dot Data Write Dot Data Read
DataWrite DataRead WRITE Parameter Dummy Read
END READ Parameter END
Serial Interface is impossible to Data Read
5.6. Dot Matrix Output Wave Form Related Command
Pre-Charge Level Column Port Voltage Level
1 Row Period Pre-Charge Period Peak Boot
Period
Data Display
Period Peak DelayPeriod Pre-Charge Period Peak Delay
Period Peak Boot Period Data Display
Period
1 Row Period Row(N) Column Port
Output Waveform
Row(N+1)1 CLK
1 CLK (0,0) (0,1) (1,0) (1,1) Row Overlap
5.7. Pre-charge When Pre-Charge, each column output is connected the pre-charge pin in the IC. Therefore all dot matrix
5. 8. Power Save
Function Display ON/OFF Stand-by Soft Reset
Command DISPON/OFF STBON/OFF SOFTRES Display-OFF Register Clear
・ ・ Dot Matrix
Function Display ON/Off OSCA Start/Stop Display-OFF
・ ・ ・
Stand-by-ON
・
5. 9. Reset When RSTB Input becomes ‘L’, All Register is set Default. When SOFTRES command is inputted, All Register is set Default 5. 10. OSC
Dot Dot Matrix Driver
Memory Dot Matrix OSCA
Controller Clock System
!" # $ % Frame frequency is adjusted by DFRAME command
“ ”
5. 11. Frame Sync Signal ( F_SYNC ) Row(last) Row(first)
5. 12. Interface Mode (Data Write Only)
Dot matrix display data write mode
Display Memory
COUT0 COUT7
MSB LSB
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1 (Default)
WriteDirection = 00h,
1 Address = 8 Pixels
XDispStart = 00h, YDispStart = 00h
Display Memory
COUT0 COUT7
MSB LSB
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1 WriteDirection = 08h ,
1 Address = 8 Pixels
XDispStart = 00h, YDispStart = 00h
Column Memory X Address
00h 01h 02h
0Eh
0Fh 00h (00,00) (01,00) (02,00) (0E,00) (0F,00) ss
01h (00,01) (01,01) (02,01) (0E,01) (0F,01) re d d A w Y o ry R o
26h (00,26) (01,26) (02,26) (0E,26) (0F,26) m e
27h (00,27) (01,27) (02,27) (0E,27) (0F,27) M
VCC_C
VCC_C
VCC_R
V
−−−−
0.3 ～ ～ ～ ～
Supply Voltage
VDD Unit Value Parameter content
VDD
VCC_R OFF OFF ON ON
V IN
Min 0.1ms Min 0.1ms
0V
0V VDD
RSTB ON Min 0.1ms
0V VDD
!
- +3.63
- -0.3
- +18.0
- -0.3
- +18.0
∼ ∼ ∼ ∼
0.3 ～ ～ ～ ～
VDD+0.3 Input Voltage Range
6. Referential Set-up Flow
6.1 Power ON-OFF
7. ELECTRICAL CHARACTERISTICS
7.1 MAXIMUM RATINGS
(Ta = -40 ～85℃)
∼ ∼ ∼ ∼
VCC_C
- +85 Operating Temperature Range T
50 ～ ～ ～ ～
℃ － － － －
STG ℃ － － － －
40 ～ ～ ～ ～
OPR － － － －
0.3 ～ ～ ～ ～
VDD+0.3 Output Voltage Range
V OUT
－ － － －
- +125 Storage temperature Range T
7.2. DC CHARACTERISTICS
(VDD= 2.8V, VCC_C=VCC_R=15V, Ta = 25 ℃ ) Related
Symbol Parameter Conditions MIN TYP MAX UNIT
Pins
VCC_C Operating Voltage for Column
VCC_C
8
16 ‐ ‐
VCC_R Operating Voltage for Row
VCC_R
8
16 ‐ ‐
1.8 VDD Logic Power 1
VDD
1.65
3.5 ‐
2.8 Logical V - High Logic Input Level 0.8*VDD
IH Input
VDD －
V Logical
V Low Logic Input Level 0.2*VDD -
IL － Input
Logical
V High Logic Output Level Iout 0.9*VDD
－ Output Logical
VDD ＝-100uA OH
V Low Logic Output Level Iout ＝100uA 0.1*VDD － OL
Output
IIL
- 1.0 Input Leakage Current －1.0 uA
VDD = 2.8V Oscillator Frequency
0.9
1.0
1.1 FOSC1
㎒
For Dot Matrix
0.82
0.91
1 VDD = 1.8V 0.8*
VCC_R = 0.8*VCC_C
VCC_R Power Regulator 0.75* 0.85*
IRVCC
VCC_R
VCC
V I =5mA Output Voltage
VCC_C
VCC_C
VCC_R _C Output Current Pin to Pin Even
Cptp1 Iout = 50uA C0-127 + 2.0 －2.0 － ％ ness *1)
Output Current Iout = 50uA C0-127 + 4.0 －4.0 － ％
Calp1 Evenness *2) Cchip1 Output Current C0-127
Iout = 50uA + 6.0 －6.0 － ％ Absolute Correctness *3) Cptp3 Peak boot Ioutpeak = 250uA C0-127 + 2.0
－2.0 － ％ Pin to Pin Evenness *1) Calp3
Peak boot Evenness *2) Ioutpeak = 250uA C0-127 + 4.0
－4.0 － ％Cchip3 Peak boot Absolute Correctness Ioutpeak = 250uA C0-127 + 6.0 －6.0 － ％
- 3) ROW ‐Vss
IOL=35 R0-R39
25
- Rrg ON Resistance ROW ‐VCC_R
40 ｍA Ω
IOL=1 ｍA R0-R39 -
1 3 k Ω Rr ON Resistance
6 －
0.4 V
ILOAD=3mA Pre-Charge SW ON Resistance Rp
UNIT MAX TYP MIN Conditions Parameter Symbol
"
Low Logic Output Level (open-drain) at 3mA sink current at SDA, SCL ( I
2 C)
V DD > 2V
0.0 －
V DD < 2V
All Pin Short Ω 900 600
0.0 －
0.2*V
DD
I OL Low-Level output
Current ( I
2 C)
VOL = 0.4V 3 - - mA
VOL = 0.6V
－ C0-127 Each Pin
7 － － C0-127 Column
IVCC_C2 mA 1 -
NOTICE:
VDD Stand-by Current
－
IVCC_R1 uA 5 -
VCC_R
IVCC_R2 uA 5 -
VCC_R *4)
IVDD2 mA 1 -
VDD *4)
IVDD1 Ω
VCC_C *4) Normal Operation
IVCC_C1 mA 2 -
VCC_C
UNIT MAX TYP MIN Related Pins Conditions Parameter Symbol uA 5 -
- 4) Iout =10
A, All Data on, Frame Frequency 120Hz, VCC_C=VCC_R=15V,
μ
VDD=2.8V, Output( DOT ) all Open, Display Size full, Others Default
- (VDD= 2.8V, VCC_C=VCC_R=15V, Ta = 25 ℃ ) (VDD= 2.8V, VCC_C=VCC_R=15V, Ta = 25 ℃ )
7. 3. AC Characteristics 7. 3. 1.1 Parallel Interface1 (Write/Read Timing)
Tcsh Tcsh Tcsh Tclw
VIH
VIL
VIH
VIL
VIH
VIL Tcsh Tas Tah
Tcycw
Tcsh
TchwVIH
Tdsw Tdhw Tcsh Tcsh
RDB (E) Tcsh Tas
VALID Tclr Tcycr
Tchr Tcsh Tcsh Tcsh
D0 to D7 (Write) D0 to D7 (Read)
Tdsr Tdhr Tah
VIL
VIL CSB WRB (RW)
Read Write
Read control high pulse time 80 Tchr
10 CSB Tcsh ns Tcycw 100 WRB
CSB – WRB , RDB time
10 Tdhr Read data hold time ( Data output disable time )
200 Tdsr Read data setup time ( Data Output Access Time )
10 Tdhw Write data hold time
Tdsw 20 D0 – D7 Write data setup time
Tclr 60 RDB Read control low pulse time
VIH
Write control high pulse width 40 Tchw
Tclw 40 WRB Write control low pulse width
Tcycr 500 RDB System cycle time Tah 10 A0 Address hold time Tas 20 A0 Address setup time
MAX MIN Units Specification Condition Symbol Parameter
VALID
VALID
VALID A0
(VSS = 0V, VDD= 2.6V~3.5V, Ta = 25 ℃)
7. 3. 1.2 Parallel Interface2 (Write/Read Timing)
Read Write
30 CSB Tcsh ns Tcycw 300 WRB
CSB – WRB , RDB time
10 Tdhr Read data hold time ( Data output disable time )
200 Tdsr Read data setup time ( Data Output Access Time )
30 Tdhw Write data hold time
Tdsw 60 D0 – D7 Write data setup time
Read control high pulse time 80 Tchr
Tclr 60 RDB Read control low pulse time
Write control high pulse width 120 Tchw 120 WRB
Tclw Write control low pulse width Tcycr 500 RDB System cycle time
Tah 30 A0 Address hold time Tas 60 A0 Address setup time
MAX MIN Units Specification Condition Symbol Parameter
(VSS = 0V,
VDD= 1.65V~3.5V , Ta = 25 ℃)
CSB SCL
20
(VSS = 0V, VDD= 2.6V~3.5V, Ta = 25 ℃)
8 th SCL
A0 NOTE : The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
t ASS t AHS
SDI
t CYS t PWL t PWH t CSH t SCC t CHW t DSS t DHS
V IL
V IH t CSS
- Conditions SCC 15 SCL to Chip select t
Input Signal Slope Output Signal Slope
MIN Parameter Symbol tr tf
20 Serial clock cycle High pulse Width Low pulse width t CYS t PWH t PWL
66
20 Data setup time Data hold time t DSS t DHS
20
50 Chip select setup time Chip select hold time Chip select high pulse width t CSS t CSH t CSW
50
20
CSB SDI SCL Related Pins
TYP
Unit
MAX ns ns ns ns
- ns
- 15
25 A0 A0 setup time A0 hold time t ASS t AHS
7. 3. 2.1 Serial Interface1
SCL, CSB
- tr tf
- 50
60
VDD= 1.65V~3.5V , Ta = 25 ℃)
(VSS = 0V,
MIN Parameter Symbol
- Conditions SCC 40 SCL to Chip select t
- ns
60 Serial clock cycle High pulse Width Low pulse width t CYS t PWH t PWL
60
150
60 Data setup time Data hold time t DSS t DHS
CSB SDI SCL Related Pins
Chip select setup time Chip select hold time Chip select high pulse width t CSS t CSH t CSW
60 100 100
TYP
Unit
MAX ns ns ns ns
60 A0 A0 setup time A0 hold time t ASS t AHS
7. 3. 2.2 Serial Interface2
SCL, CSB
7. 3. 3 I2C Interface
(VSS = 0V,
VDD= 1.65V~3.5V , Ta = 25 ℃)
Standard mode Fast mode Symbol Parameter
Unit MIN MAX MIN MAX f SCL clock frequency 100 400 kHz
scl
bus free time between a STOP and
4.7 - - t BUF 1.3 us
START condition
4.0 0.6 us - - t hold time (repeated) START condition
HD;STA
set-up time form a repeated START t 4.7 0.6 us - -
SU;STA
condition
4.0 0.6 us - - t set-up time for STOP condition
SU;STO
t data set-up time 250 - 100 ns -
SU;DAT
t data hold time - ns -
HD;DTA
t data valid acknowledge time
0.3
3.45
0.1 0.9 us
VD;ACK
t 50 ns - - data valid time 300
VD;DAT
t LOW period of the SCL clock 4.7 - 1.3 us -
LOW
4.0 0.6 us - - t HIGH period of the SCL clock
HIGH
- t fall time of both SDA and SCL signals 300 300 ns
f
- t rise time of both SDA and SCL signals 1000 - 300 ns
r
pulse width of spikes that must be t 50 50 ns
SP
suppressed by the input filter t t t 1/f
SU;STA LOW HIGH SCL SCL
t t r
BUF
t
f SDA
t t t t t t
A
0.8
C =10pF R = 10k
Column
RowT CFD
0.5 T CRD T CRPD T CFPD
I p
=500uA
0.8 I d
=100uA
0.2
C =10pF
0.2 (VSS = 0V, VDD= 2.6V~3.5V, VCC_C=VCC_R=15V, Ta = 25 ℃)
IREF 0uA
Normal Current
IREF x 5 *1) 0uA
Peak Boot Current 1h 0h
Gray Scale
μ
Column
Row
- 1) 5 Times is guaranteed until 500
- 10 - T
- 100 ns - T
- 1200 ns 800 T
- 200 ns T
C0-C127 Column Peak Delay Time
7.3.4. Driver OUTPUT
T RF T RR
0.2
0.8
“RowOverlap” command changes Row falling timing`
CRPD
CRD
R0-R39 Row Falling Time Unit Max. Typ. Min. Symbol Signal Item
C0-C127 (to R)
Column Drive Start Delay Time
CFD
C0-C127 (to R)
Column Falling Time until Row Falling
RR
R0-R39 Row Rising Time ns
RF
- 200 ns T
7.3.5. Reset Reset low pulse width must be long than 1 us.
Reset complete time is small than 1 us.
128 x 40 Mono OLED Column / Row Driver with Controller
PART 2 CONTENTS
1. Display System Command ...................................................................................................................................................31 1.1. Software Reset ........................................................................................................................................
1.2. Dot Matrix Display ON/OFF ..................................................................................................................
1.3. Dot Matrix Display Stand-by ON/OFF ..................................................................................................
1.4. Dot Matrix Frame Rate ..........................................................................................................................
1.5. Graphics Memory Writing Direction .....................................................................................................
1.6. Display Direction ....................................................................................................................................
1.7. Display Size ...........................................................................................................................................
1.8. Display Start .................................................................................................................................................
2. Read/Write command .............................................................................................................................................................37 2.1. Data Reading/Writing Box ......................................................................................................................
2.2. Dot Matrix Display Data Read/Write .....................................................................................................
2.3. Register Read ..............................................................................................................................................................
3. Driver Setting Command .......................................................................................................................................................39 3.1. Peak Pulse Width Set .............................................................................................................................
3.2. Peak Pulse Delay Set ...............................................................................................................................
3.3. Dot Matrix Current Level Set .................................................................................................................
3.4. Pre-Charge Width Set ...........................................................................................................................
3.5. Pre-Charge Mode Select .......................................................................................................................
3.6. Row overlap set .....................................................................................................................................
3.7. Row SCAN ...........................................................................................................................................
3.8. Row Scan Sequence Setting ..................................................................................................................
3.9. Data Reverse .........................................................................................................................................
4. Others ...................................................................................................................................................................................43
5. Optional Command .............................................................................................................................................................44 5.1. IC Test Co mmand ......................................................................................................................
5.2. Set Internal Regulator for Row Scan .....................................................................................................
5.3. Aging Mode Set ..............................................................................................................................................................
5.4. Set XTALK Enable ....... ...... ... .. ... .. ... ......................................................................................................................
5.5. Set VDD Selection ........... ..... ......................................................................................................................................
6. Screen Saver Command .......................................................................................................................................................48 6.1. S_Sleep Timer .............................................................................................................................
6.2. S_Sleep Start .............................................................................................................................
6.3. S_Step Ti mer ...... .......................................................................................................................
6.4. S_Step Unit .............................................................................................................................
6.5. S_Condition .............................................................................................................................
6.6. S_Saver Start/Stop .............................................................................................................................
6.7. Screen Saver Mode............................................................................................................................
6.8. S_MultiScroll............................................................................................................................
INSTRUCTION DESCRIPTION
1. Display System Command
1.1 Software Reset
Command Parameter
INSTRUCTION Parameter Definition Default WR A0 D[7:0] WR A0 D7 D6 D5 D4 D3 D2 D1 D0
- L 01h Software Reset - - - - - - - - W SOF
- Software reset command
- All registers are cleared default. *1) - Dot matrix is OFF.
- OSCA is stopped
- 1) Don’t clear Graphics memory
1.2. Dot Matrix Display ON/OFF
Command Parameter
INSTRUCTION Parameter Definition Default WR A0 D[7:0] WR A0 D7 D6 D5 D4 D3 D2 D1 D0
D=0 Dot Matrix Display OFF
- W L 02h W H D0 00h - - - - DDISPON/OFF
D=1 Dot Matrix Display ON
- When D0=”0” : Turns the dot matrix Display OFF (Default).
Display OFF means All Column Output become Pre-charge level.
All Row Output become VSS. Stop Data transfer from memory to Dot Matrix Driver.
- When D0=”1” : Turns the dot matrix Display ON.
1.3. Dot Matrix Display Stand-by ON/OFF
Command Parameter
INSTRUCTION Parameter Definition Default WR A0 D[7:0] WR A0 D7 D6 D5 D4 D3 D2 D1 D0
D=0 : Stand-by OFF DSTBYON/OFF W L 14h W H D0 01h - - - - - - - D=1 : Stand-by ON
- When D0=“0”
OSCA Start. (Don’t turn the dot matrix display on)
- When D0=”1”
Execute DDISPOFF command OSCA Stop. (Default).
- NOTE 1 : Don’t clear Graphics memory and Register.
- NOTE 2 : After software and hardware Reset, stay “DSTBYON” Mode.
- NOTE 3 : Column Driver latched datas are reset.
- 1) FO = ‘0’ Frame frequency is difference value by [Display Y Size]. For Example : { F[2:0] = 010b, Display Y Size = 32 } => Frame Frequency is 90Hz. : Freq(SCLK) = 1.0MHz
1 240 Hz
84 Hz
40 108 Hz 120 Hz 135 Hz 270 Hz
96 Hz
1
36
32 1 107 Hz
1 120 Hz
4
16 120 Hz
(MHz)
Frame Frequency
1 SCLK Freq.
1
1
1
1
Frequency (Spec.)
60 Hz Frame
90 Hz
1
93 Hz 105 Hz 210 Hz
(Measured)
1
(Spec.)
Example 1) FO = ‘0’
(MHz)
1 SCLK Freq.
1
1
1
3 F[2:0]
5,6,7
1
Frame Frequency
40
1 135 Hz 105 Hz
1
1
16 Display Y Size
32
36
40
16
32
36
1
16 Display Y Size
1.4. Dot Matrix Frame Rate Dot Matrix frame rate control command.
416
{ F[2:0] = 010b, Display Y Size = 16 } => Frame Frequency is 180Hz. : Freq(SCLK) = 1.0MHz { F[2:0] = 010b, Display Y Size = 40 } => Frame Frequency is 72Hz. : Freq(SCLK) = 1.0MHz 1 150 Hz
= 10 External Clock mode ( Test Mode )
OSCA mode selection M[1:0] = 00 Internal RC Oscillation mode
1Ah W H - - FO M1 M0 F2 F1 F0 Frame Frequency 60-120Hz 02h
WR A0 D7 D6 D5 D4 D3 D2 D1 D0 Parameter Definition Default DFRAME W L
INSTRUCTION Command WR A0 D[7:0] Parameter
F[2:0]
520 The Number of SCLK of one Row ( Display Y Size = 32 )
1
2
75 Hz
346
3