Springer Wide Bandwidth High Dynamic Range DA Converters Mar 2006 ISBN 0387304150 pdf
WIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS
THE INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER
SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
SYSTEMS: WITH CASE STUDIES METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND Related Titles:Consulting Editor: Mohammed Ismail. Ohio State University
Vol. 870, ISBN: 1-4020-4252-3 Pastre, Marc, Kayal, MaherHIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY
CIRCUITS DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR
LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS
Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 868, ISBN: 1-4020-4139-X Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 869, ISBN: 0-387-28591-1 ANALOG DESIGN ESSENTIALS DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Vol. 867, ISBN: 0-387-26121-4 U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Sansen, Willy Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: 0-387-25902-3 LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC'S Vol. 859, ISBN: 0-387-25746-2 Vol. 851, ISBN: 0-387-24314-3 Croon, Sansen, Maes Vol. 854, ISBN: 1-4020-3208-0 Claes and SansenSYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR
LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION BUILDING BLOCKS Vol. 842, ISBN: 1-4020-3173-4 Vanassche, Gielen, Sansen Leroux and Steyaert Vol. 843, ISBN: 1-4020-3190-4 CMOS PLL SYNTHESIZERS: ANALYSIS AND DESIGN CANCELLATION WIDEBAND LOW NOISE AMPLIFIERS EXPLOITING THERMAL NOISE Vol. 840, ISBN: 1-4020-3187-4 Vol. 841, ISBN: 1-4020-2848-2 van der Meer, van Staveren, van Roermund Shu, Keliu, Sánchez-Sinencio, Edgar Bruccoleri, Klumperink, Nauta OPERATIONAL AMPLIFIER SPEED AND ACCURACY IMPROVEMENT STATIC AND DYNAMIC PERFORMANCE LIMITATIONS FOR HIGH SPEED SYSTEMATIC DESIGN OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS Vol. 783, ISBN: 0-387-23668-6 Vol. 763, ISBN: 1-4020-7772-6 Ivanov and Filanovsky Vol. 768, ISBN: 1-4020-7945-1 Bajdechi and Huijsing DESIGN AND ANALYSIS OF HIGH EFFICIENCY LINE DRIVERS FOR Xdsl LOW POWER ANALOG CMOS FOR CARDIAC PACEMAKERS D/A CONVERTERS Vol. 759, ISBN: 1-4020-7727-0 Piessens and Steyaert Vol. 761, ISBN: 1-4020-7761-0 van den Bosch, Steyaert and Sansen MIXED-SIGNAL LAYOUT GENERATION CONCEPTS Vol. 751, ISBN: 1-4020-7598-7 Lin, van Roermund, Leenaerts Vol. 758, ISBN: 1-4020-7719-X Silveira and FlandreWIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS
by Konstantinos Doris
Philips Research Laboratories, Eindhoven, The Netherlands Arthur van Roermund
Eindhoven University of Technology, Eindhoven, The Netherlands
and
Domine Leenaerts Philips Research Laboratories, Eindhoven, The Netherlands A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN-10 0-387-30415-0 (HB)
ISBN-13 978-0-387-30415-1 (HB)
ISBN-10 0-387-30416-9 (e-book)
ISBN-13 978-0-387-30416-8 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
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Contents Glossary Abbreviations Preface
1.4.1 Architecture terminology . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Framework description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
19
2 Framework for Analysis and Synthesis of DACs
1.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.4 Current division based architectures . . . . . . . . . . . . . . . . 18
1.4.3 Capacitive voltage and charge division architectures . . . . . . . 16
1.4.2 Resistive voltage division architectures . . . . . . . . . . . . . . 15
1.4 Circuit aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ix
1.3.2 Signal Modulation concepts . . . . . . . . . . . . . . . . . . . . 13
1.3.1 Waveforms and Line coding . . . . . . . . . . . . . . . . . . . . 11
1.3 Signal processing aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
3 1.2 Algorithmic aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 1.1.2 Functional specifications . . . . . . . . . . . . . . . . . . . . . .
1 1.1.1 Definition of the D/A function . . . . . . . . . . . . . . . . . . .
1 1.1 Functional aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Digital to Analog conversion concepts
2.2.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 xiii xv
Contents
6.1.1 System layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2.4 Charge feedthrough and injection . . . . . . . . . . . . . . . . . 54
5.2.5 Relative timing inaccuracies . . . . . . . . . . . . . . . . . . . . 56
5.2.6 Power supply bounce and substrate noise . . . . . . . . . . . . . 59
5.2.7 Clock (timing) jitter . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 High-level modeling of Current Steering DACs
67
6.1 System modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.2 System excitations and responses . . . . . . . . . . . . . . . . . 69
5.2.2 Asymmetrical switching . . . . . . . . . . . . . . . . . . . . . . 51
6.1.3 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.4 Subsystem interaction . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.5 System modulation . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 Error properties and classification . . . . . . . . . . . . . . . . . . . . . 72
6.2.1 Error properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.2 Error classification . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3 Functional error generation mechanisms . . . . . . . . . . . . . . . . . . 79
6.3.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Algorithmic modeling . . . . . . . . . . . . . . . . . . . . . . . 80
5.2.3 Modulation of switching behavior . . . . . . . . . . . . . . . . . 53
5.2.1 Nonlinear settling and output impedance modulation . . . . . . . 48
3 Current Steering DACs
35
25
3.1 Basic circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Partitioning and segmentation . . . . . . . . . . . . . . . . . . . 26
3.1.2 Current switching network and current sources . . . . . . . . . . 29
3.1.3 Clock-data synchronization circuit . . . . . . . . . . . . . . . . . 29
3.1.4 Auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Implementations and technology impact . . . . . . . . . . . . . . . . . . 30
4 Dynamic limitations of Current Steering DACs
4.1 State of the art in dynamic linearity . . . . . . . . . . . . . . . . . . . . . 35
5.2 Time domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Dynamic limitations of current steering DACs . . . . . . . . . . . . . . . 40
4.2.1 Matching and relative amplitude precision . . . . . . . . . . . . . 41
4.2.2 Matching and relative timing precision . . . . . . . . . . . . . . 42
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Current Steering DAC circuit error analysis
45
5.1 Amplitude domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Relative amplitude inaccuracies . . . . . . . . . . . . . . . . . . 45
5.1.2 Output resistance modulation . . . . . . . . . . . . . . . . . . . 47
6.3.3 Functional modeling . . . . . . . . . . . . . . . . . . . . . . . . 82 vi Contents vii
6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7 Functional modeling of timing errors
89
7.1 Non-uniform timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.1.1 The Equivalent Timing error of a transition . . . . . . . . . . . . 89
7.1.2 Non-uniform timing in the process of signal sampling . . . . . . 91
7.1.3 Non-uniform timing in the process of signal creation . . . . . . . 92
7.2 Stochastic non-uniform timing analysis . . . . . . . . . . . . . . . . . . 95
7.2.1 Correlated non-uniform timing . . . . . . . . . . . . . . . . . . . 95
7.2.2 White non-uniform timing . . . . . . . . . . . . . . . . . . . . . 97
7.2.3 RZ and NRZ waveforms . . . . . . . . . . . . . . . . . . . . . . 100
7.3 Deterministic non-uniform timing . . . . . . . . . . . . . . . . . . . . . 103
7.3.1 Non-linear mapping of time domains . . . . . . . . . . . . . . . 103
7.3.2 Non-uniform timing in signal creation . . . . . . . . . . . . . . . 105
7.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 109
8 Functional analysis of local timing errors
8.1 Local timing error analysis . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.1.1 Equivalent timing error calculation . . . . . . . . . . . . . . . . . 109
8.1.2 Signal error calculation . . . . . . . . . . . . . . . . . . . . . . . 113
8.2 High level architectural parameter tradeoffs: segmentation . . . . . . . . 116
8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 119
9 Circuit analysis of local timing errors
9.1 Circuit analysis with linear models . . . . . . . . . . . . . . . . . . . . . 119
9.1.1 Circuit behavioral-level analysis of timing errors in a chain . . . . 120
9.1.2 Transistor level analysis . . . . . . . . . . . . . . . . . . . . . . 126
9.2 Local timing error tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.1 Switch timing errors . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.2 Latch timing errors . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 139
10 Synthesis concepts for CS DACs
10.1 Information management in the CS DAC . . . . . . . . . . . . . . . . . . 139
10.1.1 The basic current steering DAC hardware . . . . . . . . . . . . . 141
10.1.2 Information sources . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1.3 Optional hardware: detection and control operations . . . . . . . 142
10.1.4 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.1.5 Space/Time error mapping and processing . . . . . . . . . . . . . 145
10.2 Synthesis Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3 A-posteriori error correction methods . . . . . . . . . . . . . . . . . . . 148
10.3.1 Calibration in amplitude and time domain . . . . . . . . . . . . . 148
10.3.2 Generalized mapping . . . . . . . . . . . . . . . . . . . . . . . . 151
Contents
10.3.4 Realization issues of the generalized mapping concept . . . . . . 156
10.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11 Design of a 12 bit 500 Msample/s DAC 159
11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.6.2 AC linearity measurements . . . . . . . . . . . . . . . . . . . . . 181
Binary-to-Thermometer decoder . . . . . . . . . . . . . . . . . . 174 . . . . . . . . . . . . . . . . . . 175
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 . . . . . . . . . . . . . . . . . . . . . . 175
203 viii . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
B Literature data
A.1 Power spectrum of y(t) for random timing errors . . . . . . . . . . . . . 199 A.2 Spectrum of y(t) for deterministic timing errors . . . . . . . . . . . . . . 202
A Output spectrum for timing errors 199
185
References
11.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
11.6.1 DC linearity measurements . . . . . . . . . . . . . . . . . . . . . 180
11.2.1 Signaling and circuit logic . . . . . . . . . . . . . . . . . . . . . 160
11.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.1 Design approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.4.4 Clock buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.4.3 Master-slave latches and drivers
11.4.1 11.4.2 Delay equalization . . .
11.4 Decoder, data synchronization and conditioning . . . . . . . . . . . . . . 174
11.3.2 Switch
11.3.1 Current source
11.2.3 Thermometer/binary bits partitioning . . . . . . . . . . . . . . . 162 11.3 Switched-Current cell .
11.2.2 Power supply and biasing . . . . . . . . . . . . . . . . . . . . . 161
11.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Glossary Symbol Description
C q ( f , − f ) characteristic function for correlated stationary timing errors |C( f )|
δ
−2
−1 C ox oxide capacitance per unit area F m
F C on output capacitance of a switched-on current source F C o f f output capacitance of a switched-off current source F C C total clock node capacitance F C CD output capacitance of the clock driver F C D self output load capacitance of the driver F C gd MOS gate drain capacitance F C G gate capacitance of the current switches F C int interconnect capacitance between driver and current switches F C Int clock interconnect network capacitance F C ov MOS overlap capacitance per unit width F m
C u capacitance difference between switched on and off phases of a switched current source
2 characteristics function for uncorrelated stationary timing errors
µ m
Unit A
C k −l ( f k , f l ) characteristic function for timing errors
−m (t n ,t m ) joint probability density function of timing errors
2 higher frequency limit of a bandpass signal Hz c n
B
1 lower frequency limit of a bandpass signal Hz
A D gain of a driver A V th threshold mismatch process parameter mV µ m B
β current factor mismatch process parameter
(t) delta pulse ∆I k unit error of the k-th current source A
∆t timing error created by a circuit (accompanied by a subscript) sec
d i (m) thermometer bit i as a function of discrete time index mGlossary
2 E { ˆ
2 R z (m, m + q) probabilistic autocorrelation of the DT process z(m)
V
2 or A
2 ˆ
R z (m, m + q) empirical autocorrelation of the DT process z(m)
V
2 or A
2 R y (
τ
) averaged probabilistic autocorrelation
V
2 or A
R y (
V
τ
)} mean of the empirical autocorrelation
V
2 or A
2 S y ( f ) probabilistic power spectrum of the CT process y(t) W Hz −1
ˆS y ( f ) empirical power spectrum of the CT process y(t) W Hz
−1 S y ( f ) averaged probabilistic power spectrum of the CT process y(t)
W Hz −1
E { ˆ
S y ( f )} mean of the empirical power spectrum of the CT process y(t) W Hz −1
R z (0) power of z(m) W R L output DAC resistive load Ω
σ spread of timing errors sec
s (t) output signal of the DAC V or A
2 or A
) empirical autocorrelation of the CT process y(t)
E {} expectation with respect to the probability density function (PDF) of the function under consideration f frequency
N B bits remaining in binary code N T bits decoded in thermometer code p r (t) rectangular pulse p (t) sinc interpolation pulse
Hz f
1 lower band frequency limit Hz f
2 higher band frequency limit Hz f N Nyquist frequency Hz h
(t) arbitrary interpolation pulse |H( f )|
2 energy spectral density of an arbitrary pulse h(t) Hz
−2
I reference (LSB) current of the DAC A
I norm (w) normalized current amplitude as a function of w A
I u current generated by a switched current cell A
I FS full scale current of the DAC A
J p (x) Bessel function of the first kind K number of bands
λ frequency normalized over f s
L MOS transistor length m
m discrete time indexµ i local timing error of each circuit element i sec µ m timing errors as a function of the time index m sec
N number of bits
P total signal power including signal and noise W
P B power of a signal in a band Wτ
P k power of the k-th harmonic of a signal W P max power of the largest spurious component in the band of interest W P N noise power W
|P r ( f )|
2 energy spectral density of a rectangular pulse p r (t) Hz
−2 P S signal power
W
r µ (m, q) correlation function of the timing error series { µ m } sec
2 R y (t,t +
τ
) probabilistic autocorrelation of the CT process y(t)
V
2 or A
2 ˆ
R y (
x
Glossary
µ i
W MOS transistor width m |Y ( f )| magnitude spectrum of y(t) V or A z (m) generic discrete time signal V or A
Z u ( f ) output impedance of a switched current cell vs. frequency Ω
V th Threshold voltage V w (m) integer value of D(m)
V V swi voltage swing
V V ss negative power supply
V V re f reference voltage
V V L voltage swing of a latch
V V D voltage swing of a driver
V dd positive power supply
−2 ˆv(t, w) general description of the normalized pulse V or A
2 energy spectral density of a step pulse u(t) Hz
u (t) unit step |U( f )|
ˆu(t, w) normalized pulse for local timing errors
S amplitude of the power spectral density
Tr (m − 1, m) normalized transition from sample to sample V or A T s Sampling period sec
2 sec
t m non-uniform timing moments sec
1 → w
2 ) equivalent timing error for the transistion w
1 , w
T E (w
t time variable sec t ox oxide thickness m
T width of a return to zero pulse sec
τ time constant (accompanied with subscripts) sec τ (w) DAC output node time constant as a function of w sec τ u DAC output node time constant increment per each step of w sec
−1
) power spectral density of z(m) W normalized Hz S z ( f ) power spectral density of z(t) W sec
S z (t) first derivative of z(t)(instantaneous slope) V sec
λ
W S DT z (
xi Abbreviations AC Alternating Current ADC Analog-to-Digital Converter AM Amplitude Modulation BER Bit Error Rate BJT Bipolar Junction Transinstor CAD Computer Aided Design CML Current Mode Logic CMOS Complementary Metal Oxide Semiconductor CS Current Steering CT Continous Time DAC Digital-to-Analog Converter DC Direct Current DEM Dynamic Element Matching DNL Differential Non Linearity DT Discrete Time DT/CT Discrete Time to Continous Time conversion ECL Emitter Coupled Logic ESD Energy Spectral Density FM Frequency Modulation HD2,HD3 Second and third order harmonic distortion HW Hardware
INL Integral Non Linearity LSB Least Significant Bit MSB Most Singificant Bit NRZ Non Return to Zero PPM Pulse Position Modulation PSD Power Spectral Density PWL Piece-wise Linear PWM Pulse Width Modulation PDM Pulse Duration Modulation RZ Return to Zero
Abbre viations
SC Switched Capacitor SI Switched Current SDR Signal to Distortion Ratio SFDR Spurious Free Dynamic Range SNDR Signal to Noise and Distortio Ratio SNR Signal to Noise Ratio T/H Track and Hold THD Total Harmonic Distortion WSS Wide Sense Stationary
xiv
Preface
IGH-SPEED Digital to Analog (D/A) converters are essential components in digi- tal communication systems providing the necessary conversion of signals encoding
H
information in bits to signals encoding information in their amplitude vs. time domain characteristics. In general, they are parts of a larger system, the interface, which con- sists of several signal conditioning circuits. Dependent on where the converter is located within the chain of circuits in the interface, signal processing operations are partitioned in those realized with digital techniques, and those with analog.
The rapid evolution of CMOS technology has established implicit and explicite trends related to the interface, and in particular to the D/A converter. The implicit relationship comes via the growth of digital systems. First, it is a global trend with respect to all interface circuits that increasing operating frequencies of digital systems place a similar demand for the interface circuits. The second trend takes place locally within the inter- face. Initially, the D/A converter was placed at the beginning of the interface chain, and all signal conditioning was implemented in the analog domain after the D/A conversion. The increasing flexibility and robustness of digital signal processing shifted the D/A converter closer to the end point of the chain where the demands for high quality high frequency operation are very high. Third, there is a gradual change in the signal properties and spec- ifications, which reflect to the rapid widening of application range, to user requirements, and of course to environmental constraints relevant to the application. Explicit trends are established by the direct impact of physical constrains of the technology on converters. One of them concerns how information is distributed in the amplitude and time domains. Modern CMOS technologies allow less and less room to use the amplitude domain due to decreasing power supply levels but not decreasing noise and interference levels. Instead, they offer plenty of room in the time domain.
Wideband high dynamic range D/A converters are carriers of these trends and enablers of modern multi-carrier communication applications. These converters are required to xvi Preface linearity and low noise levels. To further simplify the subsequent lowpass filtering and to allow efficient implementation of pre-distortion techniques for high data rate communi- cations sampling rates multiple times higher than the actual transmitted signal bandwidth are required. However, the demands placed by these trends can not be straightforwardly mapped to physical realization despite the potential offerings of modern technologies. As a result the D/A converter becomes one of the bottlenecks in system performance.
The Current Steering Digital to Analog Converter (CS DAC) offers the possibility for such wideband high dynamic range signal conversion. However, its potential to achieve high speed is limited by the fact that it exhibits strong nonlinear behavior at high fre- quencies, which is unwanted. This nonlinear behavior, especially at high frequencies, is dominated by mechanisms that can not be described as amplitude domain transfer func- tions between input and output signals, like for example the case of the nonlinear behavior of an operational amplifier. This nonlinear behavior is neither easy to understood, nor to cope with. It stems mainly from the way circuit imperfections affect the inherently nonlin- ear transient behavior of the signals the D/A converter generates. The appearance of such behavior reveals that there is limited knowledge about the CS DAC nonlinear behavior at high frequencies. As a result, there is a corresponding difficulty to bring a relationship between signals, user information, application aspects, internal aspects of the converter, environmental aspects, etc. in a generic form that would allow maximum exploitation of what modern technologies offer. The lack of knowledge brings up an ambiguity element in the CS DAC design phase that impedes performance progress.
This book provides a structured and comprehensive description of the nonlinear be- havior of the CS DAC and of ways to deal with it. In order to achieve this an analysis and synthesis framework of concepts will be built with a generic scope beyond this par- ticular architecture, and then the proposed concepts will be applied in practice with an IC implementation. The book consists of an introductory part about DACs (Chapters 1-2), a modeling and analysis part for Current Steering Digital to Analog Converters (chapters 3-9) and a synthesis part (Chapters 10 and 11). Chapters 1 and 2 deal with the general aspects of D/A converters, and those of the framework of analysis and synthesis that will be developed.
Chapters 3-6 concern CS DACs. In Chapter 3 architectural and circuit aspects of CS DACs are discussed. In Chapter 4, the current state of the art is examined which helps to formulate the characteristics of knowledge that needs to be developed about the behavior of this circuit. In Chapter 5 circuit error mechanisms due to hardware imperfections are analyzed, emphasizing those that limit high frequency performance. This chapter reviews and extends further existing knowledge about these error mechanisms. Chapter 6 deals with high level DAC modeling. The signal errors are mapped to principle causes within the physical hierarchy of the DAC and they are categorized to classes according to their principle characteristics with amplitude, time, spatial domains, and other properties.
Chapters 7-9 deal specifically with the class of timing errors which is the most signif- icant one for high frequencies. Chapter 7 addresses functional modeling issues of timing errors, and shows that they can be described with Pulse Position and Pulse Width Modu- Pref ace xvii common modulation mechanism, each error being a specific subcase of this mechanism that is determined by its other error properties. In chapter 8 the developed models are ap- plied to spatially local timing errors (timing skew between individual current transients) which is one of the most important but least understood high frequency error mechanisms.
In chapter 9 these errors are analyzed in circuit details, moving from the functional as- pects to circuit and transistor level ones. All analysis results are then combined to reveal interesting design tradeoffs.
Chapters 10 and 11 deal with DAC synthesis. A generic view of DAC synthesis is pre- sented in chapter 10. The information available about a CS DAC is classified according to its type (e.g. information about signals, errors, application, user, etc.) and properties. Of particular importance is the definition of a-priori information, which is information about the DAC known at the design phase, and a-posteriori information obtained only after chip implementation. It is explained that current DACs use only a-priori information to deal with the dominant high-frequency error mechanisms. The use of a-posteriori information can provide a next step in DAC performance and efficiency. Two methods that can deal with local timing errors are discussed.
Chapter 11 presents the design of a concept driven 12 bit 500 Msample/s DAC IC in a CMOS 0.18 µ m process that achieves exceptionally high performance at low power consumption and occupying small area. The DAC is optimized using only a-priori infor- mation about error generation mechanisms to investigate the limits of this approach.
1 Digital to Analog conversion concepts
UNCTIONAL , algorithmic, signal processing, and circuit aspects of a Digital to Analog (D/A) converter will be briefly reviewed in this chapter. Definitions with
F respect to these aspects and D/A converters architectures will be given.
1.1 Functional aspects
1.1.1 Definition of the D/A function
The term Digital to Analog (D/A) conversion describes the conversion of a signal that represents data in Digital format to a signal that represents data in Analog format. This description excludes the electrical nature of conversion, and refers basically to how infor- mation is represented, i.e. in digital or in analog form. When one speaks of an electronic Digital to Analog converter there are additional conversions that take place.
An electronic linear D/A converter is an electronic circuit that accepts at its input a set of electrical signals, that represent a digital numeric code, and yields at its output an analog electrical signal, i.e. in proportion to a reference electrical quantity as the input numeric code is to the full range of possible codes. A full list of the electronic character- istics that the ideal electronic D/A converter must satisfy are described in [1]. It is indeed tempting to reduce the definition of the D/A converter to a statement similar to “the con- version of an input code word to an output electric quantity”, neglecting completely the electrical waveform characteristics of the input signal. Because information in the input electrical signal is defined very accurately with the use of only two digits, the input elec- trical signals can be abstracted to generic signals described by a sequence of values; it
2 Chapter 1 Digital to Analog conversion concepts (CT) electrical signals that use specific voltage levels to represent logic levels. Since the electrical nature of the input signal can be neglected the only relevant “time” issue is the sequence of the input samples.
On the basis of this reduction an N bit linear D/A converter is the electronic system that represents an N bit binary word D = D at its input with an electrical quantity
1 D
2 ...D Nat its output (usually voltage or current) that has amplitude or time domain characteristics that are modulated in proportion to the value of the code word and to a reference quantity.
Code conversion Electrical signal creation Waveform shaping
amplitude and time references
C Ts s(t) w(m) D(m) binary DT Pulse to integer h(t)
CT Figure 1.1 D/A conversion in the amplitude domain.
A functional diagram of the D/A conversion when the information is placed in the amplitude domain is given in fig. 1.1. The generic input signal is represented by the sequence of code words D(m). In the first stage of the diagram, the words D(m) are converted into the integer values w(m). The second stage represents the creation of the electrical signal that possesses physical dimensions. This is realized using amplitude and time references. A multiplication assigns the amplitude dimensions to the abstract signal. The Discrete-to-Continuous time conversion (DT/CT) assigns the time domain properties to the signal. The last sub-function of the D/A function is the shaping (filtering) of the generated electrical signal to obtain the predetermined shape (e.g. interpolation). The result of the three sub-functions is an electrical signal consisting of pulses that are amplitude modulated by the integer equivalent w(m) of the binary words D(m).
Where exactly the time domain conversion takes place does not imply any physical necessity, rather it represents the subjectiveness of the model. Physically, time domain exists in D(m) and can not be separated from it. From a modeling perspective, such a dis- tinction defines at which point time domain issues are important at the realized hardware and can not be neglected any more. For example, if a Track and Hold (T/H) circuit is used at the output to re-sample the signal and clean it from artifacts that appear at the switching transients, the time domain assignment takes place there. It should be mentioned that the term DT is misleading, because it implies that time is involved in the signal D(m); this is not true since the only relevant issue in D(m) is the sequence (the order) of the values.
The D/A conversion function with information encapsulated in the time domain of an electrical signal is given in fig. 1.2 and can be explained in a similar manner. In summary,
1.1 Functional aspects 3 code conversion in the abstract amplitude domain. conversion from the abstract to the electrical signal domain. It consists of amplitude and time domain signal creation with the use of references (e,g, voltage, current).
Electrical signal shaping (filtering) in which the electrical signal takes a predeter- mined pulse shape modulated by the integer value w.
Code conversion Electrical signal creation
time and amplitude references TsC D(m) s(t) w(m) binary PWM to integer
Figure 1.2 D/A conversion in the time domain.In this description of a D/A converter with figures 1.1 and 1.2 there is no coupling of the types of sub-operations and no transparency on the way of implementing each of them. In practice, all three sub-functions come together every time a specific algorithm is instantiated to realize the D/A function. The D/A converter that performs the 1-1 mapping of an input code to an output electrical signal as defined by the previously mentioned operations will be referred to as a D/A converter core, or simply a DAC core.
1.1.2 Functional specifications
A real D/A converter is subject to many physical imperfections that introduce limitations to its functionality. The DAC is designed such that it complies with a set of functional specifications, which can be embraced under the term “signal quality” within a well de- fined area of electrical and environmental conditions. Specifications include
Functional specifications that express whether the signal quality offered by the hardware complies to a prespecified range. Resolution, absolute accuracy, con- version rate, dynamic range are typical examples. Physical specifications that describe the physical resources required (area, power etc) for the hardware to deliver a prespecified signal quality.
Environmental specifications that describe the conditions under which the hardware can operate with a predetermined signal quality. Temperature is a typical example. Hardware quality depends on the factors considered relevant for a given application. Of- ten, figures of merit are defined to capture a combination of functional and physical spec- ifications (e.g. energy per conversion per frequency for a specific accuracy). Functional
4 Chapter 1 Digital to Analog conversion concepts Signal quality receives proper meaning by defining how information is embodied in the characteristics of the electrical signal, and how these are affected by physical imper- fections. In an ADC (see fig. 1.3) all errors due to physical imperfections are embodied
Input Input Output Output 00111 ADC DAC
All problems are embodied Problems are distributed in
in the amplitude domain (codewords) the amplitude and time domainsFigure 1.3 Dynamic problems affecting amplitude and time domains of DAC/ADC output signals.in the amplitude domain of the output signal (the codewords). In a DAC the output sig- nal consists of a series of pulses. Therefore, errors related to limitations in the dynamic response of the DAC are embodied in the characteristics of pulse to pulse transitions (fig. 1.3). These dynamic phenomena decay substantially at the end of the sampling period and the settled (DC) value of the converter can be determined. Therefore, the impact of physical problems in the functional behavior of the DAC is distributed in both amplitude and time domains at the output signal and each problem can be mapped to a specific de- formation of the ideally expected waveform (overshoot, delay, settling, etc.); in contrast, in an ADC everything ends to amplitude domain errors. Consequently, the revelant issue for DAC’s is which output waveform characteristics are relevant for a given application.
A major distinction is between static and dynamic performance evaluation. This refers to the use of time invariant, or variant input signals (e.g. sinusoids), respectively. The lat- ter result in dynamics of transients that dominate the performance. One way of assessing dynamic performance is based on the time domain response of the DAC for a full scale pulse as input (fig. 1.4). This method relies on evaluation of waveform characteristics such as the time it takes for the output signal to settle within a specified value (e.g. LSB). Other criteria include the rise/fall times, or the glitch magnitude compared to an LSB value. Evaluating time domain electrical characteristics was exercised until the beginning
1
of the 90’s. The shift of interest to the spectral properties of signals was essentially a shift from characterizing hardware at a higher layer, following the trends of digital processing systems evolution toward larger signal processing systems.
Sinusoidal signals are the most widely adopted type of signals used for performance evaluation. When processing sinusoids, any waveform deformation that generates (non) harmonic distortion is relevant to performance. Before giving the figures of merit that describe linearity it is insightful to give a brief description of the concept of linearity.
1 Static and dynamic performance terminology for ADCs and DACs is given in [2], expressing the methods
1.1 Functional aspects
5
overshoot and glitches < LSB LSB LSB settles to 1 LSB error
LSB Settling time Figure 1.4
Full scale transition: (a) settling time and (b) amplitude based eval- uation of dynamic performance. Nonlinear distortion is the distortion caused by a deviation from a linear relationship between specified input and output parameters of a system or component. For the DAC, nonlinear distortion refers to its input-output functional relationship. Yet, further specifi- cation is required to define which particular aspects of this relationship are relevant.
The DAC realizes a transfer function between its input and output signal amplitudes. For an ideal DAC this linear function can be described as s = α α is a gain
· w, where factor while s and w have their usual meaning. Time domain effects are not included here; it simply defines the output settled, or DC, signal value that corresponds to an input value. In practice, the transfer function is not linear and shows deviations. It can be modeled as
2
3 ν
a -th order polynomial s = + + ν α
1 w α 2 w α 3 w + ... α w . The degree of deviation from ν
the ideal transfer function determines the accuracy of the converter. Because only static signals are assumed, it can be called static nonlinearity. Neglecting the inherent dynamics of the DAC but using a time-variant signal, a nonlinear error is generated at the output that changes over time. The only dynamic phenomenon here relates to the signal.
In reality time-variant signals are processed by a DAC that in addition involves certain dynamic behavior. For a input sample to sample transition, an output signal transient is composed. The nonlinear errors in these case extend to the nonlinear relationship between the output signal transients, which are different for different input sample transitions. Errors generated in this way are also dynamic nonlinear errors, but dynamic applies now both to the signal and the inherent dynamics of the DAC. In practice, the DAC dynamics are dominant as frequencies increase beyond a few MHz.
Number of bits
The number of bits N of the DAC represents the relative accuracy with which a full scale electrical signal range can be represented in discrete steps. Observe that in a DAC quan- tization noise or distortion is not a relevant issue since by nature of the DAC function it
6 Chapter 1 Digital to Analog conversion concepts
Differential and Integral Non-Linearity