03 Top Level View of Computer Function and Interconnection
Willia m St a llings Willia m St a llings Com put e r Orga niza t ion a nd Arc hit e c t ure a nd Arc hit e c t ure
t h
8 Edit ion
Cha pt e r 3
T op Le ve l V ie w of Com put e r
Func t ion a nd I nt e rc onne c t ion
Progra m Conc e pt g p
Hardwired syst em s are inflexible •
- G General purpose hardw are can do l h d d
different t asks, given correct cont rol signals i l I nst ead of re- wiring, supply a new set of • cont rol signals
Wha t is a progra m ? p g
A sequence of st eps • For each st ep, an arit hm et ic or logical • h h l l operat ion is done For each operat ion, a different set of • cont rol signals is needed
Func t ion of Cont rol U nit
For each operat ion a unique code is • provided provided — e.g. ADD, MOVE
A hardware segm ent accept s t he code and • issues t he cont rol signals We have a com put er! We have a com put er! •
Com pone nt s p
The Cont rol Unit and t he Arit hm et ic and • Logic Unit const it ut e t he Cent ral Logic Unit const it ut e t he Cent ral Processing Unit
- Dat a and inst ruct ions need t o get int o t he d i i d i h
syst em and result s out — I nput / out put
Tem porary st orage of code and result s is • needed
:
Fe t c h Cyc le y
Program Count er ( PC) holds address of • next inst ruct ion t o fet ch next inst ruct ion t o fet ch Processor fet ches inst ruct ion from • m em ory locat ion point ed t o by PC l i i d b C I ncrem ent PC •
— Unless t old ot herw ise I nst ruct ion loaded int o I nst ruct ion I nst ruct ion loaded int o I nst ruct ion •
Ex e c ut e Cyc le y
- Processor- m em ory
— d t t f b t CPU d i dat a t ransfer bet ween CPU and m ain m em ory
- Processor I / O
— Dat a t ransfer bet w een CPU and I / O m odule
- Dat a processing p g
— Som e arit hm et ic or logical operat ion on dat a
- Cont rol Cont rol
n o ti u c e
m ra g g ia D
I nt e rrupt s p
Mechanism by w hich ot her m odules ( e.g. •
I / O) m ay int errupt norm al sequence of I / O) m ay int errupt norm al sequence of
processing Program •— e.g. overflow , division by zero Tim er •
— Generat ed by int ernal processor t im er y p — Used in pre- em pt ive m ult i- t asking
I nt e rrupt Cyc le p y
Added t o inst ruct ion cycle • Processor checks for int errupt • h k f — I ndicat ed by an int errupt signal
I f no int errupt , fet ch next inst ruct ion •
- I f int errupt pending: I f int errupt pending:
— Suspend execut ion of current program — Save cont ext Save cont ext
ts p p u rr te n
ts p p u rr te n
I nst ruc t ion Cyc le (w it h I nt e rrupt s) - St a t e Dia gra m g
M ult iple I nt e rrupt s p p
Disable int errupt s • — P Processor will ignore furt her int errupt s whilst ill i f t h i t t hil t processing one int errupt
— I nt errupt s rem ain pending and are checked I nt errupt s rem ain pending and are checked
aft er first int errupt has been processed— — I nt errupt s handled in sequence as t hey occur I nt errupt s handled in sequence as t hey occur Define priorit ies •
— L Low priorit y int errupt s can be int errupt ed by i it i t t b i t t d b
l a ti n e u q q
d te s
ts p p u rr te n
I le p ip
— Mem ory — I nput / Out put — CPU
Conne c t ing g
- All t he unit s m ust be connect ed
- ff f f d ff Different t ype of connect ion for different t ype of unit
— Read — Writ e — Tim ing
M e m ory Conne c t ion y
- Receives and sends dat a
- dd ( f l ) Receives addresses ( of locat i
- Receives cont rol signals
I nput /Out put Conne c t ion(1 ) p p ( )
Sim ilar t o m em ory from com put er’s • viewpoint viewpoint Out put •
— Receive dat a from com put er — Send dat a t o peripheral I nput •
— Receive dat a from peripheral p p
I nput /Out put Conne c t ion(2 ) p p ( )
Receive cont rol signals from com put er • S Send cont rol signals t o peripherals d l l h l • — e.g. spin disk
Receive addresses from com put er • — e.g. port num ber t o ident ify peripheral g p y p p
Send int errupt signals ( cont rol) •
CPU Conne c t ion
- Reads inst ruct ion and dat a
d ( f ) • Writ es out dat a ( aft er processing)
• Sends cont rol signals t o ot her unit s
- Receives ( & act s on) int errupt s
Buse s
There are a num ber of possible • int erconnect ion syst em s int erconnect ion syst em s Single and m ult iple BUS st ruct ures are • m ost com m on e.g. Cont rol/ Address/ Dat a bus ( PC) • e.g. Unibus ( DEC- PDP) •
Wha t is a Bus?
A com m unicat ion pat hway connect ing t wo • or m ore devices or m ore devices Usually broadcast • Oft en grouped •
— A num ber of channels in one bus
— e.g. 32 bit dat a bus is 32 separat e single bit
channelsDa t a Bus
Carries dat a • — Rem em ber t hat t here is no difference bet ween R b t h t t h i diff b t
“ dat a” and “ inst ruct ion” at t his level Widt h is a key det erm inant of • Widt h i k d t i t f perform ance
— 8, 16, 32, 64 bit b
Addre ss bus
I dent ify t he source or dest inat ion of dat a • e.g. CPU needs t o read an inst ruct ion • C d d
( dat a) from a given locat ion in m em ory
Bus widt h det erm ines m axim um m em ory • capacit y of syst em— e.g. 8080 has 16 bit address bus giving 64k address space
Cont rol Bus
Cont rol and t im ing inform at ion • — Mem ory read/ writ e signal M d/ it i l — I nt errupt request — Clock signals Cl k i l
e m e h
Big a nd Y e llow ? g
What do buses look like? • — Parallel lines on circuit boards P ll l li i it b d — Ribbon cables — St rip connect ors on m ot her boards S i h b d e.g. PCI –
— Set s of wires Set s of i es
re tu c e it h rc A s u B
Single Bus Proble m s g
- Lot s of devices on one bus leads t o:
P t i d l — Propagat ion delays
- – Long dat a pat hs m ean t hat co- ordinat ion of bus use
can adversely affect perform ance can adversely affect perform ance
- – I f aggregat e dat a t ransfer approaches bus capacit y
- Most syst em s use m ult iple buses t o Most syst em s use m ult iple buses t o
overcom e t hese problem s
Bus T ype s yp
- Dedicat ed
S t d t & dd li — Separat e dat a & address lines
- Mult iplexed
— Shared lines — Address valid or dat a valid cont rol line — Advant age - fewer lines — Disadvant ages
- – More com plex cont rol
Bus Arbit ra t ion
More t han one m odule cont rolling t he bus • e.g. CPU and DMA cont roller • C d ll Only one m odule m ay cont rol bus at one • t im e Arbit rat ion m ay be cent ralised or b t at o ay be ce t a sed o • dist ribut ed
Ce nt ra lise d or Dist ribut e d Arbit ra t ion
Cent ralised • — Single hardw are device cont rolling bus access Si l h d d i t lli b
Bus Cont roller – Arbit er – Arbit er – — May be part of CPU or separat e
Dist ribut ed • Dist ribut ed • — Each m odule m ay claim t he bus — Cont rol logic on all m odules C t l l i ll d l
S h • Synchronous — Event s det erm ined by clock signals — Cont rol Bus includes clock line — A single 1- 0 is a bus cycle — All devices can read clock line — Usually sync on leading edge — Usually a single cycle for an event
T im ing g
- Co- ordinat ion of event s on bus
m ra g g
m ra g g ia D d a e R
m ra g g ia D te ri W
PCI Bus
• Peripheral Com ponent I nt erconnect ion
- l l d bl d I nt el released t o public dom>32 or 64 bit
- 50 lines
PCI Bus Line s (re quire d) ( q )
- Syst em s lines
I l di l k d t — I ncluding clock and reset
- Address & Dat a
— 32 t im e m ux lines for address/ dat a — I nt errupt & validat e lines
- I nt erface Cont rol
- Arbit rat ion Arbit rat ion
PCI Bus Line s (Opt iona l) ( p )
- I nt errupt lines
N t h d — Not shared
- Cache support
- 64- bit Bus Ext ension
— Addit ional 32 lines — Tim e m ult iplexed — 2 lines t o enable devices t o agree t o use 64- g bit t ransfer
PCI Com m a nds
Transact ion bet ween init iat or ( m ast er) • and t arget and t arget Mast er claim s bus •
- Det erm ine t ype of t ransact ion
— e.g. I / O read/ w rit e Address phase • One or m ore dat a phases • One or m ore dat a phases •
m
Fore ground Re a ding g g