Multiple ADC0801 Series to MC6800 CPU Interface
Functional Description
Continued
Note 22: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.
SAMPLE PROGRAM FOR Figure 15 ADC0801-MC6800 CPU INTERFACE
DS005671-A1
DS005671-25
FIGURE 16. ADC0801–MC6820 PIA Interface
ADC0801ADC0802ADC0803ADC0804ADC0805
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Functional Description
Continued
The following schematic and sample subroutine DATA IN may be used to interface up to 8 ADC0801’s directly to the
MC6800 CPU. This scheme can easily be extended to allow the interface of more converters. In this configuration the
converters are arbitrarily located at HEX address 5000 in the MC6800 memory space. To save components, the clock
signal is derived from just one RC pair on the first converter. This output drives the other ADs.
All the converters are started simultaneously with a STORE instruction at HEX address 5000. Note that any other HEX
address of the form 5XXX will be decoded by the circuit, pulling all the CS inputs low. This can easily be avoided by
using a more definitive address decoding scheme. All the interrupts are ORed together to insure that all ADs have
completed their conversion before the microprocessor is interrupted.
The subroutine, DATA IN, may be called from anywhere in the user’s program. Once called, this routine initializes the
CPU, starts all the converters simultaneously and waits for the interrupt signal. Upon receiving the interrupt, it reads the
converters from HEX addresses 5000 through 5007 and stores the data successively at arbitrarily chosen HEX
addresses 0200 to 0207, before returning to the user’s pro- gram. All CPU registers then recover the original data they
had before servicing DATA IN.