ISSN: 1693-6930
TELKOMNIKA Vol. 14, No. 2A, June 2016 : 152 – 161
153 Design for test is divided into circuit-level design for test IC design for test, and
electronic equipment system-level design for testability electronic system design for test. IC design for testability of the key objectives is to measure to ensure the qualified products
produced; and electronic system design for test in the test under the premise, more concerned about how easy test to improve test efficiency, reduce cost of test [5]. Thus, design for test is
generally more concerned about the fault coverage and testability of electronic system-level design will have to also care for fault detection rate, isolation rate, testing costs, and many other
indicators.
2.2. Related Work
Fault propagation is studied widely recently. Zhou [6] proposed an in innovative ontology-based fault path analysis to analyze transient fault propagation effects in networked
control systems. Y Haibin [7] developed a simulation model based on directed fault propagation graph. There is gaining research on fault propagation analysis using small world network
algorithm and applied them in large-scale systems [8-10]. Prasad and Babu [11] proposed the concept of minimal set of test nodes in analog circuit fault diagnosis, and proposed polynomial
time algorithms for the first time to generate such sets. Meanwhile, they used greedy algorithm to solve the minimum test set, to get local optimal solution. Starzyk and Liu [12] also used the
greedy algorithm, but for the information entropy heuristic function. In addition, using more reasonable method to solve the test points selection. This method is better than the previous
method, but still only get a local minimum and the time and complexity is higher than the method of Prasad. Demichev A and Ilyin V [14] studied the resilience of the most important
properties of stochastic and regular small-world interconnection networks and give a comparison of fault tolerance ability of regular and irregular networks. However, most of these
methods are based on graph theory [15], and the traditional path search method is not suitable for large-scale system. Y Li [16] proposed a new shortest path to all path algorithms and it can
be used in fault propagation. Test points selection methods for the self-testing based analogue fault diagnosis system. The purpose of making such a selection is to increase the testability of
the self-testing algorithm which is used to locate the defective components of a given analogue circuit.
Currently, test points selection for analog circuits has achieved more results. However research for system-level points selection is few. In addition, combining the points selection and
test sequences together, computational complexity is relatively high. We designed the small world algorithm including the information of nodes. The proposed method could be used to
setting fault test points and fault propagation path. This approach is different than conventional analysis methods, and can be used to larger complex electronic system.
The remainder of this paper is organized as follows: Section 3 describes the methodology of the small world algorithm for system fault path searching. Section 4 presents
experiments to evaluate the performance of the algorithm including the results, analysis, and discussion. Section 5 summarizes the conclusions.
3. Method 3.1. Description of Small World Algorithm
