computing device. Parallel pipeline architec based processing. Hence in XSTREAM, bas
all the processes involved, block size is fixed input data.
Table 1. Mapping of tasks to computing dev The first stage, which is mapped to a FPGA
does FSC validation and time stamping. The the second stage, which is mapped to CPU
decompression and block identification ta Additionally, second stage also performs aux
is completely an independent task and can b The result of second stage viz., decomp
discrete stagger values, are passed to GPU stage of the pipelined architecture, propo
software. The GPU performs decompre normalization and stagger corrections as
kernels. The result of the third stage is a resolution image and is sent back to the hos
uses a high speed PCIex16 bus for comm host. Finally, the geo-tagging and writing to
separate dedicated thread with asynchron depicts the three way pipeline architecture of
Figure 2. Three way pipeline processing ado Stage
Step No. Function
Mappe on to
Stage 1 i
ii FSC Logic
Valid Frame Detection Time Stamping
FPGA FPGA
Stage 2 iii
iv Decode
Aux Separation RS-Decoding
CPU CPU
Stage 2 vi
Decompression Marker Search
CPU Stage 3
vi Code block decoding
GPU Stage 2
vii Aux Processing
CPU Stage 2
viii Stagger Estimation
OAT based Image Based CPU
GPU Stage 3
ix Radiometric Correction
GPU Stage 2
x I
and Q
Channel Misalignment due to frame
loss CPU
Stage 3 xi
Stagger Correction GPU
Stage 2 xii, xiii
Geo Tagging and File creation
CPU tecture requires buffer
ased on constraints of ed to three seconds of
devices GA acquires the data,
The result is passed to PU, where decoding,
tasks are performed. aux processing, which
n be executed on CPU. pression blocks and
U, which is the third posed in XSTREAM
pression, radiometric as three independent
a full swath and full host system. The GPU
municating with the to a file is done in a
ronous IO. Figure 2 of XSTREAM.
dopted in XSTREAM
2.3 XSTREAM System and Pro
Based on the analysis the XST asfourseparate processes, namel
Acquisition’, ‘RT Data processing display’ and ‘XScheduler’.This is
propagation of failure of one modu engineered such that it can work in
Real-Time Acquisition module is data and writing the valid frames
data can also be flushed to disk in pass for analysis and playback
adopted to providefail-safe optio Processing.
The ‘RT Data processing’ module the data in blocks and in real-time
steps as discussed in section 2.2. ‘RT Full resolution Display’ disp
products on a multi-screen display minimal navigational aids such a
jump to arbitrary location with enhancements, such as contrast str
used in offline mode to view alread The ‘XScheduler’ controls all the
status information, error messages action, logs etc., on a GUI. All
controlledby XScheduler. One of t to handle clash scenario by providi
scheduling as well as manual overr for the pass schedules of each mis
schedule accordingly. Figure 3 shows the DFD an
XSTREAM software. The hardwa system is shown in Figure 4.
Figure 3. DFD-0 of XSTREA pped
Sequential Parallel
A A
Sequential Sequential
Sequential Block
level Data Parallel
Sequential Block
level Data Parallel
Sequential and iterative
Sequential Data Parallel
Sequential Data Parallel
Sequential
1 Pass Information form Pass Sched
including pass priority etc to XSch
2
Configuration Parameters from Sc start acquisition
3 Pass Information from Scheduler t
4 Display configuration from Sched
5
Acquired data from acquisition ca
6 Raw data from Dedicated memory
preprocessing
7 Processed data to RAM, Memory
8 No lines processed, No of strips pr
9 No lines to display from shared m
10 Processed data from RAM to Disp
11 No of lines processed from shared
updation
rocess architecture
TREAM softwareis designed ely ‘Real-TimeRT stream
ing’, ‘RT Full resolution scroll is to modularize and arrest the
dule to others. Every process is independently.
is responsible for acquiring the es into host memory area.The
in real-time or flushed after the k support. This procedure is
tion in case of failure in RT le is responsible for processing
me. Processing includes all the isplays the processed Level-1A
lay. The display also provides h as scroll speed adjustments,
ithin the strip and minimal stretch.This process can also be
ady processed strips. the processes and displays the
ges, alerts requiring immediate ll the real-time processes are
f the main tasks of scheduler is iding pre-emptive priority based
erride options.XScheduler polls ssion and updates the process
and process architecture of ware block diagram of the host
REAM Software modules
edule file, Pass Configurations Scheduler
Scheduler to Acquisition Process to er to Preprocessing
eduler to RT Display cards to Dedicated Memory
ory to RT Preprocessing module for ory mapped file
ps processed to Shared Memory d memory to RT Display
isplay red memory to X Scheduler for status
ISPRS Technical Commission VIII Symposium, 09 – 12 December 2014, Hyderabad, India
This contribution has been peer-reviewed. doi:10.5194isprsarchives-XL-8-1171-2014
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Figure 4. Hardware block diagram of XSTREAM system
2.4 XSTREAM Software Implementation Specifications