Page | 5
3. Typical Application Figure 1
Figure 1 Typical Application
Note: 3Pin – Null; MCU = Micro-computer Unite or single chip Computer
When the connecting cable is shorter than 20 metres, a 5K pull-up resistor is recommended; when the connecting cable is longer than 20 metres, choose a appropriate pull-up resistor as
needed.
4. Power and Pin
DHT11’s power supply is 3-5.5V DC. When power is supplied to the sensor, do not send any instruction to the sensor in within one second in order to pass the unstable status. One
capacitor valued 100nF can be added between VDD and GND for power filtering.
5. Communication Process: Serial Interface Single-Wire Two-Way
Single-bus data format is used for communication and synchronization between MCU and DHT11 sensor. One communication process is about 4ms.
Data consists of decimal and integral parts. A complete data transmission is 40bit, and the sensor sends higher data bit first.
Data format: 8bit integral RH data + 8bit decimal RH data + 8bit integral T data + 8bit decimal T
data + 8bit check sum. If the data transmission is right, the check-sum should be the last 8bit of 8bit integral RH data + 8bit decimal RH data + 8bit integral T data + 8bit decimal T data.
Page | 6
5.1 Overall Communication Process Figure 2, below
When MCU sends a start signal, DHT11 changes from the low-power-consumption mode to the running-mode, waiting for MCU completing the start signal. Once it is completed, DHT11 sends a
response signal of 40-bit data that include the relative humidity and temperature information to MCU. Users can choose to collect read some data. Without the start signal from MCU, DHT11
will not give the response signal to MCU. Once data is collected, DHT11 will change to the low- power-consumption mode until it receives a start signal from MCU again.
Figure 2 Overall Communication Process
5.2 MCU Sends out Start Signal to DHT Figure 3, below
Data Single-bus free status is at high voltage level. When the communication between MCU and DHT11 begins, the programme of MCU will set Data Single-bus voltage level from high to low
and this process must take at least 18ms to ensure DHT ’s detection of MCUs signal, then MCU
will pull up voltage and wait 20-40us for DHT’s response.
Figure 3 MCU Sends out Start Signal DHT Responses
Page | 7
5.3 DHT Responses to MCU Figure 3, above
Once DHT detects the start signal, it will send out a low-voltage-level response signal, which lasts 80us. Then the programme of DHT sets Data Single-bus voltage level from low to high and
keeps it for 80us for DHT’s preparation for sending data.
When DATA Single-Bus is at the low voltage level, this means that DHT is sending the response signal. Once DHT sent out the response signal, it pulls up voltage and keeps it for 80us and
prepares for data transmission. When DHT is sending data to MCU, every bit of data begins with the 50us low-voltage-level and
the length of the following high-voltage-level signal determines whether data bit is 0 or 1 see Figures 4 and 5 below.
Figure 4 Data 0 Indication
Page | 8
Figure 5 Data 1 Indication
If the response signal from DHT is always at high-voltage-level, it suggests that DHT is not responding properly and please check the connection. When the last bit data is transmitted,
DHT11 pulls down the voltage level and keeps it for 50us. Then the Single-Bus voltage will be pulled up by the resistor to set it back to the free status.
6. Electrical Characteristics
VDD=5V, T = 25℃ unless otherwise stated
Note: Sampling period at intervals should be no less than 1 second.
7. Attentions of application
1 Operating conditions
Applying the DHT11 sensor beyond its working range stated in this datasheet can result in 3RH signal shiftdiscrepancy. The DHT11 sensor can recover to the calibrated status gradually when
it gets back to the normal operating condition and works within its range. Please refer to 3 of Conditions
Minimum Typical
Maximum Power Supply
DC 3V
5V 5.5V
Current Supply
Measuring 0.5mA
2.5mA Average
0.2mA 1mA
Standby 100uA
150uA Sampling
period Second
1
Page | 9 this section to accelerate its recovery. Please be aware that operating the DHT11 sensor in the
non-normal working conditions will accelerate sensor ’s aging process.
2 Attention to chemical materials
Vapor from chemical materials may interfere with DHT’s sensitive-elements and debase its
sensitivity. A high degree of chemical contamination can permanently damage the sensor.
3 Restoration process when 1 2 happen
Step one: Keep the DHT sensor at the condition of Temperature 50~60Celsius, humidity 10RH for 2 hours;
Step two:K keep the DHT sensor at the condition of Temperature 20~30Celsius, humidity 70RH for 5 hours.
4 Temperature Affect
Relative humidity largely depends on temperature. Although temperature compensation technology is used to ensure accurate measurement of RH, it is still strongly advised to keep the
humidity and temperature sensors working under the same temperature. DHT11 should be mounted at the place as far as possible from parts that may generate heat.
5 Light Affect
Long time exposure to strong sunlight and ultraviolet may debase DHT’s performance.
6 Connection wires
The quality of connection wires will affect the quality and distance of communication and high quality shielding-wire is recommended.
7 Other attentions
Welding temperature should be bellow 260Celsius and contact should take less than 10 seconds.
Avoid using the sensor under dew condition. Do not use this product in safety or emergency stop devices or any other occasion that failure
of DHT11 may cause personal injury. Storage: Keep the sensor at temperature 10-40℃, humidity 60RH.
Declaim:
This datasheet is a translated version of the manufacturer ’s datasheet. Although the due care
has been taken during the translation, D-Robotics is not responsible for the accuracy of the information contained in this document. Copyright © D-Robotics.
D-Robotics: www.droboticsonline.com
Email contact: d_roboticshotmail.co.uk
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products andor types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
NPN SILICON TRANSISTOR
2SC945
NPN SILICON TRANSISTOR
Document No. D17117EJ2V0DS00 2nd edition Previous No. TC-3005C
Date Published March 2004 N CPK Printed in Japan
c
The mark shows major revised points.
2004
DESCRIPTION
The 2SC945 is designed for use in driver stage of AF amplifier and low speed switching.
FEATURES
• High voltage LV
CEO
= 50 V MIN. • Excellent h
FE
linearity h
FE1
= 0.1 mAh
FE2
1.0 mA = 0.92 TYP.
ABSOLUTE MAXIMUM RATINGS
Maximum Temperature Storage
Temperature −55 to +150°C
Junction Temperature
+150°C Maximum Maximum Power Dissipation T
A
= 25°C Total Power Dissipation
250 mW Maximum Voltages and Currents T
A
= 25°C V
CBO
Collector to Base Voltage 60 V
V
CEO
Collector to Emitter Voltage 50 V
V
EBO
Emitter to Base Voltage 5.0 V
I
C
Collector Current 100 mA
I
B
Base Current 20 mA
ELECTRICAL CHARACTERISTICS T
A
= 25°C
CHARACTERISTIC SYMBOL TEST
CONDITIONS MIN.
TYP. MAX.
UNIT DC Current Gain
h
FE1
V
CE
= 6.0 V, I
C
= 0.1 mA 50
185 DC Current Gain
h
FE2
V
CE
= 6.0 V, I
C
= 1.0 mA 90
200 600
Gain Bandwidth Product f
T
V
CE
= 6.0 V, I
E
= −10 mA
250 MHz Collector to Base Capacitance
C
ob
V
CB
= 6.0 V, I
E
= 0, f = 1.0 MHz 3.0
pF Collector Cutoff Current
I
CBO
V
CB
= 60 V, I
E
= 0 A 100
nA Emitter Cutoff Current
I
EBO
V
EB
= 5.0 V, I
C
= 0 A 100
nA Base to Emitter Voltage
V
BE
V
CE
= 6.0 V, I
C
= 1.0 mA 0.55
0.62 0.65
V Collector Saturation Voltage
V
CEsat
I
C
= 100 mA, I
B
= 10 mA 0.15
0.3 V
Base Saturation Voltage V
BEsat
I
C
= 100 mA, I
B
= 10 mA 0.86
1.0 V
CLASSIFICATION OF h
FE2
Rank R Q P K Range
90 to 180 135 to 270
200 to 400 300 to 600
Remark h
FE2
Test Conditions: V
CE
= 6.0 V, I
C
= 1.0 mA
PACKAGE DRAWING Unit: mm
1.27 2.54
1.77 MAX. 4.2 MAX.
1 3
12.7 MIN. 5.5 MAX.
5.2 MAX.
φ
0.5
2 1. Emitter
2. Collector 3. Base
EIAJ: SC43B JEDEC: TO92
IEC: PA33
Data Sheet D17117EJ2V0DS
2
TYPICAL CHARACTERISTICS T
A
= 25°C, unless otherwise noted.
T
A
T
A
P
T
I
CBO
T
A
I
CBO
T
A
= 25
°
C I
C
V
CE
I
C
I
C
h
FE
h
FE
V
CE
I
C
I
C
V
BE
I
E
I
C
T
A
= 75° C
25°C
−
25°C V
CE
= 6.0 V V
CE
= 6.0 V
T
A
= 75
°C 25
°C
−
25 °C
V
BEsat
V
CEsat
I
C
= 10 A •
I
B
I
C
= 10 A
•
I
B
f
T
T
A
I
B
= 0.1 mA
V
BEsat
V
CEsat
V
CE
=10 V
V
CE
= 6.0 V
I
C
V
CE
I
B
= 0.1 mA
Data Sheet D17117EJ2V0DS
3
C
ib
I
C
= 0 A C
ob
I
E
= 0 A
C
ob
C
ib
V
EB
V
CB
h
fe
h
FE
V
CE
= 6.0 V I
C
= 1.0 mA V
CE
= 6.0 V I
C
= 1.0 mA V
CE
= 6.0 V I
C
= 1.0 mA
h
oe
h
re
h
ie
h
fe
h
oe
h
re
h
ie
V
CE
= 6.0 V f
= 1.0 kHz
H
e
h
e
I
C
h
e
I
C
= 1.0 mA
H
e
I
C
H
e
h
oe
h
oe
h
oe
h
re
h
re
h
fe
, h
ie
h
fe
h
oe
h
fe
h
re
h
re
h
ie
h
ie
h
fe
, h
ie
E
n V
CE
= 6.0 V
I
C
= 1.0 mA H
e
h
e
V
CE
h
e
V
CE
= 6.0 V
R
G
R
G
i
n
e
n
E
n
V
CE
I
C
E
n
I
n
E
n
I
n
The information in this document is current as of March, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products andor types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customers equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury including death to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: Standard, Special and Specific.
The Specific quality grade applies only to NEC Electronics products developed based on a customer- designated quality assurance program for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.
Special: Transportation equipment automobiles, trains, ships, etc., traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment not specifically designed for life support.
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application.
Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries. 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as
defined above. •
• •
•
•
•
M8E 02. 11-1
This datasheet has been download from: www.datasheetcatalog.com
Datasheets for electronics components.
AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
REV: 100208
GENERAL DESCRIPTION
The DS1307 serial real-time clock RTC is a low- power, full binary-coded decimal BCD clockcalendar
plus 56 bytes of NV SRAM. Address and data are transferred serially through an I
2
C, bidirectional bus. The clockcalendar provides seconds, minutes, hours,
day, date, month, and year information. The end of the month date is automatically adjusted for months
with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-
hour format with AMPM indicator. The DS1307 has a built-in power-sense circuit that detects power failures
and automatically switches to the backup supply. Timekeeping operation continues while the part
operates from the backup supply.
TYPICAL OPERATING CIRCUIT FEATURES
Real-Time Clock RTC Counts Seconds,
Minutes, Hours, Date of the Month, Month, Day of the week, and Year with Leap-Year
Compensation Valid Up to 2100
56-Byte, Battery-Backed, General-Purpose RAM with Unlimited Writes
I
2
C Serial Interface
Programmable Square-Wave Output Signal
Automatic Power-Fail Detect and Switch Circuitry
Consumes Less than 500nA in Battery-Backup Mode with Oscillator Running
Optional Industrial Temperature Range:
-40°C to +85°C
Available in 8-Pin Plastic DIP or SO
Underwriters Laboratories UL Recognized
PIN CONFIGURATIONS
V
CC
SCL SDA
X1 X2
V
BAT
GND SQWOUT
V
CC
SCL SDA
X1 X2
V
BAT
GND SQWOUT
PDIP 300 mils SO 150 mils
TOP VIEW
ORDERING INFORMATION
PART TEMP RANGE
VOLTAGE V PIN-PACKAGE TOP MARK
DS1307+ 0°C to +70°C
5.0 8 PDIP 300 mils
DS1307 DS1307N+
-40°C to +85°C 5.0
8 PDIP 300 mils DS1307N
DS1307Z+ 0°C to +70°C
5.0 8 SO 150 mils
DS1307 DS1307ZN+
-40°C to +85°C 5.0
8 SO 150 mils DS1307N
DS1307Z+TR 0°C to +70°C
5.0 8 SO 150 mils Tape and Reel DS1307
DS1307ZN+TR -40°C to +85°C
5.0 8 SO 150 mils Tape and Reel DS1307N
+Denotes a lead-freeRoHS-compliant package. A “+” anywhere on the top mark indicates a lead-free package. An “N” anywhere on the top mark indicates an industrial temperature range
device.
DS130
CPU V
CC
V
CC
V
CC
SDA SCL
GND X2
X1 V
CC
R
PU
R
PU
CRYSTAL
SQWOUT V
BAT R
PU
= t
r
C
b
DS1307 64 x 8, Serial, I
2
C Real-Time Clock
2 of 14
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground ................................................................................ -0.5V to +7.0V Operating Temperature Range Noncondensing
Commercial .......................................................................................................................... 0°C to +70°C Industrial ............................................................................................................................ -40°C to +85°C
Storage Temperature Range ......................................................................................................... -55°C to +125°C Soldering Temperature DIP, leads .................................................................................... +260°C for 10 seconds
Soldering Temperature surface mount…..……………………….Refer to the JPCJEDEC J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
T
A
= 0°C to +70°C, T
A
= -40°C to +85°C. Notes 1, 2
PARAMETER SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
Supply Voltage V
CC
4.5 5.0
5.5 V
Logic 1 Input V
IH
2.2 V
CC
+ 0.3 V
Logic 0 Input V
IL
-0.3 +0.8
V V
BAT
Battery Voltage V
BAT
2.0 3
3.5 V
DC ELECTRICAL CHARACTERISTICS
V
CC
= 4.5V to 5.5V; T
A
= 0°C to +70°C, T
A
= -40°C to +85°C. Notes 1, 2
PARAMETER SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
Input Leakage SCL I
LI
-1 1
µA IO Leakage SDA, SQWOUT
I
LO
-1 1
µA Logic 0 Output I
OL
= 5mA V
OL
0.4 V
Active Supply Current f
SCL
= 100kHz I
CCA
1.5 mA
Standby Current I
CCS
Note 3 200
µA V
BAT
Leakage Current I
BATLKG
5 50
nA Power-Fail Voltage V
BAT
= 3.0V V
PF
1.216 x V
BAT
1.25 x V
BAT
1.284 x V
BAT
V
DC ELECTRICAL CHARACTERISTICS
V
CC
= 0V, V
BAT
= 3.0V; T
A
= 0°C to +70°C, T
A
= -40°C to +85°C. Notes 1, 2
PARAMETER SYMBOL
CONDITIONS MIN
TYP MAX
UNITS V
BAT
Current OSC ON; SQWOUT OFF
I
BAT1
300 500
nA V
BAT
Current OSC ON; SQWOUT ON 32kHz
I
BAT2
480 800
nA V
BAT
Data-Retention Current Oscillator Off
I
BATDR
10 100
nA
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
3 of 14
AC ELECTRICAL CHARACTERISTICS
V
CC
= 4.5V to 5.5V; T
A
= 0°C to +70°C, T
A
= -40°C to +85°C.
PARAMETER SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
SCL Clock Frequency f
SCL
100 kHz
Bus Free Time Between a STOP and START Condition
t
BUF
4.7 µs
Hold Time Repeated START Condition
t
HD:STA
Note 4 4.0
µs LOW Period of SCL Clock
t
LOW
4.7 µs
HIGH Period of SCL Clock t
HIGH
4.0 µs
Setup Time for a Repeated START Condition
t
SU:STA
4.7 µs
Data Hold Time t
HD:DAT
µs Data Setup Time
t
SU:DAT
Notes 5, 6 250
ns Rise Time of Both SDA and SCL
Signals t
R
1000 ns
Fall Time of Both SDA and SCL Signals
t
F
300 ns
Setup Time for STOP Condition t
SU:STO
4.7 µs
CAPACITANCE
T
A
= +25°C
PARAMETER SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
Pin Capacitance SDA, SCL C
IO
10 pF
Capacitance Load for Each Bus Line
C
B
Note 7 400
pF
Note 1:
All voltages are referenced to ground.
Note 2:
Limits at -40°C are guaranteed by design and are not production tested.
Note 3:
I
CCS
specified with V
CC
= 5.0V and SDA, SCL = 5.0V.
Note 4:
After this period, the first clock pulse is generated.
Note 5:
A device must internally provide a hold time of at least 300ns for the SDA signal referred to the V
IHMIN
of the SCL signal to bridge the undefined region of the falling edge of SCL.
Note 6:
The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period t
LOW
of the SCL signal.
Note 7:
C
B
—total capacitance of one bus line in pF.
4 of 14
TIMING DIAGRAM
Figure 1. Block Diagram
RAM 56 X 8
SERIAL BUS INTERFACE
AND ADDRESS REGISTER
CONTROL LOGIC
1Hz 1Hz4.096kHz8.192kHz32.768kHz
MUX BUFFER
USER BUFFER 7 BYTES
CLOCK, CALENDAR,
AND CONTROL REGISTERS
POWER CONTROL
DS1307
X1
C
L
C
L
X2
SDA SCL
SQWOUT
V
CC
GND V
BAT
Oscillator and divider
N
START SDA
STOP SCL
t
SU:STO
t
HD:STA
t
SU:STA
REPEATED START
t
HD:DAT
t
HIGH
t
F
t
LOW
t
R
t
HD:STA
t
BUF
SU:DAT
5 of 14
TYPICAL OPERATING CHARACTERISTICS
V
CC
= 5.0V, T
A
= +25°C, unless otherwise noted.
I
CCS
vs. V
CC
10 20
30 40
50 60
70 80
90 100
110 120
1.0 2.0
3.0 4.0
5.0 V
CC
V S
UP P
LY CURRE
NT uA
V
BAT
=3.0V
I
BAT
vs. Temperature
175.0 225.0
275.0 325.0
-40 -20
20 40
60 80
TEMPERATURE °C S
UP P
LY CURRE
NT nA
V
CC
=0V, V
BAT
=3.0 SQW=32kHz
SQW off
I
BAT
vs. V
BAT
100 150
200 250
300 350
400
2.0 2.5
3.0 3.5
V
BACKUP
V S
UP P
LY CURRE
NT nA
SQW=32kHz
SQW off V
CC
= 0V
SQWOUT vs. Supply Voltage
32768 32768.1
32768.2 32768.3
32768.4 32768.5
2.0 2.5
3.0 3.5
4.0 4.5
5.0 5.5
Supply V F
RE Q
UE NCY
Hz
6 of 14
PIN DESCRIPTION
PIN NAME
FUNCTION
1 X1
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance C
L
of 12.5pF. X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz
oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is connected to X1.
Note:
For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
2 X2
3 V
BAT
Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation.
Diodes in series between the battery and the V
BAT
pin may prevent proper operation. If a backup supply is not required, V
BAT
must be grounded. The nominal power-fail trip point V
PF
voltage at which access to the RTC and user RAM is denied is set by the internal circuitry as 1.25 x V
BAT
nominal. A lithium battery with 48mAh or greater will back up the DS1307 for more than 10 years in the absence of power at +25°C.
UL recognized to ensure against reverse charging current when used with a lithium battery. Go to:
www.maxim-ic.comqainfoul .
4 GND
Ground 5
SDA Serial Data InputOutput. SDA is the data inputoutput for the I
2
C serial interface. The SDA pin is open drain and requires an external pullup resistor. The pullup voltage can be
up to 5.5V regardless of the voltage on V
CC
. 6
SCL Serial Clock Input. SCL is the clock input for the I
2
C interface and is used to synchronize data movement on the serial interface. The pullup voltage can be up to 5.5V regardless of
the voltage on V
CC
. 7
SQWOUT Square WaveOutput Driver. When enabled, the SQWE bit set to 1, the SQWOUT pin
outputs one of four square-wave frequencies 1Hz, 4kHz, 8kHz, 32kHz. The SQWOUT pin is open drain and requires an external pullup resistor. SQWOUT operates with either
V
CC
or V
BAT
applied. The pullup voltage can be up to 5.5V regardless of the voltage on V
CC
. If not used, this pin can be left floating. 8
V
CC
Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the
device and V
CC
is below V
TP
, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage.
DETAILED DESCRIPTION
The DS1307 is a low-power clockcalendar with 56 bytes of battery-backed SRAM. The clockcalendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including corrections for leap year. The DS1307 operates as a slave device on the I
2
C bus. Access is obtained by implementing a START condition and providing a device identification code followed by a register address. Subsequent registers can be accessed sequentially until a STOP condition is
executed. When V
CC
falls below 1.25 x V
BAT
, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being
written to the device from an out-of-tolerance system. When V
CC
falls below V
BAT
, the device switches into a low- current battery-backup mode. Upon power-up, the device switches from battery to V
CC
when V
CC
is greater than V
BAT
+0.2V and recognizes inputs when V
CC
is greater than 1.25 x V
BAT
. The block diagram in Figure 1 shows the
main elements of the serial RTC.
7 of 14
OSCILLATOR CIRCUIT
The DS1307 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a
functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional
error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application Note 58: Crystal Considerations with
Dallas Real-Time Clocks for detailed information.
Table 1. Crystal Specifications
PARAMETER SYMBOL
MIN TYP
MAX UNITS
Nominal Frequency f
O
32.768 kHz
Series Resistance ESR
45 kΩ
Load Capacitance C
L
12.5 pF
The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Figure 2. Recommended Layout for Crystal RTC AND RAM ADDRESS MAP
Table 2 shows the address map for the DS1307 RTC and RAM registers. The RTC registers are located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multibyte access,
when the address pointer reaches 3Fh, the end of RAM space, it wraps around to location 00h, the beginning of the clock space.
NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED
AREA UPPER LEFT QUADRANT OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE
DEVICE PACKAGE.
LOCAL GROUND PLANE LAYER 2
CRYSTAL X1
X2
GND
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CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the
time and calendar registers are in the BCD format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential i.e., if 1 equals Sunday, then 2 equals
Monday, and so on. Illogical time and date entries result in undefined operation. Bit 7 of Register 0 is the clock halt CH bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. On first
application of power to the device the time and date registers are typically reset to 010100 01 00:00:00 MMDDYY DOW HH:MM:SS. The CH bit in the seconds register will be set to a 1. The clock can be halted
whenever the timekeeping functions are not required, which minimizes current I
BATDR
. The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or
24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AMPM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit 20 to 23 hours. The hours value must be
re-entered whenever the 1224-hour mode bit is changed. When reading or writing the time and date registers, secondary user buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any I
2
C START. The time information is read from these secondary registers while the clock continues to run. This eliminates the need to re-read the registers in case the internal registers update during a
read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the I
2
C acknowledge from the DS1307. Once the divider chain is reset, to avoid rollover issues, the remaining time and
date registers must be written within one second.
Table 2. Timekeeper Registers
ADDRESS BIT 7
BIT 6 BIT 5
BIT 4 BIT 3
BIT 2 BIT 1
BIT 0 FUNCTION
RANGE
00h CH
10 Seconds Seconds
Seconds 00–59
01h 10 Minutes
Minutes Minutes
00–59 02h
12 10
Hour 10
Hour Hours
Hours 1–12
+AMPM 00–23
24 PM
AM 03h
DAY Day
01–07 04h
10 Date Date
Date 01–31
05h 10
Month Month
Month 01–12
06h 10 Year
Year Year
00–99 07h
OUT SQWE
RS1 RS0
Control —
08h–3Fh RAM
56 x 8 00h–FFh
0 = Always reads back as 0.
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CONTROL REGISTER
The DS1307 control register is used to control the operation of the SQWOUT pin.
BIT 7 BIT 6
BIT 5 BIT 4
BIT 3 BIT 2
BIT 1 BIT 0
OUT SQWE
RS1 RS0
Bit 7: Output Control OUT.
This bit controls the output level of the SQWOUT pin when the square-wave output is disabled. If SQWE = 0, the logic level on the SQWOUT pin is 1 if OUT = 1 and is 0 if OUT = 0. On initial
application of power to the device, this bit is typically set to a 0.
Bit 4: Square-Wave Enable SQWE.
This bit, when set to logic 1, enables the oscillator output. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. With the square-wave output set to 1Hz,
the clock registers update on the falling edge of the square wave. On initial application of power to the device, this bit is typically set to a 0.
Bits 1 and 0: Rate Select RS[1:0].
These bits control the frequency of the square-wave output when the square- wave output has been enabled. The following table lists the square-wave frequencies that can be selected with the
RS bits. On initial application of power to the device, these bits are typically set to a 1.
RS1 RS0
SQWOUT OUTPUT SQWE
OUT
1Hz 1
X 1
4.096kHz 1
X 1
8.192kHz 1
X 1
1 32.768kHz
1 X
X X
X X
1 1
10 of 14
I
2
C DATA BUS
The DS1307 supports the I
2
C protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock SCL, controls the bus access, and generates the START and STOP conditions. The DS1307
operates as a slave on the I
2
C bus. Figures 3, 4, and 5 detail how data is transferred on the I
2
C bus.
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy:
Both data and clock lines remain HIGH.
START data transfer:
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
STOP data transfer:
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
Data valid:
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of
data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the
I
2
C bus specifications a standard mode 100kHz clock rate and a fast mode 400kHz clock rate are defined. The DS1307 operates in the standard mode 100kHz only.
Acknowledge:
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
11 of 14
Figure 3. Data Transfer on I
2
C Serial Bus
Depending upon the state of the RW bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit MSB first.
2. Data transfer from a slave transmitter to a master receiver. The first byte the slave address is transmitted
by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the
end of the last received byte, a “not acknowledge” is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most
significant bit MSB first.
ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
R W
DIRECTION BIT
REPEATED IF MORE BYTES ARE TRANSFERED
START CONDITION
STOP CONDITION
OR REPEATED
START CONDITION
MSB
1 2
6 7
8 9
1 2
3-7 8
9 ACK
ACK SDA
SCL
12 of 14
... A
XXXXXXXX A
1101000
S XXXXXXXX A XXXXXXXX A
XXXXXXXX A P
Slave Address Word Address n Datan Datan+1 Datan+X
S - Start A - Acknowledge ACK
P - Stop R
W
DATA TRANSFERRED X+1 BYTES + ACKNOWLEDGE
Master to slave Slave to master
A XXXXXXXX
A
1101000
S 1
XXXXXXXX A XXXXXXXX XXXXXXXX A P
Slave Address Datan Datan+1 Datan+2 Datan+X S - Start
A - Acknowledge ACK P - Stop
A - Not Acknowledge NACK R
W
DATA TRANSFERRED X+1 BYTES + ACKNOWLEDGE; NOTE: LAST DATA BYTE IS
FOLLOWED BY A NOT ACKNOWLEDGE A SIGNAL Master to slave
Slave to master
... A
The DS1307 can operate in the following two modes:
1. Slave Receiver Mode Write Mode: Serial data and clock are received through SDA and SCL. After
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