Elektronika Dasar Field Effect Transistor

3.Field-Effect Transistor (FET)
Junction Field-Effect Transistor (JFET)
n-channel JFET

VGS = 0 V and VDS positive value

When VGS=0V and C some positive value,the upper region of the p-type material will be reverse biased higher than the
lower region(the greater the reverse bias,the wider the depletion region).
As the voltage VDS is increased from 0 to a few volts,the current will increase as determined by Ohm’s law and The
depletion region will widen,causing a noticeable reduction in channel widht.If V DS is increased to a level where it appears
that the two depletion regions would “touch”, a condition referred to as pinch-off will result.The level of V DS that
establishes this condition is referred to as pinch-off voltage Vp (when VGS=0V and VDS>Vp IDSS).
8
Input resistance
10 >Ω

VGS < 0V

Shockley’s Equation:

Voltage-Controlled Resistor:

where ro is the resistance with VGS _ 0 V and rd the resistance at a particular level of VGS.

Power dissipation:

p-channel JFET

PD = |VD|ID
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Or Insulated-Gate FET (IGFET)
Depletio-Type MOSFET (D-MOSFET) n-channel D-MOSFET

When VGS=0V,the drain current is IDSS.
The negative potential at the gate will tend to pressure electrons toward the p-type substrate and attract holes
from the p-type substrate.The drain current is therefore reduce with increasing negative bias for VGS.
The positive potential at the gate will draw additional electrons (free carrier) from the p-type substrate due to
the reverse leakage current,reveals that the drain current will increase.
10

Input resistance > 10 Ω

p-channel D-MOSFET

Enhachement-Type MOSFET (E-MOSFET)
n-channel E-MOSFET

If VGS = 0V,the absence of an n-channel will result in a
current of effectively zero amperes.

VD(ON)

VT

VGS(ON)

p-channel E-MOSFET

VGS

Complementary MOSFET (CMOS)
A very effective logic circuit can be established by contructing a p-channel and an n-channel MOSFET on the

same substrate.

FET Biasing
For de analysis,the coupling capacitors are open cicuits.
Fixed-Bias Configuration
Graphical Approach:

Self-Bias Configuration

Graphical Approach:

=-ID (1K

)

Voltage-Divinder Biasing

Graphical Approach:

Depletion-Type MOSFET

Graphical Approach:

Enhancement-Type MOSFET

Graphical Approach:

V GS =V DS =V DD −I D R D=12 V −I D (2K Ω)
I D=0→V GS =12V
V GS =0→ I D =6 mA
I DQ =2.75 mA
V GS =V DS =6. 4V
Q

p-channel FET

Graphical Approach:

→V GS=V G +I D R S =−4 . 55 V +I D (1 .8 K Ω)
I D=0 →V GS =−4 . 55 V
V GS =0 →I D=2 .53 mA

FET Small-Signal Model

I D=I DSS

(

gm= y fs=

V GS
1−
VP

2

)

ΔI D

2I

V
V
|V DS =const= DSS 1− GS =g mo 1− GS
ΔV GS
|V P|
VP
VP

(

At VGS Q =- 0.5V ® g m =

) (

)

DI D
2 mA
=
=3.3mS

DVGS 0.6V

DI D
1.8mA
=
= 2 .4 mS
DVGS 0 .75V
DI
1.5mA
=- 2.5V ® g m = D =
=1.4 mS
DVGS
1.1V

At VGS Q =- 1.5V ® g m =
AtVGS Q

D

ID

ID

VGS

FET ac equivalent model:
Output resistance:

rd=

Input Impedance of the FET:

Z i ( FET )=∞
(the typical values: JFET

9

12

15

¿ 10 Ω, MOSFET ≃10 −10 Ω)

Output impedance of the FET:

Z o ( FET )=r d =

1
y os

ΔV Ds
ΔI D

=

7V
=14 k Ω
0 . 5 mA

FET Small-Signal Analysis

Common-Source Circuit

+VDD

FET ac equivalent model:
Output resistance:

+VDD

Vi = 0

Zo = RD ||rd

RD
C2
R1
C1

R2

Rs

Cs

Z i =R1||R2
V o =−( gm V gs )( R D||r d )=−( gm V i )( R D||r d )→ A v=

Vo
Vi

=−g m( R D||r d )

+VDD

RD

rd=∞
s
RG

V gs=V i−gmV gs Ralignl ¿ ¿¿

Rs

V gR
¿→V i=V gs(1+gm Rs )¿V o=−(gm V gs)RD ¿Av= o =− m D ¿¿
V i 1+gm Rs

r d ≠∞
D
Vi

Vo
Vo - Vs
rd

Io

V gs=V i −I o Rs
V −V s
−I R −I R
I o =gm V gs + o
=g m V gs+ o D o s
rd
rd
−I R −I R
¿ g m(V i −I o Rs )+ o D o s
rd
gm V i
→I o =
( R D + R s)
1+ g m Rs +
rd
g R V
V o =−I o R D =− m D i
( R +R )
1+ gm Rs + D s
rd
Vo
gm R D
→ A v = =−
Vi
( R D + Rs )
1+ gm R s +
rd

Common-Drain (Source-Follower) Circuit

V o =gm V gs ( R S||r d )=gm ( V i−V o )( R S ||r d )→ A v=

Vo
g ( R ||r )
= m S d
V i 2+ g ( R S||r d )
m

G

S

Z i =RG
1
V i=0→Z o =R S||r d||
gm
Common-Gate Circuit

V o =−( gm V gs ) R D=−gm (−V i ) R D → A V =

1
Z i =RS ||
gm
V i=0→Z o =R D||r d

Enhancemen MOSFET Amplifier

Vo
Vi

=gm R D

k=

I D (ON )
(VGS ( ON ) - VTh ) 2

2

(typically 0.3 mA/V )

V i −V o
−g m V i )(R D||r d )
RG
Vo (1−gm R G )( R D||r d )
→ AV= =
Vi RG +R D||r d
V o =( I 1−g m V gs )(R D||r d )=(

gm R G >> 1)
RG >> R D or r d
(for

g m RG ( R D||r d )
=−g m ( RG||R D||r d )
R G+ RD||r d
¿−g m (R D||r d )
¿−

V i (1−

Vo
)
Vi

V i −V o
V R
R
R
=
→ Zi = i = G
= G
= G
RG
RG
I i 1− AV 1−(−g m (R D||r d )) 1+g m (R D||r d ))
V i=0→R D||r d||RG ≃R D||r d
Ii =

System Approach-Effects of RS and RL

(for

Bypassed Source Resistance

AV =

Unbypassed Source Resistance

Source Follower

Vo
= - g m ( R L || R D )
Vi

Common Gate

V
AV = o =gm(RL || RD )
Vi