S04 Silicon Nanotechnology 100%
Silicon Nanotechnology
Ken David
Director, Components Research
Technology & Manufacturing Group
Intel Corp.
February 18, 2004
1
Agenda
What is Nanotechnology?
Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or
its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004, Intel Corporation
2
Agenda
What is Silicon Nanotechnology?
CMOS Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
3
Nanotechnology Definition
“Research and technology development at the
atomic, molecular or macromolecular levels,
in the length scale of approximately
1 - 100 nanometer range.”
Dr. Mike Roco, National Science and Technology
Council, February 2000
Intel started sub-100nm production in Q3’00
4
Technology Scaling
10000
10
Nominal feature size
1000
1
Micron
Gate Length
130nm
90nm
100
0.1
Nanotechnology
70nm
50nm
10
0.01
1970
Nanometer
1980
1990
2000
5
2010
2020
Nanotechnology Today
Example of today’s technology: 50 nm transistor dimension
50nm
100nm
Transistor for
90nm-node
Influenza virus
Gate oxide=1.2nm
Source: CDC
Source: Intel
Intel 2003 Silicon Nanotech Product
Revenue >$20B
6
Scaling => Nanoscaling
Nearly 7 Orders Of Magnitude Reduction in Cost/Transistor
10
1
0.1
0.01
$
0.001
0.0001
0.00001
0.000001
Nanodollars per transistor !
0.0000001
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
Source: WSTS/Dataquest/Intel, 8/02
7
Silicon Nanotechnology Evolution
y Continued CMOS Nanoscaling
-materials, lithography innovation
y Implement Non-classical CMOS
- new architectures, new structures
y Transition to Novel devices
-alternative state variables
-must meet device requirements
and demonstrate integrability
8
Agenda
What is Silicon Nanotechnology?
CMOS Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
9
CMOS Nanoscaling….Extending
Moore’s Law
Gordon
Typical
engineer.
Source: Dr. Grant Wilson
NNI Nanotechnology Workshop
November,, 2003
10
New Materials, Devices Extend Si
Scaling
Changes
Made
Future
Options
Gate
High-k
gate
dielectric
Silicide
added
PolySi
Channel
Strained
silicon
Silicon
Transistor
Source: Intel
11
Gate dielectric
less than
3 atomic layers
thick
Source:
Intel
New Materials, Devices Extend Si
Scaling
Changes
Made
Future
Options
Metal lines
New
New
Thinner
Thinner
Barrier
Barrier
Layers
Layers
Al
Cu
Ultra
Low-k
Dielectric
Insulating
dielectric
SiO2
SiOF
CDO
(low-k)
Interconnects
Source: Intel
12
EUV LLC Consortium Demonstrates
EUVL with Prototype Exposure Tool
Source: Sandia
13
EUV Lithography - Full Field ETS Images
(using 0.1 NA system)
100 nm Elbows 1:1
80 nm Elbows 1:1
200 mm Wafer
100 nm contacts 1:1
4x5 matrix
24 x 32.5 mm2 field
Printing 80 nm images at 0.1 NA is equivalent
to printing 32 nm with 0.25 NA production system
14
152 mm2, 4X
Reflective Mask
Strained Silicon Transistors
Current Flow
Normal
electron
flow
Faster
electron
flow
Normal Silicon Lattice
Strained Silicon Lattice
Source: Intel
15
Strained Silicon Transistors
Strained silicon benefits
• Strained silicon lattice increases electron and hole mobility
in transistor channels
• Greater mobility results in 10-20% increase in transistor
current flow (drive current)
• Increased drive current = increased transistor performance
• Both NMOS and PMOS transistor performance improved
Strained silicon process
• Intel's strained silicon process is unique in the industry
• No detriments to transistor short channel behavior or
junction leakage
• The added process steps increase total processing cost by
only ~2%
16
Transistor Strain Techniques
Traditional Approach
Intel's 90nm Technology
S
G
G
G
D
D
S
Graded SiGe Layer
Selective SiGe S-D
Biaxial
Tensile Strain
Uniaxial
Compressive Strain
for PMOS
17
S
D
Tensile Si3N4 Cap
Uniaxial
Tensile Strain
for NMOS
High-K Gate Dielectric
Gate
Gate
1.2nm SiO2
3.0nm High-k
Silicon substrate
Silicon substrate
90nm process
High-k
Capacitance:
1.0x
1.6x
Leakage:
1.0x
< 0.01x
Source: Intel
18
High-K Gate Dielectric Formed Using
Atomic Layer Chemical Vapor
Deposition
Introduce reactant 2
Reactant 1
Step 1
Step 3
Final film
Step 4
Step 2
• “Self-assembly process” ready for manufacturing
• Sequential introduction of precursors molecules
• Allows for precise building of the dielectric film
Source: Intel
19
1.E-02
1.E-03
1.E-04
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
Vd=1.3V
1E-03
Vd=0.05V
1E-04
Ion
= 1.5 mA/µm
Ion = 1.5mA/µm
Ioff== 43
43 nA/µm
Ioff
nA/µm
Id (A/µm)
Id (A/µm)
High-K/Metal-Gate Achieved
Recording-Setting Performance
Lg = 80nm
1E-05
1E-06
1E-07
Vd=1.3V
Vd=0.05V
Ion = 693 µA/µm
Ioff = 25 nA/µm
1E-08
Toxe = 14.5A
1E-09
1E-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vg (V)
Vg (V)
NMOS Transistor
PMOS Transistor
Source: Intel
20
Continuation of Moore’s Law
Process Name
P856
P858
Px60
P1262
P1264
P1266
P1268
P1270
1st Production
1997
1999
2001
2003
2005
2007
2009
2011
0.25µm
0.18µm
0.13µm
90 nm
65 nm
45 nm
32 nm
22 nm
200
200
200/300
300
300
300
300
300
Inter-connect
Al
Al
Cu
Cu
Cu
Cu
Cu
?
Channel
Si
Si
Si
Strained
Si
Strained
Si
Gate dielectric
SiO2
SiO2
SiO2
SiO2
SiO2
High-k
High-k
High-k
Gate electrode
Polysilicon
Polysilicon
Polysilicon
Polysilicon
Polysilicon
Metal
Metal
Metal
Process
Generation
Wafer Size (mm)
Strained
Strained
Strained Si
Si
Si
Source: Intel
Introduction targeted at this time
Subject to change
-k and
Intel
Intelfound
foundaasolution
solutionfor
forHigh
High-k
andmetal
metalgate
gate
21
Agenda
What is Silicon Nanotechnology?
Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
22
Transistor Architectures
Lg
Source
Gate
Drain
Si
TSi
Si
Drain
Isolation
(Planar)
Gate 3
TSi
Lg
Gate 1
Source
WSi
Lg
Gate 1
Source
WSi
TSi
Gate 2
Double-gate (e.g. FINFET)
(Non-Planar)
Source: Intel
23
Drain
Tri-gate
(NonPlanar)
Gate 2
Tri-Gate Transistor
Top Gate
Actual photo
30nm tri-gate transistor
Side Gate
Source
Drain
Side Gate
Simulation
Cross-section of
silicon channel
shows much more
current flow
(indicated by red)
in tri-gate transistor
than in planar
transistor
Tri-Gate
Tri-Gate
Conventional
Planar
Planar
Source: Intel
24
World Record Non-Planar Performance
Very high drive current at saturation, 1.23 mA/µm
Very low
leakage,
40nA/µm
Drain current (amps/µm)
1E-02
1E-03
Drain voltage=1.3V
1E-04
Drain voltage=0.05V
1E-05
1E-06
1E-07
1E-08
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Gate voltage (Volts)
Tri
-gate transistor exhibits excellent device
Tri-gate
characteristics
Source: Intel
25
Non-Classical CMOS
y Many options including nanotubes/nanowires
y Collaborations with universities in progress
Silicon Nanowire
Carbon Nanotube
Source: Morales & Lieber, Science 279, 208 (1998)
26
CMOS Device Scaling Demonstration
90nm Node
2003
65nm Node
2005
45nm Node
2007
32nm Node
2009
50nm Length
(IEDM2002)
30nm
Prototype
(IEDM2000)
20nm Prototype
(VLSI2001)
22nm Node
2011
Si
16 nm node
na
25 nm
no
2013
wi
11nm node
15nm
res
??
2015
8 nm node
2017
15nm Prototype
(IEDM2001)
10nm Prototype
(DRC 2003)
Integration of nanotubes
nanotubes,, nanowires onto
Si by end of this decade will extend device
scaling well into next decade
TBD
Source: Intel; Morales and Lieber
Science,
279, 208, 1998
27
TBD
Agenda
What is silicon Nanotechnology?
Nano Scaling
Non classical CMOS
Novel Devices
Summary
28
Novel Devices
y Many device options….
y Compatibility with CMOS for evolutionary
introduction
y Directed or self assembly of arrays???
– Defect density or purity required….
y Self correcting architectures??
• Nanotechnology needs a richer suite of
functionality…
Collaboration between
industry, universities, and
government is essential
29
Novel Devices
What are we looking for?
y Required characteristics:
–
–
–
–
–
–
Alternative state variables
y Spin–electron, nuclear,
photon
y Phase
y Quantum state
y Magnetic flux quanta
y Mechanical deformation
y Dipole orientation
y Molecular state
Scalability
Performance
Energy efficiency
Gain
Operational reliability
Room temp. operation
y Preferred approach:
– CMOS process
compatibility
– CMOS architectural
compatibility
30
Intel Involved in University Research
Intel-supported Nanotechnology Research at Universities
Colorado
Illinois
Ohio
Ireland
New York
Oregon
Mass
California
Israel
Tennessee
Arizona
Texas
Florida
Intel engaged
in >300 SRC*
projects at
50 universities
31
*Semiconductor Research Corp
Agenda
What is Silicon Nanotechnology?
Nano Scaling
Non classical CMOS
Novel Devices
Summary
32
Summary
y Nanotechnology is here today in “state of the art” high speed Si
CMOS process technologies
y Si nanotechnology process scaling/convergence will continue
indefinitely.
y New architectures will further extend silicon scaling.
y Novel technologies being investigated and may be integrated with
silicon technology mid-next decade
y Compatability with CMOS (product development spectrum) will
leverage existing learning and enable earlier production of novel
devices
33
34
Thank You!
Please fill out the Session
Evaluation Form.
Ken David
Director, Components Research
Technology & Manufacturing Group
Intel Corp.
February 18, 2004
1
Agenda
What is Nanotechnology?
Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or
its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004, Intel Corporation
2
Agenda
What is Silicon Nanotechnology?
CMOS Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
3
Nanotechnology Definition
“Research and technology development at the
atomic, molecular or macromolecular levels,
in the length scale of approximately
1 - 100 nanometer range.”
Dr. Mike Roco, National Science and Technology
Council, February 2000
Intel started sub-100nm production in Q3’00
4
Technology Scaling
10000
10
Nominal feature size
1000
1
Micron
Gate Length
130nm
90nm
100
0.1
Nanotechnology
70nm
50nm
10
0.01
1970
Nanometer
1980
1990
2000
5
2010
2020
Nanotechnology Today
Example of today’s technology: 50 nm transistor dimension
50nm
100nm
Transistor for
90nm-node
Influenza virus
Gate oxide=1.2nm
Source: CDC
Source: Intel
Intel 2003 Silicon Nanotech Product
Revenue >$20B
6
Scaling => Nanoscaling
Nearly 7 Orders Of Magnitude Reduction in Cost/Transistor
10
1
0.1
0.01
$
0.001
0.0001
0.00001
0.000001
Nanodollars per transistor !
0.0000001
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
Source: WSTS/Dataquest/Intel, 8/02
7
Silicon Nanotechnology Evolution
y Continued CMOS Nanoscaling
-materials, lithography innovation
y Implement Non-classical CMOS
- new architectures, new structures
y Transition to Novel devices
-alternative state variables
-must meet device requirements
and demonstrate integrability
8
Agenda
What is Silicon Nanotechnology?
CMOS Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
9
CMOS Nanoscaling….Extending
Moore’s Law
Gordon
Typical
engineer.
Source: Dr. Grant Wilson
NNI Nanotechnology Workshop
November,, 2003
10
New Materials, Devices Extend Si
Scaling
Changes
Made
Future
Options
Gate
High-k
gate
dielectric
Silicide
added
PolySi
Channel
Strained
silicon
Silicon
Transistor
Source: Intel
11
Gate dielectric
less than
3 atomic layers
thick
Source:
Intel
New Materials, Devices Extend Si
Scaling
Changes
Made
Future
Options
Metal lines
New
New
Thinner
Thinner
Barrier
Barrier
Layers
Layers
Al
Cu
Ultra
Low-k
Dielectric
Insulating
dielectric
SiO2
SiOF
CDO
(low-k)
Interconnects
Source: Intel
12
EUV LLC Consortium Demonstrates
EUVL with Prototype Exposure Tool
Source: Sandia
13
EUV Lithography - Full Field ETS Images
(using 0.1 NA system)
100 nm Elbows 1:1
80 nm Elbows 1:1
200 mm Wafer
100 nm contacts 1:1
4x5 matrix
24 x 32.5 mm2 field
Printing 80 nm images at 0.1 NA is equivalent
to printing 32 nm with 0.25 NA production system
14
152 mm2, 4X
Reflective Mask
Strained Silicon Transistors
Current Flow
Normal
electron
flow
Faster
electron
flow
Normal Silicon Lattice
Strained Silicon Lattice
Source: Intel
15
Strained Silicon Transistors
Strained silicon benefits
• Strained silicon lattice increases electron and hole mobility
in transistor channels
• Greater mobility results in 10-20% increase in transistor
current flow (drive current)
• Increased drive current = increased transistor performance
• Both NMOS and PMOS transistor performance improved
Strained silicon process
• Intel's strained silicon process is unique in the industry
• No detriments to transistor short channel behavior or
junction leakage
• The added process steps increase total processing cost by
only ~2%
16
Transistor Strain Techniques
Traditional Approach
Intel's 90nm Technology
S
G
G
G
D
D
S
Graded SiGe Layer
Selective SiGe S-D
Biaxial
Tensile Strain
Uniaxial
Compressive Strain
for PMOS
17
S
D
Tensile Si3N4 Cap
Uniaxial
Tensile Strain
for NMOS
High-K Gate Dielectric
Gate
Gate
1.2nm SiO2
3.0nm High-k
Silicon substrate
Silicon substrate
90nm process
High-k
Capacitance:
1.0x
1.6x
Leakage:
1.0x
< 0.01x
Source: Intel
18
High-K Gate Dielectric Formed Using
Atomic Layer Chemical Vapor
Deposition
Introduce reactant 2
Reactant 1
Step 1
Step 3
Final film
Step 4
Step 2
• “Self-assembly process” ready for manufacturing
• Sequential introduction of precursors molecules
• Allows for precise building of the dielectric film
Source: Intel
19
1.E-02
1.E-03
1.E-04
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
Vd=1.3V
1E-03
Vd=0.05V
1E-04
Ion
= 1.5 mA/µm
Ion = 1.5mA/µm
Ioff== 43
43 nA/µm
Ioff
nA/µm
Id (A/µm)
Id (A/µm)
High-K/Metal-Gate Achieved
Recording-Setting Performance
Lg = 80nm
1E-05
1E-06
1E-07
Vd=1.3V
Vd=0.05V
Ion = 693 µA/µm
Ioff = 25 nA/µm
1E-08
Toxe = 14.5A
1E-09
1E-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vg (V)
Vg (V)
NMOS Transistor
PMOS Transistor
Source: Intel
20
Continuation of Moore’s Law
Process Name
P856
P858
Px60
P1262
P1264
P1266
P1268
P1270
1st Production
1997
1999
2001
2003
2005
2007
2009
2011
0.25µm
0.18µm
0.13µm
90 nm
65 nm
45 nm
32 nm
22 nm
200
200
200/300
300
300
300
300
300
Inter-connect
Al
Al
Cu
Cu
Cu
Cu
Cu
?
Channel
Si
Si
Si
Strained
Si
Strained
Si
Gate dielectric
SiO2
SiO2
SiO2
SiO2
SiO2
High-k
High-k
High-k
Gate electrode
Polysilicon
Polysilicon
Polysilicon
Polysilicon
Polysilicon
Metal
Metal
Metal
Process
Generation
Wafer Size (mm)
Strained
Strained
Strained Si
Si
Si
Source: Intel
Introduction targeted at this time
Subject to change
-k and
Intel
Intelfound
foundaasolution
solutionfor
forHigh
High-k
andmetal
metalgate
gate
21
Agenda
What is Silicon Nanotechnology?
Nanoscaling
Nonclassical CMOS
Novel Devices
Summary
22
Transistor Architectures
Lg
Source
Gate
Drain
Si
TSi
Si
Drain
Isolation
(Planar)
Gate 3
TSi
Lg
Gate 1
Source
WSi
Lg
Gate 1
Source
WSi
TSi
Gate 2
Double-gate (e.g. FINFET)
(Non-Planar)
Source: Intel
23
Drain
Tri-gate
(NonPlanar)
Gate 2
Tri-Gate Transistor
Top Gate
Actual photo
30nm tri-gate transistor
Side Gate
Source
Drain
Side Gate
Simulation
Cross-section of
silicon channel
shows much more
current flow
(indicated by red)
in tri-gate transistor
than in planar
transistor
Tri-Gate
Tri-Gate
Conventional
Planar
Planar
Source: Intel
24
World Record Non-Planar Performance
Very high drive current at saturation, 1.23 mA/µm
Very low
leakage,
40nA/µm
Drain current (amps/µm)
1E-02
1E-03
Drain voltage=1.3V
1E-04
Drain voltage=0.05V
1E-05
1E-06
1E-07
1E-08
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Gate voltage (Volts)
Tri
-gate transistor exhibits excellent device
Tri-gate
characteristics
Source: Intel
25
Non-Classical CMOS
y Many options including nanotubes/nanowires
y Collaborations with universities in progress
Silicon Nanowire
Carbon Nanotube
Source: Morales & Lieber, Science 279, 208 (1998)
26
CMOS Device Scaling Demonstration
90nm Node
2003
65nm Node
2005
45nm Node
2007
32nm Node
2009
50nm Length
(IEDM2002)
30nm
Prototype
(IEDM2000)
20nm Prototype
(VLSI2001)
22nm Node
2011
Si
16 nm node
na
25 nm
no
2013
wi
11nm node
15nm
res
??
2015
8 nm node
2017
15nm Prototype
(IEDM2001)
10nm Prototype
(DRC 2003)
Integration of nanotubes
nanotubes,, nanowires onto
Si by end of this decade will extend device
scaling well into next decade
TBD
Source: Intel; Morales and Lieber
Science,
279, 208, 1998
27
TBD
Agenda
What is silicon Nanotechnology?
Nano Scaling
Non classical CMOS
Novel Devices
Summary
28
Novel Devices
y Many device options….
y Compatibility with CMOS for evolutionary
introduction
y Directed or self assembly of arrays???
– Defect density or purity required….
y Self correcting architectures??
• Nanotechnology needs a richer suite of
functionality…
Collaboration between
industry, universities, and
government is essential
29
Novel Devices
What are we looking for?
y Required characteristics:
–
–
–
–
–
–
Alternative state variables
y Spin–electron, nuclear,
photon
y Phase
y Quantum state
y Magnetic flux quanta
y Mechanical deformation
y Dipole orientation
y Molecular state
Scalability
Performance
Energy efficiency
Gain
Operational reliability
Room temp. operation
y Preferred approach:
– CMOS process
compatibility
– CMOS architectural
compatibility
30
Intel Involved in University Research
Intel-supported Nanotechnology Research at Universities
Colorado
Illinois
Ohio
Ireland
New York
Oregon
Mass
California
Israel
Tennessee
Arizona
Texas
Florida
Intel engaged
in >300 SRC*
projects at
50 universities
31
*Semiconductor Research Corp
Agenda
What is Silicon Nanotechnology?
Nano Scaling
Non classical CMOS
Novel Devices
Summary
32
Summary
y Nanotechnology is here today in “state of the art” high speed Si
CMOS process technologies
y Si nanotechnology process scaling/convergence will continue
indefinitely.
y New architectures will further extend silicon scaling.
y Novel technologies being investigated and may be integrated with
silicon technology mid-next decade
y Compatability with CMOS (product development spectrum) will
leverage existing learning and enable earlier production of novel
devices
33
34
Thank You!
Please fill out the Session
Evaluation Form.