Foto 2 : Bagian Depan dari Alat

  

Foto 1 : Bagian Atas dari Alat

Foto 2 : Bagian Depan dari Alat

  

Foto 3 : Bagian Dalam dari Alat

MCUV. ASM

  ; - - Di s p l a y Po r t & RAMs - - ; Di s Da t EQU P1 PS1 BI T P3 . 0 PS2 BI T P3 . 1 PS3 BI T P3 . 2 PS4 BI T P3 . 3 d g 1 EQU 0 8 h d g 2 EQU 0 9 h d g 3 EQU 0 Ah d g 4 EQU 0 Bh APa r 2 EQU 0 Ch APa r 1 EQU 0 Dh SPa r 2 EQU 0 Eh SPa r 1 EQU 0 Fh MPa r 2 EQU 1 0 h MPa r 1 EQU 1 1 h DPa r 2 EQU 1 2 h DPa r 1 EQU 1 3 h RBa k 2 EQU 1 4 h RBa k 1 EQU 1 5 h J 1 _ 2 EQU 1 6 h J 1 _ 1 EQU 1 7 h J 2 _ 2 EQU 1 8 h J 2 _ 1 EQU 1 9 h p 5 0 ms EQU 2 0 h FLAG EQU 2 1 h Sd h 5 BI T FLAG. 0 ; - - Ot h e r s Po r t & RAMs - - ; SOu t BI T P3 . 4 SI n BI T P3 . 5 Bu t t o n BI T P3 . 7 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - o r g 0 0 h j mp mu l a i o r g 0 Bh j mp T0 _ Ve c t ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - mu l a i : ; - - I n i s i a l i s a s i Va r & Po r t mo v SP, # 2 2 h mo v Di s Da t , # 0 FFh s e t b PS1 s e t b PS2 s e t b PS3 s e t b PS4 s e t b SOu t s e t b SI n mo v d g 4 , # 1 0 h mo v d g 3 , # 1 0 h mo v d g 2 , # 1 0 h mo v d g 1 , # 1 0 h ; - - I n i s i a l i s a s i Ti me r mo v TMOD, # 5 1 h c l r TR1 c l r TR0 c l r ET1 c l r ET0 u l a n g :

  Pa g e 1

MCUV. ASM

  ; - - - Te mb a k a n Pe r t a ma mo v TH0 , # 0 0 h mo v TL0 , # 0 0 h mo v TH1 , # 0 0 h mo v TL1 , # 0 0 h c l r TF0 s e t b TR1 s e t b TR0 mo v b , # 4 0 a mb i l _ f r e k : c p l SOu t n o p n o p n o p n o p n o p n o p n o p n o p n o p d j n z b , a mb i l _ f r e k ; - - - t u n g g u : mo v a , TL1 j n z d a p a t j n b TF0 , t u n g g u c l r TR1 c l r TR0 j mp u l a n g d a p a t : c l r TR0 c l r TR1 ; - - - Si mp a n J a r a k - 1 mo v J 1 _ 2 , TH0 mo v J 1 _ 1 , TL0 ; - - - Tu n g g u 5 0 0 ms c l r Sd h 5 mo v TH0 , # 0 3 Ch mo v TL0 , # 0 B0 h mo v p 5 0 ms , # 1 0 s e t b TR0 s e t b ET0 s e t b EA d l y 5 0 0 ms : c a l l s h o w7 s j n b Sd h 5 , d l y 5 0 0 ms ; mo v R0 , # 1 0 ; 1 ( R0 = x ) ; d l y 5 0 0 ms _ 1 : ; mo v R1 , # 1 0 0 ; x ( R1 = y ) ; d l y 5 0 0 ms _ 2 : ; mo v R2 , # 2 4 5 ; y * x ( R2 = z ) ; d j n z R2 , $ ; 2 * z * y * x ; d j n z R1 , d l y 5 0 0 ms _ 2 ; 2 * y * x ; d j n z R0 , d l y 5 0 0 ms _ 1 ; 2 * x ; - - - Te mb a k a n Ke d u a mo v TH0 , # 0 0 h mo v TL0 , # 0 0 h mo v TH1 , # 0 0 h mo v TL1 , # 0 0 h c l r TF0 s e t b TR1 s e t b TR0

  Pa g e 2 MCUV. ASM mo v b , # 4 0 a mb i l _ f r e k 2 : c p l SOu t n o p n o p n o p n o p n o p n o p n o p n o p n o p d j n z b , a mb i l _ f r e k 2 ; - - - t u n g g u 2 : mo v a , TL1 j n z d a p a t 2 j n b TF0 , t u n g g u 2 c l r TR1 c l r TR0 j mp u l a n g d a p a t 2 : c l r TR0 c l r TR1 ; - - - Hi t u n g J a r a k - 2 mo v d p h , TH0 mo v d p l , TL0 mo v DPa r 2 , # 0 mo v DPa r 1 , # 1 2 5 c a l l d i v _ i n t mo v MPa r 2 , # 0 mo v MPa r 1 , # 2 c a l l mu l _ i n t mo v J 2 _ 2 , d p h mo v J 2 _ 1 , d p l ; - - - Hi t u n g J a r a k - 1 mo v d p h , J 1 _ 2 mo v d p l , J 1 _ 1 mo v DPa r 2 , # 0 mo v DPa r 1 , # 1 2 5 c a l l d i v _ i n t mo v MPa r 2 , # 0 mo v MPa r 1 , # 2 c a l l mu l _ i n t mo v J 1 _ 2 , d p h mo v J 1 _ 1 , d p l ; - - Ce k Ma n a Ya n g Be s a r mo v a , J 2 _ 2 c l r c s u b b a , J 1 _ 2 j c J 2 _ Le b i h _ Ke c i l j n z J 2 _ Le b i h _ Be s a r mo v a , J 2 _ 1 c l r c s u b b a , J 1 _ 1 j c J 2 _ Le b i h _ Ke c i l j n z J 2 _ Le b i h _ Be s a r ; - - J a r a k Sa ma , V = c m/ s

  Pa g e 3 MCUV. ASM mo v d g 4 , # 0 mo v d g 3 , # 0 mo v d g 2 , # 0 mo v d g 1 , # 0 j mp u l a n g J 2 _ Le b i h _ Ke c i l : mo v d p h , J 1 _ 2 mo v d p l , J 1 _ 1 mo v SPa r 2 , J 2 _ 2 mo v SPa r 1 , J 2 _ 1 c a l l s u b b _ i n t j mp Ub a h _ Ke De s i ma l J 2 _ Le b i h _ Be s a r : mo v d p h , J 2 _ 2 mo v d p l , J 2 _ 1 mo v SPa r 2 , J 1 _ 2 mo v SPa r 1 , J 1 _ 1 c a l l s u b b _ i n t Ub a h _ Ke De s i ma l : ; - - Ka l i 2 Du l u mo v MPa r 2 , # 0 mo v MPa r 1 , # 2 c a l l mu l _ i n t ; - - Ya n g a k a n d i t a mp i l k a n mo v RBa k 2 , d p h ; Rb - Rs - Pl - St mo v RBa k 1 , d p l ; Amb i l Ri b u a n mo v DPa r 2 , # 0 0 3 h mo v DPa r 1 , # 0 E8 h c a l l d i v _ i n t ; Rb - Rs - Pl - St / 1 0 0 0 = Rb mo v d g 4 , d p l ; Ge t <Rb > ; Amb i l r a t u s a n mo v MPa r 2 , # 0 0 3 h mo v MPa r 1 , # 0 E8 h c a l l mu l _ i n t ; Rb * 1 0 0 0 mo v SPa r 2 , d p h mo v SPa r 1 , d p l mo v d p h , RBa k 2 mo v d p l , RBa k 1 c a l l s u b b _ i n t ; Rb - Rs - Pl - St - Rb * 1 0 0 0 = Rs - Pl - St mo v RBa k 2 , d p h ; Rs - Pl - St mo v RBa k 1 , d p l mo v DPa r 2 , # 0 mo v DPa r 1 , # 1 0 0 c a l l d i v _ i n t ; Rs - Pl - St / 1 0 0 = Rs mo v d g 3 , d p l ; Ge t <Rs > ; Amb i l Pu l u h a n mo v MPa r 2 , # 0 mo v MPa r 1 , # 1 0 0 c a l l mu l _ i n t ; Rs * 1 0 0 mo v SPa r 2 , d p h mo v SPa r 1 , d p l mo v d p h , RBa k 2 mo v d p l , RBa k 1 c a l l s u b b _ i n t ; Rs - Pl - St - Rs * 1 0 0 = Pl - St mo v RBa k 2 , d p h ; Pl - St mo v RBa k 1 , d p l

  Pa g e 4 MCUV. ASM mo v DPa r 2 , # 0 mo v DPa r 1 , # 1 0 c a l l d i v _ i n t ; Pl - St / 1 0 = Pl mo v d g 2 , d p l ; Ge t <Pl > ; Amb i l Sa t u a n mo v MPa r 2 , # 0 mo v MPa r 1 , # 1 0 c a l l mu l _ i n t ; Pl * 1 0 mo v SPa r 2 , d p h mo v SPa r 1 , d p l mo v d p h , RBa k 2 mo v d p l , RBa k 1 c a l l s u b b _ i n t ; Pl - St - Pl * 1 0 = St mo v d g 1 , d p l ; Ge t <St > j mp u l a n g ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T0 _ Ve c t : p u s h p s w c l r TR0 mo v TH0 , # 0 3 Ch mo v TL0 , # 0 B0 h s e t b TR0 d j n z p 5 0 ms , T0 _ Ve c t _ En d c l r TR0 c l r ET0 c l r EA s e t b Sd h 5 T0 _ Ve c t _ En d : p o p p s w r e t i ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - d l y _ k e y : ; - - De l a y Sa mp a i To mb o l Di l e p a s p u s h 0 h p u s h 1 h d k _ u l a n g : mo v R0 , # 2 0 0 d l y _ k e y _ : c a l l s h o w7 s d j n z R0 , d l y _ k e y _ j n b Bu t t o n , d k _ u l a n g p o p 1 h p o p 0 h r e t ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s h o w7 s : ; - - Ta mp i l k a n An g k a Ke Di s p l a y p u s h a c c p u s h 0 h mo v d p t r , # d b 7 s ; - - Sh o w Di g i t - 4 mo v a , d g 4 mo v c a , @a +d p t r mo v Di s Da t , a c l r PS4 c a l l d l y 7 s s e t b PS4 ; - - Sh o w Di g i t - 3

  Pa g e 5 MCUV. ASM mo v a , d g 3 mo v c a , @a +d p t r mo v Di s Da t , a c l r PS3 c a l l d l y 7 s s e t b PS3 ; - - Sh o w Di g i t - 2 mo v a , d g 2 mo v c a , @a +d p t r mo v Di s Da t , a c l r PS2 c a l l d l y 7 s s e t b PS2 ; - - Sh o w Di g i t - 1 mo v a , d g 1 mo v c a , @a +d p t r mo v Di s Da t , a c l r PS1 c a l l d l y 7 s s e t b PS1 p o p 0 h p o p a c c r e t d l y 7 s : ; - - De l a y Ta h a n mo v R0 , # 1 0 0 d j n z R0 , $ r e t d b 7 s : ; - - Da t a Ba s e Ko mb i n a s i Se g me n ; - g f e d c b a d b 1 1 0 0 0 0 0 0 b ; 0 d b 1 1 1 1 1 0 0 1 b ; 1 d b 1 0 1 0 0 1 0 0 b ; 2 d b 1 0 1 1 0 0 0 0 b ; 3 d b 1 0 0 1 1 0 0 1 b ; 4 d b 1 0 0 1 0 0 1 0 b ; 5 d b 1 0 0 0 0 0 1 0 b ; 6 d b 1 1 1 1 1 0 0 0 b ; 7 d b 1 0 0 0 0 0 0 0 b ; 8 d b 1 0 0 1 0 0 0 0 b ; 9 d b 1 0 0 0 1 0 0 0 b ; A d b 1 0 0 0 0 0 1 1 b ; B d b 1 1 0 0 0 1 1 0 b ; C d b 1 0 1 0 0 0 0 1 b ; D d b 1 0 0 0 0 1 1 0 b ; E d b 1 0 0 0 1 1 1 0 b ; F d b 1 1 1 1 1 1 1 1 b ; Bl a n k ( 1 7 ) ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; a d d _ i n t : ; [ DPH: DPL] + [ APa r 2 : APa r 1 ] - > [ DPH: DPL] p u s h a c c mo v a , APa r 1 a d d a , d p l mo v d p l , a mo v a , APa r 2 a d d c a , d p h mo v d p h , a p o p a c c r e t ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; s u b b _ i n t :

  Pa g e 6

MCUV. ASM

  ; [ DPH: DPL] - [ SPa r 2 : SPa r 1 ] - > [ DPH: DPL] p u s h a c c c l r c mo v a , d p l s u b b a , SPa r 1 mo v d p l , a mo v a , d p h s u b b a , SPa r 2 mo v d p h , a p o p a c c r e t ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; mu l _ i n t : ; [ DPH: DPL] X [ MPa r 2 : MPa r 1 ] - > [ DPH: DPL] p u s h a c c p u s h b mo v a , d p l mo v b , MPa r 1 mu l a b x c h a , d p l p u s h b mo v b , MPa r 2 mu l a b p o p b a d d a , b x c h a , d p h mo v b , MPa r 1 mu l a b a d d a , d p h mo v d p h , a p o p b p o p a c c r e t ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; d i v _ i n t : ; [ DPH: DPL] / [ DPa r 2 : DPa r 1 ] - > [ DPH: DPL] p u s h a c c p u s h b p u s h 2 h p u s h 3 h p u s h 4 h mo v r 2 , # 1 6 c l r a mo v r 3 , a mo v r 4 , a d i _ l o o p : mo v a , d p l a d d a , a c c mo v d p l , a mo v a , d p h r l c a mo v d p h , a mo v a , r 3 r l c a mo v r 3 , a mo v a , r 4 r l c a mo v r 4 , a mo v a , r 3 s u b b a , DPa r 1 mo v b , a mo v a , r 4

  Pa g e 7 MCUV. ASM s u b b a , DPa r 2 j c d i _ s ma l l e r mo v r 4 , a mo v r 3 , b o r l d p l , # 1 d i _ s ma l l e r : d j n z r 2 , d i _ l o o p p o p 4 h p o p 3 h p o p 2 h p o p b p o p a c c r e t e n d

  Pa g e 8

  Features ™

• Compatible with MCS-51 Products • 2K Bytes of Reprogrammable Flash Memory
• – Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range • Fully Static Operation: 0 Hz to 24 MHz
• Two-level Program Memory Lock • 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines • Two 16-bit Timer/Counters
• Six Interrupt Sources

  8-bit

• Programmable Serial UART Channel • Direct LED Drive Outputs

  Microcontroller

• On-chip Analog Comparator • Low-power Idle and Power-down Modes

  with 2K Bytes Description Flash

  The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with

  2K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology

AT89C2051

  and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a power- ful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

  The AT89C2051 provides the following standard features: 2K bytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera- tion down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

  Pin Configuration

PDIP/SOIC

  1

  20 VCC (RXD) P3.0

  2

  19 P1.7 (TXD) P3.1

  3

  18 P1.6

  XTAL2

  4

  17 P1.5

  XTAL1

  5

  16 P1.4 (INT0) P3.2

  6

  15 P1.3 (INT1) P3.3

  7

  14 P1.2 (TO) P3.4

  8

  13 P1.1 (AIN1) (T1) P3.5

  9

  12 P1.0 (AIN0) GND

  10

  11 P3.7 Rev. 0368E–02/00

  Block Diagram

AT89C2051

  XTAL1

  INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input)

  INT0 (external interrupt 0) P3.3

  P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2

  Figure 2. External Clock Drive Configuration Port Pin Alternate Functions

  Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators

  Figure 1. Oscillator Connections

  XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as s There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi- mum voltage high and low time specifications must be observed.

  XTAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics

  Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

  Pin Description

  VCC Supply voltage. GND Ground. Port 1

  Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device.

  RST

  Port 3 also serves the functions of various special features of the AT89C2051 as listed below: Port 3 also receives some control signals for Flash pro- gramming and verification.

  IL ) because of the pullups.

  Port 3 pins P3.0 to P3.5, P3.7 are seven bi-irectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I

  Port 3

  ) because of the internal pullups. Port 1 also receives code data during Flash programming and verification.

  IL

  Port 1 is an 8-bit bi-irectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require exter- nal pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (I

  Each machine cycle takes 12 oscillator or clock cycles.

  Special Function Registers

  A map of the on-chip memory area called the Special Func- random data, and write accesses will have an indetermi- tion Register (SFR) space is shown in the table below. nate effect. Note that not all of the addresses are occupied, and unoc- User software should not write 1s to these unlisted loca- cupied addresses may not be implemented on the chip. tions, since they may be used in future products to invoke Read accesses to these addresses will in general return new features. In that case, the reset or inactive values of the new bits will always be 0.

  Table 1. AT89C2051 SFR Map and Reset Values

  0F8H

  0FFH

  0F0H B

  0F7H 00000000

  0E8H

  0EFH

  0E0H ACC

  0E7H 00000000

  0D8H

  0DFH

  0D0H PSW

  0D7H 00000000

  0C8H

  0CFH

  0C0H

  0C7H

  0B8H

  IP

  0BFH

  XXX00000

  0B0H P3

  0B7H 11111111

  0A8H

  IE

  0AFH

  0XX00000

  0A0H

  0A7H

  98H SCON SBUF

  9FH 00000000

  XXXXXXXX

  90H P1

  97H 11111111

  88H TCON TMOD TL0 TL1 TH0 TH1

  8FH 00000000 00000000 00000000 00000000 00000000 00000000

  80H SP DPL DPH PCON

  87H 00000111 00000000 00000000

  0XXX0000

AT89C2051

  Restrictions on Certain Instructions

1. Branching instructions:

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR

  P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used. It should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

  3 P P Same as mode 2, also verify is disabled.

  2 P U Further programming of the Flash is disabled.

  Program Lock Bits LB1 LB2 Protection Type 1 U U No program lock features.

  is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used.

  CC

  In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Regis- ters retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V

  Power-down Mode

  In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

  The AT89C2051 and is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 2K bytes of flash program memory. It is fully com- pati bl e with the MCS-51 arc hitec tur e, and c an be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is

  Idle Mode

  1. The Lock Bits can only be erased with the Chip Erase operation.

   Note:

  Lock Bit Protection

  On the chip are two lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below:

  Program Memory Lock Bits

  A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions men- tioned above. It is the responsibility of the controller user to know the physical features and limitations of the device b e i n g u s e d a n d a d j u s t t h e i n s t r u c t i o n s u s e d correspondingly.

  The AT89C2051 contains 128 bytes of internal data mem- ory. Thus, in the AT89C2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is exter- nal PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program.

  7FFH for the 89C2051). Violating the physical space limits may cause unknown program behavior. CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family archi- tecture have been preserved.

  These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to

  2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H would not.

2. MOVX-related instructions, Data Memory:

  Programming The Flash

  3. Pulse pin XTAL1 once to advance the internal address counter.

  indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

  Ready/Busy: The Progress of byte programming can also

  be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indi- cate BUSY. P3.1 is pulled High again when programming is done to indicate READY.

  Program Verify: If lock bits LB1 and LB2 have not been

  programmed code data can be read back via the data lines for verification:

  1. Reset the internal address counter to 000H by bringing RST from “L” to “H”.

  2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins.

  4. Read the next code data byte at the port P1 pins.

  power off

  5. Repeat steps 3 and 4 until the entire array is read. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.

  Chip Erase: The entire PEROM array (2K bytes) and the

  two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code array is written with all “1”s in the Chip Erase operation and must be executed before any non- blank memory byte can be re-programmed.

  Reading the Signature Bytes: The signature bytes are

  read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The values returned are as follows.

  (000H) = 1EH indicates manufactured by Atmel (001H) = 21H indicates 89C2051

  Programming Interface

  Data Polling: The AT89C2051 features Data Polling to

  CC

  The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory array in the erased state (i.e., con- tents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the

  2. Set pin RST to “H” Set pin P3.2 to “H”

  array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically.

  Internal Address Counter: The AT89C2051 contains an

  internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by apply- ing a positive going pulse to pin XTAL1.

  Programming Algorithm: To program the AT89C2051, the following sequence is recommended.

  1. Power-up sequence: Apply power between V

  CC

  and GND pins Set RST and XTAL1 to GND

  3. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the PEROM Pro- gramming Modes table.

  10.Power-off sequence: set XTAL1 to “L” set RST to “L” Turn V

  To Program and Verify the Array:

  4. Apply data for Code byte at location 000H to P1.0 to P1.7.

  5. Raise RST to 12V to enable programming.

  6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write cycle is self-timed and typically takes 1.2 ms.

  7. To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3 to P3.7 to the appropiate levels. Output data can be read at the port P1 pins.

  8. To program a byte at the next address location, pulse

  XTAL1 pin once to advance the internal address counter. Apply new data to the port P1 pins.

  9. Repeat steps 5 through 8, changing data and advancing the address counter for the entire 2K bytes array or until the end of the object file is reached.

  Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combi- nation of control signals. The write operation cycle is self- timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

AT89C2051

  Notes:

  1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at XTAL 1 pin.

  2. Chip Erase requires a 10 ms PROG pulse.

  3. P3.1 is pulled Low during programming to indicate RDY/BSY.

  Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory Flash Programming Modes

  

Mode RST/VPP P3.2/PROG P3.3 P3.4 P3.5 P3.7

  Write Code Data

  

  12V L H H H Read Code Da

  

  H H L L H H Write Lock Bit - 1

  12V H H H H Bit - 2

  12V H H L L Chip Erase

  12V H L L L Read Signature Byte H H L L L L

  (2) PP Note: 1. Only used in 12-volt programming mode.

  Flash Programming and Verification Waveforms Flash Programming and Verification Characteristics

  EHQZ

  GHSL

  V PP Hold after PROG

  10 µs t

  GLGH

  PROG Width 1 110 µs t

  ELQV

  ENABLE Low to Data Valid 1.0 µs t

  Data Float after ENABLE 1.0 µs t

  SHGL

  GHBL

  PROG High to BUSY Low 50 ns t

  WC

  Byte Write Cycle Time 2.0 ms t

  BHIH

  RDY/BSY\ to Increment Clock Delay 1.0 µs t

  IHIL

  V PP Setup to PROG Low 10 µs t

  1.0 µs t

  T

  12.5 V

  A

  = 0°C to 70°C, V

  CC

  = 5.0 ± 10%

  Symbol Parameter Min Max Units

  V PP Programming Enable Voltage

  11.5

  I PP Programming Enable Current

  PP

  250 µA t

  DVGL

  Data Setup to PROG Low 1.0 µs t

  GHDX

  Data Hold after PROG 1.0 µs t

  EHSH

  P3.4 (ENABLE) High to V

  Increment Clock High 200 ns

• NOTICE: Stresses beyond those listed under “Absolute
• 0.5
• 0.1
• 0.9
• 0.5
• 0.5

  CC

  IN

  I LI Input Leakage Current (Port P1.0, P1.1) 0 < V

  = 5V ± 10% -750 µA

  CC

  V IN = 2V, V

  I TL Logical 1 to 0 Transition Current (Ports 1, 3)

  V IN = 0.45V

  Logical 0 Input Current (Ports 1, 3)

  IL

  V I

  0.9 V

  CC

  = -12 µA

  OH

  V I

  CC

  0.75 V

  I OH = -30 µA

  2.4 V

  = 5V ± 10%

  CC

  I OH = -80 µA, V

  < V

  ±10 µA

  0.5 V

  = 6V/3V 15/5.5 mA Idle Mode, 12 MHz, V

  CC

  V CC = 3V P1.0 & P1.1 = 0V or V

  100 µA

  CC

  V CC = 6V P1.0 & P1.1 = 0V or V

  

  5/1 mA Power-down Mode

  CC

  = 6V/3V P1.0 & P1.1 = 0V or V

  CC

  CC

  V OS Comparator Input Offset Voltage

  I CC Power Supply Current Active Mode, 12 MHz, V

  = 25°C 10 pF

  A

  Pin Capacitance Test Freq. = 1 MHz, T

  IO

  C

  V RRST Reset Pull-down Resistor 50 300 KΩ

  V CC

  V CM Comparator Input Common Mode Voltage

  20 mV

  V CC = 5V

  V OH Output High-voltage (Ports 1, 3)

  = 2.7V

  20 µA

  OL

  = -40°C to 85°C, V

  A

  T

  DC Characteristics

  Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V DC Output Current...................................................... 25.0 mA

  Operating Temperature ................................. -55°C to +125°C

  Absolute Maximum Ratings*

  CC for Power-down is 2V.

  2. Minimum V

  may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

  exceeds the test condition, V

  = 2.0V to 6.0V (unless otherwise noted)

  OL

  for all output pins: 80 mA If I

  OL

  per port pin: 20 mA Maximum total I

  OL

  must be externally limited as follows: Maximum I

  OL

  1. Under steady state (non-transient) conditions, I

  Notes:

  AT89C2051

  CC

  

Symbol Parameter Condition Min Max Units

  CC

  CC

  I OL = 10 mA, V

  = 5V

  CC

  I OL = 20 mA, V

  (Ports 1, 3)

  

  Output Low-voltage

  OL

  V V

  V CC

  0.7 V

  V IL Input Low-voltage

  Input High-voltage (XTAL1, RST)

  IH1

  V V

  V CC

  CC

  0.2 V

  Input High-voltage (Except XTAL1, RST)

  IH

  V V

  CC

  0.2 V

• 50 µA

  External Clock Drive Waveforms External Clock Drive Symbol Parameter

  High Time

  Fall Time

  CHCL

  20 20 ns t

  Rise Time

  CLCH

  30 15 ns t

  Low Time

  CLCX

  30 15 ns t

  CHCX

  V CC = 2.7V to 6.0V

  83.3 41.6 ns t

  Clock Period

  CLCL

  24 MHz t

  12

  Oscillator Frequency

  CLCL

  1/t

  V CC = 4.0V to 6.0V Units Min Max Min Max

  20 20 ns

AT89C2051

  Symbol Parameter

• 117 ns t

  XHQX

  QVXH

  µs t

  CLCL

  Serial Port Clock Cycle Time 1.0 12t

  XLXL

  t

  12 MHz Osc Variable Oscillator Units Min Max Min Max

  V CC = 5.0V ± 20%; Load Capacitance = 80 pF

  Serial Port Timing: Shift Register Mode Test Conditions

• 133 ns t

  CLCL

  Output Data Hold after Clock Rising Edge 50 2t

  CLCL

  XHDX

   Note:

  Float Waveform

  Input Data Hold after Clock Rising Edge ns t

  XHDV

  Clock Rising Edge to Input Data Valid 700 10t

  CLCL

   Note:

  ₍₎ Shift Register Mode Timing Waveforms AC Testing Input/Output Waveform

  Output Data Setup to Clock Rising Edge 700 10t

• 133 ns

1. AC Inputs during testing are driven at V

• 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V

  OL level occurs.

  /V

  OH

  1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change frothe loaded V

  max. for a logic 0.

  IL

  min. for a logic 1 and V

  IH

  CC

  AT89C2051 TYPICAL ICC - ACTIVE (85°C)

  20 Vcc=6.0V

  15 I C Vcc=5.0V C

  10 Vcc=3.0V m

5 A

  6

  12

  18

  24 FREQUENCY (MHz) AT89C2051 TYPICAL ICC - IDLE (85°C)

3 Vcc=6.0V

  I

  2 C Vcc=5.0V C

  1 m A

  Vcc=3.0V

  3

  6

  9

  12 FREQUENCY (MHz) AT89C2051 TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C)

  20

  15 I C C

  10 µ

5 A

  3.0V

  4.0V

  5.0V

  6.0V Vcc VOLTAGE

  Notes:

  1. XTAL1 tied to GND for I (power-down)

  CC

  2. P.1.0 and P1.1 = V or GND

  CC

  3. Lock bits programmed

  AT89C2051 Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range

  20P3

  20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)

  

Package Type

  (-40°C to 85°C)

  20S Industrial

  20P3

  (0°C to 70°C) AT89C2051-24PI AT89C2051-24SI

  20S Commercial

  4.0V to 6.0V AT89C2051-24PC AT89C2051-24SC

  12

  24

  (-40°C to 85°C)

  20S Industrial

  20P3

  (0°C to 70°C) AT89C2051-12PI AT89C2051-12SI

  20S Commercial

  20P3

  2.7V to 6.0V AT89C2051-12PC AT89C2051-12SC

  20S 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

  Packaging Information

  20P3, 20-lead, 0.300" Wide, Plastic Dual Inline

  20S, 20-lead, 0.300" Wide, Plastic Gull WIng Small

  Package (PDIP) Outline (SOIC) Dimensions in Inches and (Millimeters) Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AD

  1.060(26.9) _{0.013 (0.330)} ^{0.020 (0.508)} .980(24.9) PIN

  1 .280(7.11) _{0.299 (7.60) 0.420 (10.7)} .240(6.10) 0.291 (7.39) 0.393 (9.98) _{PIN 1} .090(2.29)

  .900(22.86) REF MAX _{.050 (1.27) BSC} .210(5.33) .005(.127) MAX

  MIN SEATING PLANE ^{0.513 (13.0)} _{0.497 (12.6) 0.105 (2.67)} .015(.381) MIN _{0.092 (2.34)} .150(3.81) .115(2.92) .022(.559) .014(.356)

  .070(1.78) .110(2.79) _{0.012 (0.305)} .045(1.13) .090(2.29) ^{0.003 (0.076)} .325(8.26)

  .300(7.62) _{8 REF 0.013 (0.330)} REF _{0.009 (0.229)}

  15 .014(.356) .008(.203) _{0.035 (0.889)} .430(10.92) MAX _{0.015 (0.381)}

  Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway 1150 E. Cheyenne Mtn. Blvd.

  San Jose, CA 95131 Colorado Springs, CO 80906 TEL (408) 441-0311 TEL (719) 576-3300 FAX (408) 487-2600 FAX (719) 540-1759

  Europe Atmel Rousset

  Atmel U.K., Ltd. Zone Industrielle Coliseum Business Centre 13106 Rousset Cedex Riverside Way France Camberley, Surrey GU15 3YL TEL (33) 4-4253-6000 England FAX (33) 4-4253-6001 TEL (44) 1276-686-677 FAX (44) 1276-686-697

  Asia Atmel Asia, Ltd.

  Room 1219 Chinachem Golden Plaza

  77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369

  Japan Atmel Japan K.K.

  9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581

  Fax-on-Demand

  North America: 1-(800) 292-8635 International: 1-(408) 441-0732

  e-mail

  literature@atmel.com

  Web Site

  http://www.atmel.com

  BBS

  1-(408) 436-4309 © Atmel Corporation 2000.

  

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life suppor t devices or systems.

  ® ™ Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

  Printed on recycled paper. Terms and product names in this document may be trademarks of others. LM358, LM258, LM2904, LM2904A, LM2904V, NCV2904 Single Supply Dual Operational Amplifiers http://onsemi.com

  Utilizing the circuit designs perfected for Quad Operational Amplifiers, these dual operational amplifiers feature low power drain, a common mode input voltage range extending to ground/V , and

  EE

  PDIP−8 single supply or split supply operation. The LM358 series is

  N, AN, VN SUFFIX equivalent to one−half of an LM324.

  CASE 626

  8 These amplifiers have several distinct advantages over standard

  1

  operational amplifier types in single supply applications. They can operate at supply voltages as low as 3.0 V or as high as 32 V, with SOIC−8 quiescent currents about one−fifth of those associated with the

  D, VD SUFFIX

  8 MC1741 (on a per amplifier basis). The common mode input range

  CASE 751

  1

  includes the negative supply, thereby eliminating the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage.

  Micro8] Features

  8 DMR2 SUFFIX

  Short Circuit Protected Outputs

• CASE 846A

  1

• True Differential Input Stage
• Single Supply Operation: 3.0 V to 32 V

  Low Input Bias Currents

• PIN CONNECTIONS
• Internally Compensated

  8 Output A Common Mode Range Extends to Negative Supply

  V CC

• 1

  7 Output B −

  Single and Split Supply Operation

• 2

  Inputs A

  3

  6 −

  Inputs B

  ESD Clamps on the Inputs Increase Ruggedness of the Device

• 4

  5 V /Gnd EE without Affecting Operation

  Pb−Free Packages are Available

• (Top View)
• NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes

ORDERING INFORMATION

  See detailed ordering and shipping information in the package dimensions

DEVICE MARKING INFORMATION

  See general marking information in the device marking section

LM358, LM258, LM2904, LM2904A, LM2904V, NCV2904

  Bias Circuitry Common to Both

  (One−Half of Circuit Shown)

  

Figure 2. Representative Schematic Diagram

  25 Figure 1.

  2.0 k Q24 Q23 Q12

  5.0 pF Q18 Q17 Q20 Q21

  40 k Q13 Q14 Q15 Q16 Q19

  2.4 k Q25 Q22

  Inputs Q2 Q3 Q4 Q5 Q26 Q7 Q8 Q6 Q9 Q11 Q10 Q1

  V EE /Gnd

  V CC

  Amplifiers

  Single Supply Split Supplies

  V CC

  CC(max)

  1.5 V to V

  EE

  2 V

  1

  CC

  2 V

  1

  CC(max)

  3.0 V to V

  V EE /Gnd

  1.5 V to V EE(max) Output

LM358, LM258, LM2904, LM2904A, LM2904V, NCV2904

  (T = +25 °

  C, unless otherwise noted.)

  MAXIMUM RATINGS A Rating Symbol Value Unit

  Power Supply Voltages Vdc

  Single Supply

  V

  32 CC Split Supplies

  V , V ±

  16 CC EE Input Differential V V ±

  32 Vdc

  IDR

  Input Common Mode V V −0.3 to 32 Vdc

  ICR

  Output Short Circuit Duration t SC Continuous Junction Temperature

  T 150 ° C

  J