1-bit ALU for MSB (correction)

  1-bit ALU for MSB (correction) ALUop b i

  2 °

  The ALU for the MSB must also

  less i a i

  detect overflow and indicate the ₇ sign of the result.

  Lecture 6: Multiply, Shift, and Divide V c c

  = n ⊗ n −

  1 c

  V set ( A B ) i = <

  Professor Mike Schulte Computer Architecture ECE 201

  c

• i

  1

  2

  1

  3 ALUop 1 ,

  ° 4 versions of multiply hardware & algorithm:

  ° Paper and pencil example (unsigned): Multiplicand

  ° Binary makes it easy:

  n bits x n bits = 2n bit product

  °

  Product 01001000 = 72

  1001 = 9 1000 0000 0000 1000

  1000 = 8 Multiplier

  ° shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable MULTIPLY (unsigned)

  MIPS instructions ° Instruction Example Meaning Comments ° multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product

  ° shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable

  ° shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable

  ° shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)

  ° shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant

  Hi = $2 mod $3 ° Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi ° Move from Lo mflo $1 $1 = Lo Used to get copy of Lo ° shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant

  ° Hi = $2 mod $3 ° divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder °

  ° multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product ° divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder

• 0 => place 0 ( 0 x multiplicand)
• 1 => place a copy ( 1 x multiplicand)
• successive refinement

  Unsigned Combinational Multiplier How does it work? A A A A _{3 2 1} A A A A _{3 2 1} B B A A A A _{3 2 1} B ₁ A A A A _{3 2 1} B ₁ A A A A _{3 2 1} B ₂ A A A A _{3 2 1} A A A A _{3 2 1} B B _{2 3} P P P P P P P P _{7 6 5 4 3 2 1} A A A A _{3 2 1} B ₃

  °

  at each stage shift A left ( x 2)

  P P P P P P P P _{7 6 5 4 3 2 1} °

  use next bit of B to determine whether to add in shifted multiplicand

  i °

  Stage i accumulates A * 2 if B == 1

  i °

  accumulate 2n bit partial product at each stage

  ° Q: How much hardware for 32 bit multiplier?

  Multiply Algorithm Version 1 Start Unisigned shift-add multiplier (version 1)

  Multiplier0 = 1 Multiplier0 = 0

  ° 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg,

  1. Test Multiplier0 32-bit multiplier reg Shift Left 1a. Add multiplicand to product & Multiplicand place the result in Product register 64 bits

  ° Product Multiplier Multiplicand

  Multiplier Shift Right 0000 0000 0011 0000 0010 2. Shift the Multiplicand register left 1 bit. 64-bit ALU 32 bits

  °

  0000 0010 0001 0000 0100 3. Shift the Multiplier register right 1 bit. Write

  ° 0000 0110 0000 0000 1000

  Product

  Control

  64 bits

  ° th 0000 0110

  n No: < n repetitions repetition? Yes: n repetitions

  Multiplier = datapath + control

  Observations on Multiply Version 1 MULTIPLY HARDWARE Version 2 °

  ° 1 clock per cycle => ≈≈ 100 clocks per multiply 32 -bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg

  ° 1/2 bits in multiplicand always 0 => 64-bit adder is wasted

  Multiplicand

  ° 0’s inserted in left of multiplicand as shifted

  32 bits

  => least significant bits of product never changed

  Multiplier Shift Right

  once formed

  32-bit ALU 32 bits

  ° Instead of shifting multiplicand to left, shift product to Shift Right right.

  Product

  Control

  Write 64 bits

  Multiply Algorithm Version 2 3. Shift the Multiplier register right 1 bit.

1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register n

  th

  00 00 00 0010

  Product Multiplier Multiplicand

  3: 0000 110 000 0 0010 1: 0000 110 000 0 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010

  00 00 0010

  2: 0000 110

  00 00 00 0010

  1: 0001 10

  3: 0001 10

  repetition? Start 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010 1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010

  Done Yes: n repetitions 2. Shift the Product register right 1 bit. No: < n repetitions

  repetition? Start 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0 000 0011 0010 3: 0001 0 000 001 0010 1: 0011 0 000 001 0010 2: 0001 10

  th

  1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register n

  Done Yes: n repetitions 2. Shift the Product register right 1 bit. No: < n repetitions

   0000 0110 0000 0010 Product Multiplier Multiplicand Still more wasted space! 3. Shift the Multiplier register right 1 bit.

  00 001 0010

  Observations on Multiply Version 2 MULTIPLY HARDWARE Version 3 °

  °

Product register wastes space that exactly matches 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product

size of multiplier reg, ( -bit Multiplier reg)

  ° Both Multiplier register and Product register require

  Multiplicand

  right shift

  32 bits

  ° Combine Multiplier register and Product register

  32-bit ALU Shift Right Product

  (Multiplier) Control

  Write 64 bits

  Start

  Multiply Algorithm Version 3 Observations on Multiply Version 3

  Multiplicand Product 0010 0000 0011

  Product0 = 1 Product0 = 0

1. Test ° 2 steps per bit because Multiplier & Product combined

  Product0 ° MIPS registers Hi and Lo are left and right half of Product °

  Gives us MIPS instruction MultU 1a. Add multiplicand to the left half of product & place the result in the left half of Product register ° What about signed multiplication?

• easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) 2. Shift the Product register right 1 bit.
• apply definition of 2’s complement
• need to sign-extend partial products and subtract at the end
• Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles can be modified to handle multiple bits at a time
• 32nd

  No: < 32 repetitions repetition? Yes: 32 repetitions

  Motivation for Booth’s Algorithm Booth’s Algorithm ° Example 2 x 6 = 0010 x 0110: middle of run

   0010

  end of run beginning of run

   x 0110 + 0000 shift (0 in multiplier)

• + 0010 add (1 in multiplier) 0 1 1 1 1 0
• + 0010 add (1 in multiplier) + 0000 shift (0 in multiplier) Current Bit Bit to the Right Explanation Example Op

  00001100

  1 Begins run of 1s 000111

  10

  00 sub

  °

  ALU with add or subtract gets same result in more than one way: 6 = – 2 + 8

  1

  1 Middle of run of 1s 00011

  11 000 none

  0110 = – 00010 + 01000

  1 End of run of 1s

  00

  01 111000 add °

  For example Middle of run of 0s

  00 1111000 none °

   0010 x

11 Originally for Speed (when shift was faster than add)

   0000 shift (0 in multiplier)

• – 0010 sub (start string of 1’s)

  ° Replace a string of 1s in multiplier with an initial subtract when we first

   0000 shift (mid string of 1’s) see a one and then later add for the bit after the last one

• –1
• + 0010 add (end string of 1’s)
• + 10000 00001100

  01111

  Operation Multiplicand Product next? 0. initial value 0010 0000 1101 10 -> sub

  1 01 -> add

  1 done

  4b. 0010 1111 1010

  1 1 shift

  4a 1111 010

  1 1 11 -> nop

  3b. 0010 1111 010

  11 shift

  11 10 -> sub

  2b. 0010 0000 10

  1 shift P

  1a. P = P - m 1110 + 1110 1110 1101 shift P (sign ext) 1b. 0010 1111 0 110

  Booths Example (2 x -3)

• + 1110 3a. 0010 1110 10

  4b. 0010 0000 1110 done Operation Multiplicand Product next? 0. initial value 0010 0000 0111 10 -> sub

  1 shift

  4a. 0010 + 0010 0001 110

  1 01 -> add

  3. 0010 1111 110

  01 1 11 -> nop, shift

  2. 0010 1111 10

  1 11 -> nop, shift

  1a. P = P - m 1110 + 1110 1110 0111 shift P (sign ext) 1b. 0010 1111 0 011

  Booths Example (2 x 7)

• + 0010 2a. 0001 0 110

  Shifters

  1

  1

  1

  1

  1

  1

  1

  1

  1

  1

  1

  1

  1

  1

  1

  Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend "0" msb lsb "0" msb lsb "0"

  1

  1

  1

  1

  1

  1

  1

  1

  1 sel A B D Basic Building Block 8-bit right shifter

  How many levels for 32-bit shifter?

  °

  What comes in the MSBs?

  Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! Combinational Shifter from MUXes °

  1 S ₂ S ₁ S A A ₁ A ₂ A ₃ A ₄ A ₅ A ₆ A ₇ R R ₁ R ₂ R ₃ R ₄ R ₅ R ₆ R ₇ 2-to-1 Mux

  Unsigned Divide: Paper & Pencil DIVIDE HARDWARE Version 1

   1001 Quotient

  ° 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Divisor 1000 1001010 Dividend –1000

   10 Shift Right 101 Divisor 1010

  64 bits

• –1000

   10 Remainder (or Modulo result) Quotient Shift Left 64-bit ALU 32 bits See how big a number can be subtracted, creating quotient bit on each step

  Write Remainder Binary => 1 * divisor or 0 * divisor

  Control

  64 bits Dividend = Quotient x Divisor + Remainder 3 versions of divide, successive refinement

  Start: Place Dividend in Remainder

  Divide Algorithm Version 1 Observations on Divide Version 1 ° Takes n+1 steps for n-bit Quotient & Rem.

  1. Subtract the Divisor register from the Remainder register, and place the result Remainder Quotient Divisor

  ° 1/2 bits in divisor always 0 in the Remainder register. 0000 0111 0000 0010 0000 => 1/2 of 64-bit adder is wasted

  Test Remainder < 0 Remainder

  ≥≥ => 1/2 of divisor is wasted

  Remainder

  ° Instead of shifting divisor to right,

  2a. Shift the 2b. Restore the original value by adding the

  shift remainder to left?

  Quotient register Divisor register to the Remainder register, & to the left setting place the sum in the Remainder register. Also

  ° 1st step cannot produce a 1 in quotient bit

  the new rightmost shift the Quotient register to the left, setting bit to 1. the new least significant bit to 0.

  (otherwise too big) => switch order to shift first and then subtract,

  3. Shift the Divisor register right 1 bit. can save 1 iteration n+1 No: < n+1 repetitions repetition? Yes: n+1 repetitions (n = 4 here)

  Divide: Paper & Pencil DIVIDE HARDWARE Version 2

  ° 32 -bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg,

  1010 Quotient

  32-bit Quotient reg Divisor 0001 00001010 Dividend

   00001

• –0001

   0000 0001 Divisor

• –0001

  32 bits

   00 Remainder (or Modulo result) Quotient Shift Left 32-bit ALU 32 bits

• Notice that there is no way to get a 1 in leading digit!

  Shift Left (this would be an overflow, since quotient would have

  Remainder

  Control n+1 bits)

  Write 64 bits

  Start: Place Dividend in Remainder

  Divide Algorithm Version 2 Observations on Divide Version 2

  Remainder Quotient Divisor 1. Shift the Remainder register left 1 bit.

  0000 0111 0000 0010 ° Eliminate Quotient register by combining with Remainder as shifted left

2. Subtract the Divisor register from the Start by shifting the Remainder left as before.

• left half of the Remainder register, & place the

  left half of the

• result in the Remainder register. Thereafter loop contains only two steps because the shifting of the

  Remainder register shifts both the remainder in the left half and the quotient in the right half Test Remainder Remainder < 0

  ≥ ≥

  The consequence of combining the two registers together and the • Remainder new order of the operations in the loop is that the remainder will shifted left one time too many.

  3a. Shift the 3b. Restore the original value by adding the Divisor

• Quotient register register to the left half of the Remainderregister, the left half of the register to the left setting &place the sum in the left half of the Remainder the new rightmost register. Also shift the Quotient register to the left, bit to 1. setting the new least significant bit to 0.

   Thus the final correction step must shift back only the remainder in

  nth No: < n repetitions

  repetition? Yes: n repetitions (n = 4 here)

  DIVIDE HARDWARE Version 3 °

  32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, ( -bit Quotient reg)

  Remainder (Quotient) Divisor 32-bit ALU Write

  Control

  32 bits 64 bits Shift Left

  “HI” “LO” Divide Algorithm Version 3

  Remainder Divisor

  0000 0111 0010

  3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. Test Remainder Remainder < 0 Remainder • 0

  2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3a. Shift the

  Remainder register

  to the left setting the new rightmost bit to 1.

  1. Shift the Remainder register left 1 bit. Yes: n repetitions (n = 4 here) nth repetition? No: < n repetitions Start: Place Dividend in Remainder

  Observations on Divide Version 3

° Same Hardware as Multiply: just need ALU to add or subtract, and 63-bit

  register to shift left or shift right

  °

  Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide

  °

  Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary Note: Dividend and Remainder must have same sign

• Note: Quotient negated if Divisor sign & Dividend sign disagree
• e.g., –7 ÷ 2 = –3, remainder = –1

  °

  Possible for quotient to be too large: if divide 64-bit interger by 1, quotient is 64 bit