ISSN: 2180 - 1843 Vol. 2 No. 1 January - June 2010 Journal of Telecommunication, Electronic and Computer Engineering
64
the current technology of Orthogonal Frequency Division Multiplexing OFDM
adopted in IEEE 802.16 WiMAX standard, the system can provide high data rate
up to 70 Mbps [2]. The RF receiver in WiMAX system plays a paramount role
in converting baseband signal from the RF signal so that the system can be
communicating wirelessly. Therefore, the performance of the WiMAX system
also relies on the RF front end receiver system such as LNA where it must be
well designed to minimize the noise level or distortions in the system.[3] .
The approach taken in designing the ampliiers involves a series of
chronological steps. No design is complete without some desired goals. The design
speciications for the low noise ampliier were shown in Table 1:
Table 1 Design speciications for LNA
LNA
Gain dB 35
Frequency 5.8 GHz
NF dB 3
Matching Technique Microstrip and lump reactive
element VSWR
1.5 Bandwidth MHz
1000 5.8 GHz Centre Input sensitivity
- 80 dBm WiMAX Refering to Table 1 the gain targeted for the LNA is
Refering to Table 1 the gain targeted for the LNA is more than 35 dB. This gain is
necessary to amplify weak signals and separated from the noise. The ampliier
will maintain noise igure less than 3 dB and provide bandwidth of 1000 MHz.
The input sensitivity for the LNA is set at -80dBm compliant with the standard
WiMAX application.
II. THeOReTICaL DIsCRIpTION
Basically, for the design of an ampliier, the input and output matching network
are designed to achieve the required stability, small signal gain, and bandwidth
[4]. Super high frequency ampliier is a typical active circuit used to amplify the
amplitude of RF signal. Basic concept and consideration in design of super high
frequency ampliier is presented below. For the LNA designed, the formulae and
equation were referred to [1]. Figure 1 shows a typical single-stage ampliier
including inputoutput
matching networks.
Figure 1 Typical amplifier designed
Figure 1 Typical ampliier designed
The basic concept of high frequency ampliier design is to match inputoutput
of a transistor at high frequencies using S parameters [S] frequency characteristics
at a speciic DC-bias point with source impedance and load impedance. IO
matching circuit is essential to reduce unwanted relection of signal and to
improve eiciency of transmission from source to load. The targeted speciication
ampliier is shown in Table 1.
Power Gain Several power gains were deined in order
to understand operation of super high frequency ampliier, as shown in Figure
2, power gains of 2 port circuit network with power impedance or load impedance
at power ampliier represented with scatering coeicient are classiied into
Operating Power Gain, Transducer Power Gain and Available Power Gain.[4],[5]
LNA is weak
r will width
set at - on.
t and e the
h [4]. Figure 2 IO circuit of 2-port network
Figure 2 IO circuit of 2-port network
ISSN: 2180 - 1843 Vol. 2 No. 1 January - June 2010 High Gain Cascaded Low Noise Ampliier using T – Matching Network
65
Operating Power Gain Operating power gain is the ratio of
power P
L
delivered to the load Z
L
to power P
in
supplied to 2 port network. Power delivered to the load is the
diference between the power relected at the output port and the input power,
and power supplied to 2-port network is the diference between the input power
at the input port and the relected power. Therefore, Operating Power Gain is
represented by
1 |
1 |
| |
1 |
| |
| 1
1 supplied
2 22
2 2
21 2
L L
in in
L P
S S
P P
amplifier the
to power
load the
to delivered
Power G
Where, T
in
indicates relection coeicient of load at the input port of 2-port network
and T
s
is relection coeicient of power supplied to the input port.
Transducer Power Gain Transducer Power Gain is the ratio of P
avs
, maximum power available from source to P
L
, power delivered to the load. As maximum power is obtained when input
impedance of circuit network is equal to conjugate complex number of power
impedance, if T
in
= T
s
, transducer power gain is represented by
2 |
1 1
| |
| 1
| |
1 |
| supplied
2 21
12 22
11 2
2 2
21 L
S L
S L
S in
L P
S S
S S
S P
P amplifier
the to
power load
the to
delivered Power
G
Where, indicates load reflection coefficient.
¸¸¹ ·
¨¨© §
Where, T
L
indicates load relection coeicient.
Available Power Gain Available Power Gain, G
A
is the ratio of P
avs
, power available from the source, to P
avn
, power available from 2-port network, that
is,
avn
P
that is,
avs avn
A
P P
G
. Po . Therefore Available Po
¸¸¹ ·
¨¨© §
Power gain is P
avn
when Tin = T
s
. Therefore Available Power Gain is given by:
3 |
1 |
1 |
| |
1 |
| |
1 supplied
2 22
2 21
2 11
2 L
S S
avs avn
S S
S P
P amplifier
the to
power
That is, the above formula indicates power gain when input
¸¸¹ ·
¨¨© §
That is, the above formula indicates power gain when input and output are
matched.
Noise Figure Signals and noises applied to the input
port of ampliier were ampliied by the gain of the ampliier and noise of ampliier
itself is added to the output. Therefore, SNR Signal to Noise Ratio of the output
port is smaller than that of the input port. The ratio of SNR of input port to that of
output port is referred to as noise igure and is larger than 1 dB. Typically, noise
igure of 2-port transistor has a minimum value at the speciied admitance given by
formula:
4 |
|
2 min
opt s
S N
Y Y
G R
F F
¸¸¹ ·
¨¨© §
For low noise transistors, manufactures usually provide
opt N
Y R
F ,
,
min
by frequencies. N
deined by formula for desired noise igure:
to the input
mplex power
5 |
1 |
4 |
| 1
| |
2 min
2 2
opt N
S opt
s
Z R
F F
N
Condition for Matching
¸¸¹ ·
¨¨© §
Condition for Matching The scatering coeicients of transistor
were determined. The only lexibility permited to the designer is the input
output matching circuit. The input circuit should match to the source and the output
circuit should match to the load in order to deliver maximum power to the load. Ater
stability of active device is determined, inputoutput matching circuits should be
designed so that relection coeicient of each port can be correlated with conjugate
complex number as given below:
ISSN: 2180 - 1843 Vol. 2 No. 1 January - June 2010 Journal of Telecommunication, Electronic and Computer Engineering
66
power rom 2-
s given
L L
S IN
S S
S S
22 21
12 11
1
6
S S
L OUT
S S
S S
11 21
12 22
1
7 The noise figure of the first stage of the receiver
¸¸¹ ·
¨¨© §
The noise igure of the irst stage of the receiver overrules noise igure of the
whole system. To get minimum noise igure using transistor, power relection
coeicient should match with T
opt
and load relection coeicient should match
with T
out
s
=
opt
8
¸¸¹ ·
¨¨© §
s s
out L
S S
S S
11 21
12 22
1
9
Design LNa
From equation 1 to 9, the related power gain and noise igure for single stage LNA
are calculated. By using ADS 2005A, the noise igure circle was outside the unit
circle and the VSWR recorded was 2.179. From simulation, it was recorded that
the ampliier gain S21 was 17.23 dB. The input insertion loss S11 was -6.28dB and
the output insertion loss S22 was -7.60dB. The relected loss S12 was -20.18 dB and
the noise igure was 1.16 dB. These values were within the design speciication and
were accepted. The overall performance of the low noise
ampliier is determined by calculating the transducer gain GT, noise igure F and the
input and output standing wave ratios, VSWR
IN
and VSWR
OUT
. The optimum, T
opt
and T
L
were obtained as T
opt
= 17.354 +j 50.131 and T
L
= 79.913- j7.304. The calculated gain for the LNA was 19.3 dB,
which correspond to a noise igure of 0.301 dB. The input matching load T
opt
is required to provide high-loaded Q factor
for beter sensitivity. A T-network was used to match the input impedance. The
elements of T-network can be realized in the form of lump reactive elements and
microstrip line impedance. Using Smith Chart matching technique, the component
values are shown in Table 2. The DC block capacitor was selected for the
circuit and the value is recommended at least 10 times from the C
1
. For this reason 7.5 pF capacitors are selected as bypass
capacitors. With these components, the schematic circuit for single stage LNA is
shown in Figure 3.
Table 2 LNA Ampliier parameters
Components Values
L
1
3.60 nH L
2
0.88 nH L
3
0.67 nH L
4
0.75 nH C
1
0.5012 pF C
B
7.5 pF
Figure 3 The schematic circuit for single stage amplifier
Figure 3 The schematic circuit for single stage ampliier
To achieve the targeted overall gain of 35 dB, it was decided to design a cascaded
ampliier using similar stages to double the LNA gain. The simulation of cascaded
ampliier will be discussed in section III.
III. sImULaTION
