sImULaTION High Gain Cascaded Low Noise Amplifier using T – Matching Network.
ISSN: 2180 - 1843 Vol. 2 No. 1 January - June 2010 Journal of Telecommunication, Electronic and Computer Engineering
66
power rom 2-
s given
L L
S IN
S S
S S
22 21
12 11
1
6
S S
L OUT
S S
S S
11 21
12 22
1
7 The noise figure of the first stage of the receiver
¸¸¹ ·
¨¨© §
The noise igure of the irst stage of the receiver overrules noise igure of the
whole system. To get minimum noise igure using transistor, power relection
coeicient should match with T
opt
and load relection coeicient should match
with T
out
s
=
opt
8
¸¸¹ ·
¨¨© §
s s
out L
S S
S S
11 21
12 22
1
9
Design LNa
From equation 1 to 9, the related power gain and noise igure for single stage LNA
are calculated. By using ADS 2005A, the noise igure circle was outside the unit
circle and the VSWR recorded was 2.179. From simulation, it was recorded that
the ampliier gain S21 was 17.23 dB. The input insertion loss S11 was -6.28dB and
the output insertion loss S22 was -7.60dB. The relected loss S12 was -20.18 dB and
the noise igure was 1.16 dB. These values were within the design speciication and
were accepted. The overall performance of the low noise
ampliier is determined by calculating the transducer gain GT, noise igure F and the
input and output standing wave ratios, VSWR
IN
and VSWR
OUT
. The optimum, T
opt
and T
L
were obtained as T
opt
= 17.354 +j 50.131 and T
L
= 79.913- j7.304. The calculated gain for the LNA was 19.3 dB,
which correspond to a noise igure of 0.301 dB. The input matching load T
opt
is required to provide high-loaded Q factor
for beter sensitivity. A T-network was used to match the input impedance. The
elements of T-network can be realized in the form of lump reactive elements and
microstrip line impedance. Using Smith Chart matching technique, the component
values are shown in Table 2. The DC block capacitor was selected for the
circuit and the value is recommended at least 10 times from the C
1
. For this reason 7.5 pF capacitors are selected as bypass
capacitors. With these components, the schematic circuit for single stage LNA is
shown in Figure 3.
Table 2 LNA Ampliier parameters
Components Values
L
1
3.60 nH L
2
0.88 nH L
3
0.67 nH L
4
0.75 nH C
1
0.5012 pF C
B
7.5 pF
Figure 3 The schematic circuit for single stage amplifier
Figure 3 The schematic circuit for single stage ampliier
To achieve the targeted overall gain of 35 dB, it was decided to design a cascaded
ampliier using similar stages to double the LNA gain. The simulation of cascaded
ampliier will be discussed in section III.