Implementasi Power Line Communication Pada Jaringan Listrik Arus Searah Sebagai Sistem Kendali Terpusat.
ABSTRAK
Dengan meningkatnya kebutuhan jalur komunikasi data, khususnya pada
komunikasi dengan bandwidth rendah, PLC menjadi metode alternatif untuk
komunikasi sinyal kendali. Sistem PLC dalam Tugas Akhir ini telah dirancang
dan direalisasi dengan menggunakan modulasi FSK sebagai physical layer, dan
menggunakan protokol komunikasi UART. Sebagai pengendali digunakan
mikrokontroler MCS51. Sistem PLC pada Tugas Akhir ini dibuat dengan
konfigurasi satu master dua slave.
Sistem PLC yang telah dibuat diimplementasikan sebagai pengandali on
off dengan jumlah output yang dikendalikan sebanyak 48 output. Dari pengujian
yang telah dilakukan didapatkan kesimpulan bahwa sistem ini dapat bekerja
dengan baik dengan sensitivitas sinyal data sebesar 10 mVpp dan dengan
ketahanan terhadap noise sampai dengan 200 mVpp.
i
ABSTRACT
Within increasing demand in data communication line, especially in
narrow band communication, PLC can be alternative for control signal
communication. PLC system for this final project use FSK modulation as physical
layer, and use UART as communication protocol. Microcontroller MCS51 used
as controller. PLC system in this task uses one master two slave configuration.
This PLC system has been implemented as on off control with 48 outputs.
From the test has been held, these systems can work excellent with 10 mV pp data
signal sensitivity, and noise resistant up to 200 mV pp .
ii
DAFTAR ISI
Halaman
ABSTRAK ...................................................................................................
i
ABSTRACT .................................................................................................
ii
KATA PENGANTAR ................................................................................. iii
DAFTAR ISI ................................................................................................
v
DAFTAR GAMBAR .................................................................................... viii
DAFTAR TABEL ........................................................................................
x
BAB I PENDAHULUAN
I.1
Latar Belakang .................................................................................
1
I.2
Perumusan Masalah .........................................................................
2
I.3
Tujuan ..............................................................................................
2
I.4
Pembatasan Masalah ........................................................................
2
I.5
Alat yang digunakan ........................................................................
2
I.6
Sistematika Pembahasan ..................................................................
2
BAB II TEORI PENUNJANG
II.1 UART (Universal Asynchronous Receive/Transmit) .....................
4
II.2 Modulasi FSK (Frequency Shift Keying) ........................................
5
II.2.1
Modulasi Langsung ....................................................
6
II.2.2
Modulasi dengan FractionalN Synthesizer ..........….
8
II.3 Demodulator FSK Exar XR2211....................................................
9
II.4 LPF (Low Pass Filter) ……............................................................. 13
II.5 BPF (Band Pass Filter) ……........................................................... 14
II.6 Rangkaian Dasar Mikrokontroler …................................................ 15
II.7 Rele ………...………….................................................................. 16
v
BAB III PERANCANGAN
III.1 Perancangan Dan Realisasi LPF ...................................................
19
III.2 Perancangan Dan Realisasi BPF ....................................................
21
III.3 Perancangan Dan Realisasi Modulator FSK ..................................
22
III.4 Perancangan Dan Realisasi Demodulator FSK .............................. 23
III.5 Perancangan Dan Realisasi Rangkaian Mikrokontroler ................
25
III.5.1
Rangkaian Mikrokontroler Master ............................ 25
III.5.2
Rangkaian Mikrokontroler Slave ............................... 26
III.6 Penggabungan Modul – Modul PLC Master Controller ................ 27
III.7 Penggabungan Modul – Modul PLC Slave Controller ................... 28
III.8 Perancangan Dan Realisasi Program Mikrokontroler ..................... 28
BAB IV UJI COBA ALAT
IV.1 Karakteristik LPF ............................................................................ 34
IV.2 Karakteristik BPF ............................................................................ 35
IV.3 Karakteristik Modulator FSK .......................................................... 35
IV.4 Karakteristik Demodulator FSK ...................................................... 36
IV.5 Karakteristik Sinyal FSK Di Jalur Listrik DC ................................. 37
IV.6 Karakteristik Noise Di Jalur Listrik DC .......................................... 38
IV.7 Pengujian Sistem PLC ..................................................................... 38
BAB V KESIMPULAN DAN SARAN
V.1 Kesimpulan ....................................................................................
40
V.2 Saran ..............................................................................................
40
DAFTAR PUSTAKA .................................................................................
xi
vi
LAMPIRAN
Lampiran A
Listing Program Mikrokontroler Master .......................................
A1
Listing Program Mikrokontroler Slave A ......................................
A6
Listing Program Mikrokontroler Slave B ......................................
A10
Lampiran B
Rangkaian Keseluruhan Sistem PLC ........................................... B1
Layout PCB Mikrokontroler Master ............................................ B2
Layout PCB Mikrokontroler Slave ............................................... B3
Layout PCB FSK modulator ......................................................... B4
Layout PCB FSK demodulator ..................................................... B4
Lampiran C
IC LM 555 .................................................................................... C1
IC Exar XR 2211 ........................................................................ C11
Lampiran D
Foto alat ........................................................................................ D1
vii
DAFTAR GAMBAR
Halaman
1. Gambar II1 Timing diagram UART .................................................
5
2. Gambar II2 Spektrum frekuensi FSK ................................................
5
3. Gambar II3 Sinyal FSK .....................................................................
6
4. Gambar II4 Modulasi langsung dengan VCO ..................................
7
5. Gambar II5 IC 555 sebagai FSK modulator .....................................
7
6. Gambar II6 FractionalN Synthesizer ..............................................
8
7. Gambar II7 FSK demodulator ..........................................................
9
8. Gambar II8 Tracking Frequency .......................................................
11
9. Gambar II9 Low pass filter.................................................................
13
10. Gambar II10 High pass filter..............................................................
14
11. Gambar II11 Diagram Blok mikrokontroler AT89S52 .....................
15
12. Gambar II12 Rangkaian dasar mikrokontroler AT89S52 ................
16
13. Gambar II13 SPST (Single Pole Single Throw) ...............................
17
14. Gambar II14 SPDT (Single Pole Double Throw) ..............................
17
15. Gambar II15 DPST (Double Pole Single Throw) ..............................
18
16. Gambar II16 DPDT (Double Pole Double Throw) ...........................
18
17. Gambar III1 Blok diagram PLC .......................................................
19
18. Gambar III2 Low Pass Filter..............................................................
20
19. Gambar III3 High Pass Filter ............................................................
21
20. Gambar III4 Voltage Controlled Oscillator dengan IC 555 .............
23
21. Gambar III5 FSK Demodulator.........................................................
25
22. Gambar III6 Master Controller .........................................................
26
23. Gambar III7 Slave Controller ............................................................
27
24. Gambar III8 Master PLC controller .................................................
27
25. Gambar III9 Slave PLC controller ...................................................
28
26. Gambar III10 Flowchart program master controller ........................
29
27. Gambar III11 Flowchart program slave controller ...........................
29
28. Gambar III12 SFR Timer Mode.........................................................
30
29. Gambar III13 initialisasi TMOD......................................................
30
viii
30. Gambar III14 SFR Serial Port Control...........................................
31
31. Gambar III15Frame data ...............................................................
33
32. Gambar IV1 Karakteristik LPF (logaritmis)...................................
34
33. Gambar IV2 Karakteristik BPF (logaritmis)...................................
35
34. Gambar IV3 Respon PLL demodulator FSK..................................
35
35. Gambar IV4 Pemasangan beban di jalur listrik DC........................
35
ix
DAFTAR TABEL
Halaman
1. Tabel III1 SFR serial mode...............................................................
32
2. Tabel IV1 Karakteristik LPF (Low Pass Filter) ...............................
34
3. Tabel IV2 Karakteristik BPF (Band Pass Filter) ..............................
35
4. Tabel IV3 Karakteristik modulator FSK ...........................................
35
5. Tabel IV4 Karakteristik FSK demodulator terhadap frekuensi .........
36
6. Tabel IV5 Karakteristik demodulator FSK terhadap tegangan .........
37
7. Tabel IV6 Karakteristik sinyal FSK Di Jalur Listrik DC terhadap
beban terpasang ....................................................................................
37
8. Tabel IV7 Karakteristik sinyal FSK Di Beban terhadap
beban terpasang ....................................................................................
38
9. Tabel IV8 Karakteristik noise di jalur listrik DC ...............................
38
10. Tabel IV9 Pengujian Sistem PLC ......................................................
39
x
LAMPIRAN A
Listing Program PLC Controller
Lampiran
Listing program master controller
$mod51
CALL INIT
LAGI:
MOV A,P1
MOV R5,A
MOV P0,#11111110B
JB P0.4,NO2
MOV R0,#01H
NO2:
JB P0.5,NO3
MOV R0,#03H
NO3:
JB P0.6,NOA
MOV R0,#05H
NOA:
JB P0.7,NO4
MOV A,R5
ANL A,#0FH
ADD A,#0F0H
MOV R4,A
MOV A,R0
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
CALL DELAY
A 1
Lampiran
MOV A,R5
ANL A,#0F0H
RL A
RL A
RL A
RL A
ADD A,#0F0H
MOV R4,A
MOV A,R0
INC A
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
NO4:
MOV P0,#11111101B
JB P0.4,NO5
MOV R0,#07H
NO5:
JB P0.5,NO6
MOV R0,#09H
NO6:
JB P0.6,NOB
MOV R0,#0BH
NOB:
JB P0.7,NO7
NO7:
A 2
Lampiran
MOV P0,#11111011B
JB P0.4,NO8
NO8:
MOV R0,#0DH
JB P0.5,NO9
NO9:
MOV R0,#0FH
JB P0.6,NOC
NOC:
JB P0.7,NOSTARR
NOSTARR:
MOV P0,#11110111B
JB P0.4,NO0
MOV R4,#0F0H
MOV A,R0
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
CALL DELAY
MOV R4,#0F0H
MOV A,R0
INC A
RR A
RR A
RR A
RR A
A 3
Lampiran
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
NO0:
JB P0.5,NOKRESS
NOKRESS:
JB P0.6,NOD
MOV R4,#0FFH
MOV A,R0
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
CALL DELAY
MOV R4,#0FFH
MOV A,R0
INC A
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
NOD:
A 4
Lampiran
JB P0.7,NON
NON:
LJMP LAGI
INIT:
MOV P0,#00H
MOV P1,#00H
MOV P2,#00H
MOV SP, #30H
MOV SCON, #50H
;inisialisasi baud rate (9600 bps)
MOV TMOD, #20H
MOV TL1, #0FDH
MOV TH1, #0FDH
MOV PCON, #00H
SETB TR1
RET
KIRIM:
CLR TI
MOV SBUF,A
JNB TI,$
RET
DELAY:
DLY0:
MOV R6,#0FFH
DLY1:
DJNZ R6,DLY1
RET
END
A 5
Lampiran
Listing program slave controler
SLAVE A
$mod51
MOV R0,#00H
MOV R1,#00H
MOV R2,#00H
MOV R3,#00H
MOV R4,#00H
MOV R5,#00H
MOV R6,#00H
MOV R7,#00H
MOV P0,00H
MOV P1,00H
MOV P2,00H
LJMP START
TERIMA:
JNB
RI,$
MOV A,SBUF
MOV R1,A
CLR RI
MOV A,#11110000B
ANL A,R1
MOV R2,A
MOV A,#00001111B
ANL A,R1
MOV R3,A
RR A
RR A
RR A
RR A
MOV R4,A
A 6
Lampiran
RETI
START:
MOV SP, #30H
MOV SCON, #50H
;inisialisasi baud rate (9600 bps)
MOV TMOD, #20H
MOV TL1, #0FDH
MOV TH1, #0FDH
MOV PCON, #00H
SETB TR1
ULANG:
CALL TERIMA
CJNE R2,#10H,ADDB
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R3
MOV P0,A
ADDB:
CJNE R2,#20H,ADDCO
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R4
MOV P0,A
ADDCO:
CJNE R2,#30H,ADDD
MOV A,R3
A 7
Lampiran
ORL A,#0F0H
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R3
MOV P1,A
ADDD:
CJNE R2,#40H,ADDE
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R4
MOV P1,A
ADDE:
CJNE R2,#50H,ADDF
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P2
ANL A,R5
ORL A,R3
MOV P2,A
ADDF:
CJNE R2,#60H,ADDG
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P2
ANL A,R5
A 8
Lampiran
ORL A,R4
MOV P2,A
ADDG:
LJMP ULANG:
DELAY:
MOV R0,#0FH
DLY1:
MOV R1,#0FFH
DLY0:
DJNZ R1,DLY0
DJNZ R0,DLY1
END
A 9
Lampiran
SLAVE B
$mod51
MOV R0,#00H
MOV R1,#00H
MOV R2,#00H
MOV R3,#00H
MOV R4,#00H
MOV R5,#00H
MOV R6,#00H
MOV R7,#00H
MOV P0,00H
MOV P1,00H
MOV P2,00H
LJMP START
TERIMA:
JNB
RI,$
MOV A,SBUF
MOV R1,A
CLR RI
MOV A,#11110000B
ANL A,R1
MOV R2,A
MOV A,#00001111B
ANL A,R1
MOV R3,A
RR A
RR A
RR A
RR A
MOV R4,A
RETI
A 10
Lampiran
START:
MOV SP, #30H
MOV SCON, #50H
;inisialisasi baud rate (9600 bps)
MOV TMOD, #20H
MOV TL1, #0FDH
MOV TH1, #0FDH
MOV PCON, #00H
SETB TR1
ULANG:
CALL TERIMA
CJNE R2,#70H,ADDB
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R3
MOV P0,A
ADDB:
CJNE R2,#80H,ADDCO
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R4
MOV P0,A
ADDCO:
CJNE R2,#90H,ADDD
MOV A,R3
ORL A,#0F0H
A 11
Lampiran
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R3
MOV P1,A
ADDD:
CJNE R2,#A0H,ADDE
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R4
MOV P1,A
ADDE:
CJNE R2,#B0H,ADDF
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P2
ANL A,R5
ORL A,R3
MOV P2,A
ADDF:
CJNE R2,#C0H,ADDG
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P2
ANL A,R5
ORL A,R4
A 12
Lampiran
MOV P2,A
ADDG:
LJMP ULANG:
DELAY:
MOV R0,#0FH
DLY1:
MOV R1,#0FFH
DLY0:
DJNZ R1,DLY0
DJNZ R0,DLY1
END
A 13
Lampiran
LAMPIRAN B
Rangkaian Dan PCB
A 14
Lampiran
100 nF
12 V
.615 mH
Jalur Listrik DC
Skema Keseluruhan Sistem PLC
A 15
Lampiran
PCB MASTER CONTROLLER
PCB Bottom
PCB Layout
A 16
Lampiran
PCB SLAVE CONTROLLER
PCB Bottom
PCB Layout
A 17
Lampiran
PCB FSK MODULATOR
PCB FSK DEMODULATOR
A 18
Lampiran
A 19
XR-2211
...the analog plus
FSK Demodulator/
Tone Decoder
company TM
June 1997-3
APPLICATIONS
FEATURES
D Wide Frequency Range, 0.01Hz to 300kHz
D Caller Identification Delivery
D Wide Supply Voltage Range, 4.5V to 20V
D FSK Demodulation
D HCMOS/TTL/Logic Compatibility
D Data Synchronization
D FSK Demodulation, with Carrier Detection
D Wide Dynamic Range, 10mV to 3V rms
D Tone Decoding
D Adjustable Tracking Range, +1% to 80%
D FM Detection
D Excellent Temp. Stability, +50ppm/°C, max.
D Carrier Detection
GENERAL DESCRIPTION
quadrature phase detector which provides carrier
detection, and an FSK voltage comparator which provides
FSK demodulation. External components are used to
independently set center frequency, bandwidth, and output
delay. An internal voltage reference proportional to the
power supply is provided at an output pin.
The XR-2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications
applications. It is particularly suited for FSK modem
applications. It operates over a wide supply voltage range
of 4.5 to 20V and a wide frequency range of 0.01Hz to
300kHz. It can accommodate analog signals between
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal within the pass band, a
The XR-2211 is available in 14 pin packages specified for
military and industrial temperature ranges.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XR-2211M
14 Pin CDIP (0.300”)
-55°C to +125°C
XR-2211N
14 Pin CDIP (0.300”)
-40°C to +85°C
XR-2211P
14 Pin PDIP (0.300”)
-40°C to +85°C
XR-2211ID
14 Lead SOIC (Jedec, 0.150”)
-40°C to +85°C
Rev. 3.01
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-2211
BLOCK DIAGRAM
VCC
GND
NC
1
4
9
Pre Amplifier
INP
TIM C1
2
Loop
q-Det
14
Lock
Detect
Comparator
VCO
TIM C2
13
TIM R
12
Quad
q-Det
11
LDO
3
LDF
6
LDOQ
5
LDOQN
7
DO
Internal
VREF
10
VREF
FSK Comp
Reference
COMP I
8
Figure 1. XR-2211 Block Diagram
Rev. 3.01
2
XR-2211
PIN CONFIGURATION
VCC
INP
LDF
GND
LDOQN
LDOQ
DO
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
INP
LDF
GND
LDOQN
LDOQ
DO
TIM C1
TIM C2
TIM R
LDO
VREF
NC
COMP I
14 Lead CDIP, PDIP (0.300”)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
TIM C1
TIM C2
TIM R
LDO
VREF
NC
COMP I
14 Lead SOIC (Jedec, 0.150”)
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
VCC
2
INP
I
Receive Analog Input.
3
LDF
O
Lock Detect Filter.
4
GND
5
LDOQN
O
Lock Detect Output Not. This output will be low if the VCO is in the capture range.
6
LDOQ
O
Lock Detect Output. This output will be high if the VCO is in the capture range.
7
DO
O
Data Output. Decoded FSK output.
8
COMP I
I
FSK Comparator Input.
9
NC
10
VREF
O
Internal Voltage Reference. The value of VREF is VCC/2 - 650mV.
11
LDO
O
Loop Detect Output. This output provides the result of the quadrature phase detection.
12
TIM R
I
Timing Resistor Input. This pin connects to the timing resistor of the VCO.
13
TIM C2
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14
TIM C1
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
Positive Power Supply.
Ground Pin.
Not Connected.
Rev. 3.01
3
XR-2211
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
20
V
4
7
mA
R0 > 10KW. See Figure 4.
+1
+3
%
Deviation from fO = 1/R0 C0
Temperature
+20
+50
ppm/°C
Power Supply
0.05
0.5
%/V
VCC = 12 +1V. See Figure 7.
0.2
%/V
VCC = + 5V. See Figure 7.
300
kHz
R0 = 8.2KW, C0 = 400pF
0.01
Hz
R0 = 2MW, C0 = 50mF
2000
KW
General
Supply Voltage
4.5
Supply Current
Oscillator Section
Frequency Accuracy
Frequency Stability
Upper Frequency Limit
100
Lowest Practical Operating
Frequency
See Figure 8.
Timing Resistor, R0 - See
Figure 5
Operating Range
5
Recommended Range
5
KW
See Figure 7 and Figure 8.
mA
Measured at Pin 11
Loop Phase Dectector Section
Peak Output Current
+150
+200
+300
Output Offset Current
1
mA
Output Impedance
1
MW
+5
V
Maximum Swing
+4
Quadrature Phase Detector
Peak Output Current
Measured at Pin 3
100
300
mA
Output Impedance
1
MW
Maximum Swing
11
VPP
Input Preampt Section
Input Impedance
Referenced to Pin 10
Measured at Pin 2
20
KW
Input Signal
Voltage Required to
Cause Limiting
2
10
mV rms
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 3.01
4
XR-2211
DC ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
2
MW
Measured at Pins 3 and 8
100
nA
70
dB
RL = 5.1KW
Voltage Comparator Section
Input Impedance
Input Bias Current
Voltage Gain
55
Output Voltage Low
300
500
mV
IC = 3mA
Output Leakage Current
0.01
10
mA
VO = 20V
5.3
5.7
V
Measured at Pin 10
AC Small Signal
Internal Reference
Voltage Level
4.9
Output Impedance
100
W
Maximum Source Current
80
mA
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW
Package Power Dissipation Ratings
CDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 8mW/°C
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mW
Derate Above TA = 25°C . . . . . . . . . . . . . . 60mW/°C
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 5mW/°C
SYSTEM DESCRIPTION
The main PLL within the XR-2211 is constructed from an
input preamplifier, analog multiplier used as a phase
detector and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that
input signals above typically 10mV rms are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a
current controlled oscillator with its normal input current
(fO) set by a resistor (R0) to ground and its driving current
with a resistor (R1) from the phase detector.
(internally connected). When in lock, these frequencies
are fIN+ fVCO (2 times fIN when in lock) and fIN - fVCO (0Hz
when lock). By adding a capacitor to the phase detector
output, the 2 times fIN component is reduced, leaving a
DC voltage that represents the phase difference between
the two frequencies. This closes the loop and allows the
VCO to track the input frequency.
The FSK comparator is used to determine if the VCO is
driven above or below the center frequency (FSK
comparator). This will produce both active high and
active low outputs to indicate when the main PLL is in lock
(quadrature phase detector and lock detector
comparator).
The output of the phase detector produces sum and
difference of the input and the VCO frequencies
Rev. 3.01
5
XR-2211
PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this
terminal. The internal impedance at pin 2 is 20KW.
Recommended input signal level is in the range of 10mV
rms to 3V rms.
10 must be bypassed to ground with a 0.1mF capacitor for
proper operation of the circuit.
Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 3.) With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VREF. The peak to peak voltage swing
available at the phase detector output is equal to 2 x VREF.
Quadrature Phase Detector Output (Pin 3): This is the
high impedance output of quadrature phase detector and
is internally connected to the input of lock detect voltage
comparator. In tone detection applications, pin 3 is
connected to ground through a parallel combination of RD
and CD (see Figure 3) to eliminate the chatter at lock
detect outputs. If the tone detect section is not used, pin 3
can be left open.
VCO Control Input (Pin 12): VCO free-running
frequency is determined by external timing resistor, R0,
connected from this terminal to ground. The VCO
free-running frequency, fO, is:
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
“low” state when the PLL is out of lock and goes to “high”
state when the PLL is locked. It is an open collector type
output and requires a pull-up resistor, RL, to VCC for
proper operation. At “low” state, it can sink up to 5mA of
load current.
fO +
1
Hz
R 0·C 0
where C0 is the timing capacitor across pins 13 and 14.
For optimum temperature stability, R0 must be in the
range of 10KW to 100KW (see Figure 9.)
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6.
This output is also an open collector type stage which can
sink 5mA of load current at low or “on” state.
This terminal is a low impedance point, and is internally
biased at a DC level equal to VREF. The maximum timing
current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, RL, to VCC for
proper operation. It can sink 5mA of load current. When
decoding FSK signals, FSK data output is at “high” or “off”
state for low input frequency, and at “low” or “on” state for
high input frequency. If no input signal is present, the logic
state at pin 7 is indeterminate.
VCO Timing Capacitor (Pins 13 and 14): VCO
frequency is inversely proportional to the external timing
capacitor, C0, connected across these terminals (see
Figure 6.) C0 must be non-polar, and in the range of
200pF to 10mF.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with R0 at pin 12
(see Figure 10.)
FSK Comparator Input (Pin 8): This is the high
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase
detector output (pin 11). This data filter is formed by RF
and CF (see Figure 3.) The threshold voltage of the
comparator is set by the internal reference voltage, VREF,
available at pin 10.
VCO Free-Running Frequency, fO: XR-2211 does not
have a separate VCO output terminal. Instead, the VCO
outputs are internally connected to the phase detector
sections of the circuit. For set-up or adjustment purposes,
the VCO free-running frequency can be tuned by using
the generalized circuit in Figure 3, and applying an
alternating bit pattern of O’s and 1’s at the known mark
and space frequencies. By adjusting R0, the VCO can
then be tuned to obtain a 50% duty cycle on the FSK
output (pin 7). This will ensure that the VCO fO value is
accurately referenced to the mark and space frequencies.
Reference Voltage, VREF (Pin 10): This pin is internally
biased at the reference voltage level, VREF: VREF = VCC /2
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at pins 5, 8, 11 and 12. Pin
Rev. 3.01
6
XR-2211
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Loop
Filter
Data
Filter
FSK
Output
φ Det
FSK
Comp
φ
VCO
Input
Preamp
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
φ
φ Det
Lock Detect
Filter
ÎÎ
ÎÎ
ÎÎÎ
ÎÎ
Lock Detect
Outputs
Lock Detect
Comp
Figure 2. Functional Block Diagram of a Tone and FSK
Decoding System Using XR-2211
VCC
RB
Loop
Phase
Detect
2
Input
Signal
11
RF
Rl
8
7
+
C1
CF
10
R1
12
VCO
FSK
Comp.
Internal
Reference
0.1mF
0.1mF
14
13
R0
6
C0
+
Quad
Phase
Detect
LDOQ
LDOQN
3
RD
Lock
Detect
Comp.
CD
Figure 3. Generalized Circuit Connection for
FSK and Tone Detection
Rev. 3.01
7
5
XR-2211
DESIGN EQUATIONS
(All resistance in W, all frequency in Hz and all capacitance in farads, unless otherwise specified)
(See Figure 3 for definition of components)
1. VCO Center Frequency, fO:
fO +
1
R 0·C 0
2. Internal Reference Voltage, VREF (measured at pin 10):
V REF +
ǒV2 Ǔ–650mV in volts
CC
3. Loop Low-Pass Filter Time Constant, t:
t + C 1·R PP (seconds)
where:
R PP +
ǒRR)·RR Ǔ
1
F
1
F
if RF is 1 or CF reactance is 1, then RPP = R1
4. Loop Damping, j:
z+
Ǹǒ
1250·C 0
R 1·C 1
Ǔ
Note: For derivation/explanation of this equation, please see TAN-011.
5. Loop-tracking
Df
bandwidth, "+ f
0
Df + R 0
R1
f0
Tracking
Bandwidth
Df
fLL
f1
Df
fO
f2
fLH
Rev. 3.01
8
XR-2211
6. FSK Data filter time constant, tF:
tF +
RB · RF
·C (seconds)
( R B ) R F) F
7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 10 and pin11, per unit of
phase error at phase detector input):
Kd +
ƪ
ƫ
V REF · R 1 volt
10, 000·p radian
Note: For derivation/explanation of this equation, please see TAN-011.
8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin 11):
K0 +
–2p
+
V REF ·C 0 · R 1
ńsecond
ǒradianvolt
Ǔ
9. The filter transfer function:
F(s) +
1
at 0 Hz.
1 ) SR 1·C 1
S = Jw and w = 0
10. Total loop gain. KT:
K T + K O·K d·F(s) +
1
ƫ
ǒ5, 000·C R·(R ) R )Ǔƪseconds
F
0
1
F
11. Peak detector current IA:
IA +
V REF
(V REF in volts and I A in amps)
20, 000
Note: For derivation/explanation of this equation, please see TAN-011.
Rev. 3.01
9
XR-2211
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 10, the functions
of external components are defined as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth,
and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a one-pole post-detection filter for
the FSK data output. The resistor RB from pin 7 to pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
Design Instructions:
The circuit of Figure 10 can be tailored for any FSK decoding application by the choice of five key circuit components: R0,
R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, fO and f1, these parameters can be calculated as
follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Calculate PLL center frequency, fO:
f O + ǸF 1·F 2
b) Choose value of timing resistor R0, to be in the range of 10KW to 100KW. This choice is arbitrary. The recommended
value is R0 = 20KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX.
RO + RO )
RX
2
c) Calculate value of C0 from design equation (1) or from Figure 7:
CO +
1
R0 · f0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R1 +
R 0·f 0
·2
(f 1–f 2)
e) Calculate C1 to set loop damping. (See design equation 4):
Normally, j = 0.5 is recommended.
C1 +
1250·C 0
R1 · j2
Rev. 3.01
10
XR-2211
f)
The input to the XR-2211 may sometimes be too sensitive to noise conditions on the input line. Figure 4 illustrates
a method of de-sensitizing the XR-2211 from such noisy line conditions by the use of a resistor, Rx, connected
from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level.
V IN minimum (peak) + V a–V b + DV " 2.8mV offset + V REF
ǒ
V
20, 000
or R X + 20, 000 REF –1
(20, 000 ) R X)
DV
Ǔ
VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold)
VCC
Input
ÎÎ
To Phase
Detector
Va
Vb
2
20K
Rx
20K
ÎÎ
ÎÎ
VREF 10
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, CF:
R sum +
CF +
(R F ) R 1)·R B
( R 1 ) R F ) R B)
0.25
(R sum·Baud Rate)
Baud rate in
1
seconds
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
11
XR-2211
1.0
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
R0=5KW
15
R0=10KW
R0=5KΩ
C0( mF)
Supply vs. Current (mA)
20
10
0.1
R0=10KΩ
R0=20KW
R0=40KW
5
R0=80KW
R0>100K
R0=160KW
0
4
6
8 10
12 14 16
Supply Voltage,
0.01
100
18 20 22 24
1000
fO(HZ)
V+ (Volts)
Figure 5. Typical Supply Current vs. V+
(Logic Outputs Open Circuited)
10000
Figure 6. VCO Frequency vs. Timing Resistor
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
1,000
C0=0.001mF
Normalized Frequency
1.02
R0(KW )
C0=0.0033mF
100
C0=0.01mF
C0=0.1mF
C0=0.0331mF
10
1000
4
4
2
0.98
1
0.97
4
6
8
10
fO(Hz)
Normalized Frequency Drift (% of f O)
12
14
Figure 8. Typical fO vs. Power Supply
Characteristics
+1.0
1MΩ
R0=10K
+0.5
500K
R0=50K
50K
R0=500K
10K
V+ = 12V
R1 = 10 R0
fO = 1 kHz
R0=1MΩ
-1.0
-50
-25
0
R0
Curve
5K
1
10K
2
30K
3
100K
4
300K
5
16 18
20 22
V+ (Volts)
-0.5
25
50
75
100
125
Temperature (°C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 3.01
12
3
3
0.99
Figure 7. VCO Frequency vs. Timing Capacitor
5
2
10000
0
1
1.00
C0=0.33mF
0
fO = 1kHz
RF = 10R0
5
1.01
24
XR-2211
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.
Step 1: Calculate fO: from design instructions
(a) f O + Ǹ1200·2200 =1624
Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K. (See design instructions (b))
ǒ Ǔ
(b) R T + 10 ) 10 + 15K
2
Step 3: Calculate C0 from design instructions
(c) C O +
1
+ 39nF
15000·1624
Step 4: Calculate R1 : from design instructions
(d) R 1 + 20000·1624·2 + 51, 000
(2200–1200)
Step 5: Calculate C1 : from design instructions
(e) C 1 + 1250·39nF2 + 3.9nF
51000·0.5
Step 6: Calculate RF : RF should be at least five times R1, RF = 51,000⋅5 = 255 KW
Step 7: Calculate RB : RB should be at least five times RF, RB = 255,000⋅5 = 1.2 MW
Step 8: Calculate RSUM :
R SUM +
(R F ) R 1)·R B
+ 240KW
(R F ) R 1 ) R B )
Step 9: Calculate CF :
CF +
0.25
+ 1nF
ǒ R SUM·Baud Rate Ǔ
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
13
XR-2211
VCC
RB
11
Loop
Phase
Detect
13
14
27nF
CO
8
1.8m
5%
Rx
20K
RL
5.1K
5%
5%
7
CF
10%
Data
Output
FSK
Comp.
R1
35.2K
10
1%
0.1µF
R0
20K
1%
12
VCO
0.1µF
5%
1nF
C1
2.7nF
5%
2
Input
Signal
RF 178K
Internal
Reference
VCO
Fine
Tune
6
LDOQ
+
Quad
Phase
Detect
LDOQN
Lock
Detect
Comp.
5
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals
(Bell 202 Format)
VCC
RB
11
Loop
Phase
Detect
2
Input
Signal
0.1µF
RF
14
7
+
C1
VCO
8
CF
R1
12
10
0.1µF
13
RL
5.1k
FSK
Comp.
Internal
Reference
R0
C0
Rx
6 LDOQ
Quad
Phase
Detect
3
RD
CD
Lock
Detect
Comp.
5 LDOQN
Between 400K and 600K
Figure 11. External Connectors for FSK Demodulation with Carrier
Detect Capability
Rev. 3.01
14
XR-2211
VCC
Loop
Phase
Detect
8
11
12
2
VCO
0.1µF
14
FSK
Comp.
R1
200K
10
1%
0.1µF
Internal
Reference
R0
20K
1%
13
C0 5%
50nF
Tone
Input
7
+
C1
220pF
5%
Rx
5K
VCC
VCO
Fine
Tune
6 LDOQ
+
Quad
Phase
Detect
RL2
5.1K
RL3
5.1K
Logic Output
5 LDOQN
3
CD
80nF
RD
470K
Lock
Detect
Comp.
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect
frequency approaches the capture bandwidth.
Excessively large values of CD will slow the response time
of the lock detect output. For Caller I.D. applications
choose CD = 0.1mF.
The lock detect section of XR-2211 can be used as a
carrier detect option for FSK decoding.
The
recommended circuit connection for this application is
shown in Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “low” state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
Tone Detection
Figure 12 shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at “high” and “low” logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Note: Data Output is “Low” When No Carrier is Present.
The minimum value of the lock detect filter capacitance
CD is inversely proportional to the capture range, +Dfc.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C1. For most applications, Dfc
> Df/2. For RD = 470KW, the approximate minimum value
of CD can be determined by:
Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors RL2 and
RL3, as shown in Figure 12.
C D § 16 C in mF and f in Hz.
Df
With reference to Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
follows: R0 and C0 set VCO center frequency; R1 sets the
detection bandwidth; C1 sets the low pass-loop filter time
constant and the loop damping factor.
C in mF and f in Hz.
With values of CD that are too small, chatter can be
observed on the lock detect output as an incoming signal
Rev. 3.01
15
XR-2211
Design Instructions:
The circuit of Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components:
R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these parameters are calculated as follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 7 fS = fO:
CO +
1
R 0·fs
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0·f 0·2
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C1 for a given loop damping factor:
Normally, j = 0.5 is recommended.
C1 +
1250·C 0
R 1·j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D § 16
Df
C in mF
Increasing CD slows down the logic output response time.
Design Examples:
Tone detector with a detection band of + 100Hz:
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20 KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 6 fS = fO:
C0 +
1 +
1
+ 50nF
20, 000·1, 000
R 0·f S
Rev. 3.01
16
XR-2211
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0·f O·2
20, 000·1, 000·2
+
+ 400K
100
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C0 for a given loop damping factor:
Normally, j = 0.5 is recommended.
C1 +
–9
1250·C 0
+ 1250·50·10 2 + 6.25pF
400, 000·0.5
R 1·j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D + 16 w 16 w 80nF
200
Df
Increasing CD slows down the logic output response time.
f)
Fine tune center frequency with 5KW potentiometer, RX.
VCC
VCC
RF
0.1µF
100K
Loop
Phase
Detect
2
0.1µF
FM
Input
3
8
11
7
+
C1
12
VCO
14
13
R1
CF
FSK
Comp
.
Internal
Reference
10
0.1µF
4
+
1
2
11
LM324
R0
6
C0
LDOQ
+
Quad
Phase
Detect
LDOQN
Lock
Detect
Comp.
5
Figure 13. Linear FM Detector Using XR-2211 and an External Op Amp.
(See Section on Design Equation for Component Values.)
Rev. 3.01
17
Demodulated
Output
XR-2211
Linear FM Detection
XR-2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry
applications. The recommended circuit connection for
this application is shown in Figure 13. The demodulated
output is taken from the loop phase detector output (pin
11), through a post-detection filter made up of RF and CF,
and an external buffer amplifier. This buffer amplifier is
necessary because of the high impedance output at pin
11. Normally, a non-inverting unity gain op amp can be
used as a buffer amplifier, as shown in Figure 13.
The FM detector gain, i.e., the output voltage change per
unit of FM deviation can be given as:
V OUT +
R 1·V REF
100·R 0
where VR is the internal reference voltage (VREF = VCC /2
- 650mV). For the choice of external components R1, R0,
CD, C1 and CF, see the section on design equations.
V+
1
REF
Voltage
Output
20K
Input
2
10
Lock
Detect
Filter
B
10K
10K
From
VCO
B’
3
6
Lock Detect
Outputs
20K
5
Internal Voltage
Reference
2K
Input Preamplifier
and Limiter
Lock Detect
Comparator
Quadrature
Phase Detector
2K
8
A
Timing
Capacitor
A’
13 C0 14
B’
B
11
A
From
VCO
A’
FSK
Comparator
Loop
Input
Detector
Output
7
FSK
Data
Output
4
12
R0 Timing
Resistor
8K
Ground
Voltage Controlled
Oscillator
Loop Phase Detector
Figure 14. Equivalent Schematic Diagram
Rev. 3.01
18
FSK Comparator
XR-2211
14 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
14
8
1
7
E
E1
D
A1
Base
Plane
Seating
Plane
A
L
e
c
B
α
B1
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.100
0.200
2.54
5.08
A1
0.015
0.060
0.38
1.52
B
0.014
0.026
0.36
0.66
B1
0.045
0.065
1.14
1.65
c
0.008
0.018
0.20
0.46
D
0.685
0.785
17.40
19.94
E1
0.250
0.310
6.35
7.87
E
0.300 BSC
7.62 BSC
e
0.100 BSC
2.54 BSC
L
0.125
0.200
3.18
5.08
α
0°
15°
0°
Note: The control dimension is the inch column
15°
Rev. 3.01
19
XR-2211
14 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
14
8
1
7
E1
E
D
Seating
Plane
A2
A
L
α
A1
B
INCHES
SYMBOL
MIN
eA
eB
B1
e
MAX
MILLIMETERS
MIN
MAX
A
0.145
0.210
3.68
5.33
A1
0.015
0.070
0.38
1.78
A2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.725
0.795
18.42
20.19
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 3.01
20
C
XR-2211
14 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
14
8
E
H
1
7
C
A
Seating
Plane
α
e
B
A1
L
INCHES
SYMBOL
MIN
MAX
MILLIMETERS
MIN
MAX
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.337
0.344
8.55
8.75
E
0.150
0.157
3.80
4.00
e
0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
α
0°
8°
0°
Note: The control dimension is the millimeter column
Rev. 3.01
21
8°
XR-2211
Notes
Rev. 3.01
22
XR-2211
Notes
Rev. 3.01
23
XR-2211
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1995 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.01
24
LM555
Timer
General Description
Features
The LM555 is a highly stable device for generating accurate
time delays or oscillation. Additional terminals are provided
for triggering or resetting if desired. In the time delay mode of
operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator,
the free running frequency and duty cycle are accurately
controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms, and
the output circuit can source or sink up to 200mA or drive
TTL circuits.
n
n
n
n
n
n
n
n
n
Direct replacement for SE555/NE555
Timing from microseconds through hours
Operates in both astable and monostable modes
Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TTL compatible
Temperature stability better than 0.005% per ˚C
Normally on and normally off output
Available in 8-pin MSOP package
Applications
n
n
n
n
n
n
n
Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator
Schematic Diagram
DS007851-1
© 2000 National Semiconductor Corporation
DS007851
www.national.com
LM555 Timer
February 2000
LM555
Connection Diagram
Dual-In-Line, Small Outline
and Molded Mini Small Outline Packages
DS007851-3
Top View
Ordering Information
Package
8-Pin SOIC
8-Pin MSOP
8-Pin MDIP
www.national.com
Part Number
Package Marking
Media Transport
LM555CM
LM555CM
Rails
LM555CMX
LM555CM
2.5k Units Tape and Reel
LM555CMM
Z55
1k Units Tape and Reel
LM555CMMX
Z55
3.5k Units Tape and Reel
LM555CN
LM555CN
Rails
2
NSC Drawing
M08A
MUA08A
N08E
Soldering Information
Dual-In-Line Package
Soldering (10 Seconds)
260˚C
Small Outline Packages
(SOIC and MSOP)
Vapor Phase (60 Seconds)
215˚C
Infrared (15 Seconds)
220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Power Dissi
Dengan meningkatnya kebutuhan jalur komunikasi data, khususnya pada
komunikasi dengan bandwidth rendah, PLC menjadi metode alternatif untuk
komunikasi sinyal kendali. Sistem PLC dalam Tugas Akhir ini telah dirancang
dan direalisasi dengan menggunakan modulasi FSK sebagai physical layer, dan
menggunakan protokol komunikasi UART. Sebagai pengendali digunakan
mikrokontroler MCS51. Sistem PLC pada Tugas Akhir ini dibuat dengan
konfigurasi satu master dua slave.
Sistem PLC yang telah dibuat diimplementasikan sebagai pengandali on
off dengan jumlah output yang dikendalikan sebanyak 48 output. Dari pengujian
yang telah dilakukan didapatkan kesimpulan bahwa sistem ini dapat bekerja
dengan baik dengan sensitivitas sinyal data sebesar 10 mVpp dan dengan
ketahanan terhadap noise sampai dengan 200 mVpp.
i
ABSTRACT
Within increasing demand in data communication line, especially in
narrow band communication, PLC can be alternative for control signal
communication. PLC system for this final project use FSK modulation as physical
layer, and use UART as communication protocol. Microcontroller MCS51 used
as controller. PLC system in this task uses one master two slave configuration.
This PLC system has been implemented as on off control with 48 outputs.
From the test has been held, these systems can work excellent with 10 mV pp data
signal sensitivity, and noise resistant up to 200 mV pp .
ii
DAFTAR ISI
Halaman
ABSTRAK ...................................................................................................
i
ABSTRACT .................................................................................................
ii
KATA PENGANTAR ................................................................................. iii
DAFTAR ISI ................................................................................................
v
DAFTAR GAMBAR .................................................................................... viii
DAFTAR TABEL ........................................................................................
x
BAB I PENDAHULUAN
I.1
Latar Belakang .................................................................................
1
I.2
Perumusan Masalah .........................................................................
2
I.3
Tujuan ..............................................................................................
2
I.4
Pembatasan Masalah ........................................................................
2
I.5
Alat yang digunakan ........................................................................
2
I.6
Sistematika Pembahasan ..................................................................
2
BAB II TEORI PENUNJANG
II.1 UART (Universal Asynchronous Receive/Transmit) .....................
4
II.2 Modulasi FSK (Frequency Shift Keying) ........................................
5
II.2.1
Modulasi Langsung ....................................................
6
II.2.2
Modulasi dengan FractionalN Synthesizer ..........….
8
II.3 Demodulator FSK Exar XR2211....................................................
9
II.4 LPF (Low Pass Filter) ……............................................................. 13
II.5 BPF (Band Pass Filter) ……........................................................... 14
II.6 Rangkaian Dasar Mikrokontroler …................................................ 15
II.7 Rele ………...………….................................................................. 16
v
BAB III PERANCANGAN
III.1 Perancangan Dan Realisasi LPF ...................................................
19
III.2 Perancangan Dan Realisasi BPF ....................................................
21
III.3 Perancangan Dan Realisasi Modulator FSK ..................................
22
III.4 Perancangan Dan Realisasi Demodulator FSK .............................. 23
III.5 Perancangan Dan Realisasi Rangkaian Mikrokontroler ................
25
III.5.1
Rangkaian Mikrokontroler Master ............................ 25
III.5.2
Rangkaian Mikrokontroler Slave ............................... 26
III.6 Penggabungan Modul – Modul PLC Master Controller ................ 27
III.7 Penggabungan Modul – Modul PLC Slave Controller ................... 28
III.8 Perancangan Dan Realisasi Program Mikrokontroler ..................... 28
BAB IV UJI COBA ALAT
IV.1 Karakteristik LPF ............................................................................ 34
IV.2 Karakteristik BPF ............................................................................ 35
IV.3 Karakteristik Modulator FSK .......................................................... 35
IV.4 Karakteristik Demodulator FSK ...................................................... 36
IV.5 Karakteristik Sinyal FSK Di Jalur Listrik DC ................................. 37
IV.6 Karakteristik Noise Di Jalur Listrik DC .......................................... 38
IV.7 Pengujian Sistem PLC ..................................................................... 38
BAB V KESIMPULAN DAN SARAN
V.1 Kesimpulan ....................................................................................
40
V.2 Saran ..............................................................................................
40
DAFTAR PUSTAKA .................................................................................
xi
vi
LAMPIRAN
Lampiran A
Listing Program Mikrokontroler Master .......................................
A1
Listing Program Mikrokontroler Slave A ......................................
A6
Listing Program Mikrokontroler Slave B ......................................
A10
Lampiran B
Rangkaian Keseluruhan Sistem PLC ........................................... B1
Layout PCB Mikrokontroler Master ............................................ B2
Layout PCB Mikrokontroler Slave ............................................... B3
Layout PCB FSK modulator ......................................................... B4
Layout PCB FSK demodulator ..................................................... B4
Lampiran C
IC LM 555 .................................................................................... C1
IC Exar XR 2211 ........................................................................ C11
Lampiran D
Foto alat ........................................................................................ D1
vii
DAFTAR GAMBAR
Halaman
1. Gambar II1 Timing diagram UART .................................................
5
2. Gambar II2 Spektrum frekuensi FSK ................................................
5
3. Gambar II3 Sinyal FSK .....................................................................
6
4. Gambar II4 Modulasi langsung dengan VCO ..................................
7
5. Gambar II5 IC 555 sebagai FSK modulator .....................................
7
6. Gambar II6 FractionalN Synthesizer ..............................................
8
7. Gambar II7 FSK demodulator ..........................................................
9
8. Gambar II8 Tracking Frequency .......................................................
11
9. Gambar II9 Low pass filter.................................................................
13
10. Gambar II10 High pass filter..............................................................
14
11. Gambar II11 Diagram Blok mikrokontroler AT89S52 .....................
15
12. Gambar II12 Rangkaian dasar mikrokontroler AT89S52 ................
16
13. Gambar II13 SPST (Single Pole Single Throw) ...............................
17
14. Gambar II14 SPDT (Single Pole Double Throw) ..............................
17
15. Gambar II15 DPST (Double Pole Single Throw) ..............................
18
16. Gambar II16 DPDT (Double Pole Double Throw) ...........................
18
17. Gambar III1 Blok diagram PLC .......................................................
19
18. Gambar III2 Low Pass Filter..............................................................
20
19. Gambar III3 High Pass Filter ............................................................
21
20. Gambar III4 Voltage Controlled Oscillator dengan IC 555 .............
23
21. Gambar III5 FSK Demodulator.........................................................
25
22. Gambar III6 Master Controller .........................................................
26
23. Gambar III7 Slave Controller ............................................................
27
24. Gambar III8 Master PLC controller .................................................
27
25. Gambar III9 Slave PLC controller ...................................................
28
26. Gambar III10 Flowchart program master controller ........................
29
27. Gambar III11 Flowchart program slave controller ...........................
29
28. Gambar III12 SFR Timer Mode.........................................................
30
29. Gambar III13 initialisasi TMOD......................................................
30
viii
30. Gambar III14 SFR Serial Port Control...........................................
31
31. Gambar III15Frame data ...............................................................
33
32. Gambar IV1 Karakteristik LPF (logaritmis)...................................
34
33. Gambar IV2 Karakteristik BPF (logaritmis)...................................
35
34. Gambar IV3 Respon PLL demodulator FSK..................................
35
35. Gambar IV4 Pemasangan beban di jalur listrik DC........................
35
ix
DAFTAR TABEL
Halaman
1. Tabel III1 SFR serial mode...............................................................
32
2. Tabel IV1 Karakteristik LPF (Low Pass Filter) ...............................
34
3. Tabel IV2 Karakteristik BPF (Band Pass Filter) ..............................
35
4. Tabel IV3 Karakteristik modulator FSK ...........................................
35
5. Tabel IV4 Karakteristik FSK demodulator terhadap frekuensi .........
36
6. Tabel IV5 Karakteristik demodulator FSK terhadap tegangan .........
37
7. Tabel IV6 Karakteristik sinyal FSK Di Jalur Listrik DC terhadap
beban terpasang ....................................................................................
37
8. Tabel IV7 Karakteristik sinyal FSK Di Beban terhadap
beban terpasang ....................................................................................
38
9. Tabel IV8 Karakteristik noise di jalur listrik DC ...............................
38
10. Tabel IV9 Pengujian Sistem PLC ......................................................
39
x
LAMPIRAN A
Listing Program PLC Controller
Lampiran
Listing program master controller
$mod51
CALL INIT
LAGI:
MOV A,P1
MOV R5,A
MOV P0,#11111110B
JB P0.4,NO2
MOV R0,#01H
NO2:
JB P0.5,NO3
MOV R0,#03H
NO3:
JB P0.6,NOA
MOV R0,#05H
NOA:
JB P0.7,NO4
MOV A,R5
ANL A,#0FH
ADD A,#0F0H
MOV R4,A
MOV A,R0
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
CALL DELAY
A 1
Lampiran
MOV A,R5
ANL A,#0F0H
RL A
RL A
RL A
RL A
ADD A,#0F0H
MOV R4,A
MOV A,R0
INC A
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
NO4:
MOV P0,#11111101B
JB P0.4,NO5
MOV R0,#07H
NO5:
JB P0.5,NO6
MOV R0,#09H
NO6:
JB P0.6,NOB
MOV R0,#0BH
NOB:
JB P0.7,NO7
NO7:
A 2
Lampiran
MOV P0,#11111011B
JB P0.4,NO8
NO8:
MOV R0,#0DH
JB P0.5,NO9
NO9:
MOV R0,#0FH
JB P0.6,NOC
NOC:
JB P0.7,NOSTARR
NOSTARR:
MOV P0,#11110111B
JB P0.4,NO0
MOV R4,#0F0H
MOV A,R0
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
CALL DELAY
MOV R4,#0F0H
MOV A,R0
INC A
RR A
RR A
RR A
RR A
A 3
Lampiran
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
NO0:
JB P0.5,NOKRESS
NOKRESS:
JB P0.6,NOD
MOV R4,#0FFH
MOV A,R0
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
CALL DELAY
MOV R4,#0FFH
MOV A,R0
INC A
RR A
RR A
RR A
RR A
ADD A,#0FH
ANL A,R4
MOV P2,A
CALL KIRIM
NOD:
A 4
Lampiran
JB P0.7,NON
NON:
LJMP LAGI
INIT:
MOV P0,#00H
MOV P1,#00H
MOV P2,#00H
MOV SP, #30H
MOV SCON, #50H
;inisialisasi baud rate (9600 bps)
MOV TMOD, #20H
MOV TL1, #0FDH
MOV TH1, #0FDH
MOV PCON, #00H
SETB TR1
RET
KIRIM:
CLR TI
MOV SBUF,A
JNB TI,$
RET
DELAY:
DLY0:
MOV R6,#0FFH
DLY1:
DJNZ R6,DLY1
RET
END
A 5
Lampiran
Listing program slave controler
SLAVE A
$mod51
MOV R0,#00H
MOV R1,#00H
MOV R2,#00H
MOV R3,#00H
MOV R4,#00H
MOV R5,#00H
MOV R6,#00H
MOV R7,#00H
MOV P0,00H
MOV P1,00H
MOV P2,00H
LJMP START
TERIMA:
JNB
RI,$
MOV A,SBUF
MOV R1,A
CLR RI
MOV A,#11110000B
ANL A,R1
MOV R2,A
MOV A,#00001111B
ANL A,R1
MOV R3,A
RR A
RR A
RR A
RR A
MOV R4,A
A 6
Lampiran
RETI
START:
MOV SP, #30H
MOV SCON, #50H
;inisialisasi baud rate (9600 bps)
MOV TMOD, #20H
MOV TL1, #0FDH
MOV TH1, #0FDH
MOV PCON, #00H
SETB TR1
ULANG:
CALL TERIMA
CJNE R2,#10H,ADDB
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R3
MOV P0,A
ADDB:
CJNE R2,#20H,ADDCO
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R4
MOV P0,A
ADDCO:
CJNE R2,#30H,ADDD
MOV A,R3
A 7
Lampiran
ORL A,#0F0H
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R3
MOV P1,A
ADDD:
CJNE R2,#40H,ADDE
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R4
MOV P1,A
ADDE:
CJNE R2,#50H,ADDF
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P2
ANL A,R5
ORL A,R3
MOV P2,A
ADDF:
CJNE R2,#60H,ADDG
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P2
ANL A,R5
A 8
Lampiran
ORL A,R4
MOV P2,A
ADDG:
LJMP ULANG:
DELAY:
MOV R0,#0FH
DLY1:
MOV R1,#0FFH
DLY0:
DJNZ R1,DLY0
DJNZ R0,DLY1
END
A 9
Lampiran
SLAVE B
$mod51
MOV R0,#00H
MOV R1,#00H
MOV R2,#00H
MOV R3,#00H
MOV R4,#00H
MOV R5,#00H
MOV R6,#00H
MOV R7,#00H
MOV P0,00H
MOV P1,00H
MOV P2,00H
LJMP START
TERIMA:
JNB
RI,$
MOV A,SBUF
MOV R1,A
CLR RI
MOV A,#11110000B
ANL A,R1
MOV R2,A
MOV A,#00001111B
ANL A,R1
MOV R3,A
RR A
RR A
RR A
RR A
MOV R4,A
RETI
A 10
Lampiran
START:
MOV SP, #30H
MOV SCON, #50H
;inisialisasi baud rate (9600 bps)
MOV TMOD, #20H
MOV TL1, #0FDH
MOV TH1, #0FDH
MOV PCON, #00H
SETB TR1
ULANG:
CALL TERIMA
CJNE R2,#70H,ADDB
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R3
MOV P0,A
ADDB:
CJNE R2,#80H,ADDCO
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P0
ANL A,R5
ORL A,R4
MOV P0,A
ADDCO:
CJNE R2,#90H,ADDD
MOV A,R3
ORL A,#0F0H
A 11
Lampiran
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R3
MOV P1,A
ADDD:
CJNE R2,#A0H,ADDE
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P1
ANL A,R5
ORL A,R4
MOV P1,A
ADDE:
CJNE R2,#B0H,ADDF
MOV A,R3
ORL A,#0F0H
MOV R5,A
MOV A,P2
ANL A,R5
ORL A,R3
MOV P2,A
ADDF:
CJNE R2,#C0H,ADDG
MOV A,R4
ORL A,#0FH
MOV R5,A
MOV A,P2
ANL A,R5
ORL A,R4
A 12
Lampiran
MOV P2,A
ADDG:
LJMP ULANG:
DELAY:
MOV R0,#0FH
DLY1:
MOV R1,#0FFH
DLY0:
DJNZ R1,DLY0
DJNZ R0,DLY1
END
A 13
Lampiran
LAMPIRAN B
Rangkaian Dan PCB
A 14
Lampiran
100 nF
12 V
.615 mH
Jalur Listrik DC
Skema Keseluruhan Sistem PLC
A 15
Lampiran
PCB MASTER CONTROLLER
PCB Bottom
PCB Layout
A 16
Lampiran
PCB SLAVE CONTROLLER
PCB Bottom
PCB Layout
A 17
Lampiran
PCB FSK MODULATOR
PCB FSK DEMODULATOR
A 18
Lampiran
A 19
XR-2211
...the analog plus
FSK Demodulator/
Tone Decoder
company TM
June 1997-3
APPLICATIONS
FEATURES
D Wide Frequency Range, 0.01Hz to 300kHz
D Caller Identification Delivery
D Wide Supply Voltage Range, 4.5V to 20V
D FSK Demodulation
D HCMOS/TTL/Logic Compatibility
D Data Synchronization
D FSK Demodulation, with Carrier Detection
D Wide Dynamic Range, 10mV to 3V rms
D Tone Decoding
D Adjustable Tracking Range, +1% to 80%
D FM Detection
D Excellent Temp. Stability, +50ppm/°C, max.
D Carrier Detection
GENERAL DESCRIPTION
quadrature phase detector which provides carrier
detection, and an FSK voltage comparator which provides
FSK demodulation. External components are used to
independently set center frequency, bandwidth, and output
delay. An internal voltage reference proportional to the
power supply is provided at an output pin.
The XR-2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications
applications. It is particularly suited for FSK modem
applications. It operates over a wide supply voltage range
of 4.5 to 20V and a wide frequency range of 0.01Hz to
300kHz. It can accommodate analog signals between
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal within the pass band, a
The XR-2211 is available in 14 pin packages specified for
military and industrial temperature ranges.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XR-2211M
14 Pin CDIP (0.300”)
-55°C to +125°C
XR-2211N
14 Pin CDIP (0.300”)
-40°C to +85°C
XR-2211P
14 Pin PDIP (0.300”)
-40°C to +85°C
XR-2211ID
14 Lead SOIC (Jedec, 0.150”)
-40°C to +85°C
Rev. 3.01
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-2211
BLOCK DIAGRAM
VCC
GND
NC
1
4
9
Pre Amplifier
INP
TIM C1
2
Loop
q-Det
14
Lock
Detect
Comparator
VCO
TIM C2
13
TIM R
12
Quad
q-Det
11
LDO
3
LDF
6
LDOQ
5
LDOQN
7
DO
Internal
VREF
10
VREF
FSK Comp
Reference
COMP I
8
Figure 1. XR-2211 Block Diagram
Rev. 3.01
2
XR-2211
PIN CONFIGURATION
VCC
INP
LDF
GND
LDOQN
LDOQ
DO
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
INP
LDF
GND
LDOQN
LDOQ
DO
TIM C1
TIM C2
TIM R
LDO
VREF
NC
COMP I
14 Lead CDIP, PDIP (0.300”)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
TIM C1
TIM C2
TIM R
LDO
VREF
NC
COMP I
14 Lead SOIC (Jedec, 0.150”)
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
VCC
2
INP
I
Receive Analog Input.
3
LDF
O
Lock Detect Filter.
4
GND
5
LDOQN
O
Lock Detect Output Not. This output will be low if the VCO is in the capture range.
6
LDOQ
O
Lock Detect Output. This output will be high if the VCO is in the capture range.
7
DO
O
Data Output. Decoded FSK output.
8
COMP I
I
FSK Comparator Input.
9
NC
10
VREF
O
Internal Voltage Reference. The value of VREF is VCC/2 - 650mV.
11
LDO
O
Loop Detect Output. This output provides the result of the quadrature phase detection.
12
TIM R
I
Timing Resistor Input. This pin connects to the timing resistor of the VCO.
13
TIM C2
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14
TIM C1
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
Positive Power Supply.
Ground Pin.
Not Connected.
Rev. 3.01
3
XR-2211
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
20
V
4
7
mA
R0 > 10KW. See Figure 4.
+1
+3
%
Deviation from fO = 1/R0 C0
Temperature
+20
+50
ppm/°C
Power Supply
0.05
0.5
%/V
VCC = 12 +1V. See Figure 7.
0.2
%/V
VCC = + 5V. See Figure 7.
300
kHz
R0 = 8.2KW, C0 = 400pF
0.01
Hz
R0 = 2MW, C0 = 50mF
2000
KW
General
Supply Voltage
4.5
Supply Current
Oscillator Section
Frequency Accuracy
Frequency Stability
Upper Frequency Limit
100
Lowest Practical Operating
Frequency
See Figure 8.
Timing Resistor, R0 - See
Figure 5
Operating Range
5
Recommended Range
5
KW
See Figure 7 and Figure 8.
mA
Measured at Pin 11
Loop Phase Dectector Section
Peak Output Current
+150
+200
+300
Output Offset Current
1
mA
Output Impedance
1
MW
+5
V
Maximum Swing
+4
Quadrature Phase Detector
Peak Output Current
Measured at Pin 3
100
300
mA
Output Impedance
1
MW
Maximum Swing
11
VPP
Input Preampt Section
Input Impedance
Referenced to Pin 10
Measured at Pin 2
20
KW
Input Signal
Voltage Required to
Cause Limiting
2
10
mV rms
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 3.01
4
XR-2211
DC ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
2
MW
Measured at Pins 3 and 8
100
nA
70
dB
RL = 5.1KW
Voltage Comparator Section
Input Impedance
Input Bias Current
Voltage Gain
55
Output Voltage Low
300
500
mV
IC = 3mA
Output Leakage Current
0.01
10
mA
VO = 20V
5.3
5.7
V
Measured at Pin 10
AC Small Signal
Internal Reference
Voltage Level
4.9
Output Impedance
100
W
Maximum Source Current
80
mA
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW
Package Power Dissipation Ratings
CDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 8mW/°C
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mW
Derate Above TA = 25°C . . . . . . . . . . . . . . 60mW/°C
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 5mW/°C
SYSTEM DESCRIPTION
The main PLL within the XR-2211 is constructed from an
input preamplifier, analog multiplier used as a phase
detector and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that
input signals above typically 10mV rms are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a
current controlled oscillator with its normal input current
(fO) set by a resistor (R0) to ground and its driving current
with a resistor (R1) from the phase detector.
(internally connected). When in lock, these frequencies
are fIN+ fVCO (2 times fIN when in lock) and fIN - fVCO (0Hz
when lock). By adding a capacitor to the phase detector
output, the 2 times fIN component is reduced, leaving a
DC voltage that represents the phase difference between
the two frequencies. This closes the loop and allows the
VCO to track the input frequency.
The FSK comparator is used to determine if the VCO is
driven above or below the center frequency (FSK
comparator). This will produce both active high and
active low outputs to indicate when the main PLL is in lock
(quadrature phase detector and lock detector
comparator).
The output of the phase detector produces sum and
difference of the input and the VCO frequencies
Rev. 3.01
5
XR-2211
PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this
terminal. The internal impedance at pin 2 is 20KW.
Recommended input signal level is in the range of 10mV
rms to 3V rms.
10 must be bypassed to ground with a 0.1mF capacitor for
proper operation of the circuit.
Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 3.) With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VREF. The peak to peak voltage swing
available at the phase detector output is equal to 2 x VREF.
Quadrature Phase Detector Output (Pin 3): This is the
high impedance output of quadrature phase detector and
is internally connected to the input of lock detect voltage
comparator. In tone detection applications, pin 3 is
connected to ground through a parallel combination of RD
and CD (see Figure 3) to eliminate the chatter at lock
detect outputs. If the tone detect section is not used, pin 3
can be left open.
VCO Control Input (Pin 12): VCO free-running
frequency is determined by external timing resistor, R0,
connected from this terminal to ground. The VCO
free-running frequency, fO, is:
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
“low” state when the PLL is out of lock and goes to “high”
state when the PLL is locked. It is an open collector type
output and requires a pull-up resistor, RL, to VCC for
proper operation. At “low” state, it can sink up to 5mA of
load current.
fO +
1
Hz
R 0·C 0
where C0 is the timing capacitor across pins 13 and 14.
For optimum temperature stability, R0 must be in the
range of 10KW to 100KW (see Figure 9.)
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6.
This output is also an open collector type stage which can
sink 5mA of load current at low or “on” state.
This terminal is a low impedance point, and is internally
biased at a DC level equal to VREF. The maximum timing
current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, RL, to VCC for
proper operation. It can sink 5mA of load current. When
decoding FSK signals, FSK data output is at “high” or “off”
state for low input frequency, and at “low” or “on” state for
high input frequency. If no input signal is present, the logic
state at pin 7 is indeterminate.
VCO Timing Capacitor (Pins 13 and 14): VCO
frequency is inversely proportional to the external timing
capacitor, C0, connected across these terminals (see
Figure 6.) C0 must be non-polar, and in the range of
200pF to 10mF.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with R0 at pin 12
(see Figure 10.)
FSK Comparator Input (Pin 8): This is the high
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase
detector output (pin 11). This data filter is formed by RF
and CF (see Figure 3.) The threshold voltage of the
comparator is set by the internal reference voltage, VREF,
available at pin 10.
VCO Free-Running Frequency, fO: XR-2211 does not
have a separate VCO output terminal. Instead, the VCO
outputs are internally connected to the phase detector
sections of the circuit. For set-up or adjustment purposes,
the VCO free-running frequency can be tuned by using
the generalized circuit in Figure 3, and applying an
alternating bit pattern of O’s and 1’s at the known mark
and space frequencies. By adjusting R0, the VCO can
then be tuned to obtain a 50% duty cycle on the FSK
output (pin 7). This will ensure that the VCO fO value is
accurately referenced to the mark and space frequencies.
Reference Voltage, VREF (Pin 10): This pin is internally
biased at the reference voltage level, VREF: VREF = VCC /2
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at pins 5, 8, 11 and 12. Pin
Rev. 3.01
6
XR-2211
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Loop
Filter
Data
Filter
FSK
Output
φ Det
FSK
Comp
φ
VCO
Input
Preamp
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
φ
φ Det
Lock Detect
Filter
ÎÎ
ÎÎ
ÎÎÎ
ÎÎ
Lock Detect
Outputs
Lock Detect
Comp
Figure 2. Functional Block Diagram of a Tone and FSK
Decoding System Using XR-2211
VCC
RB
Loop
Phase
Detect
2
Input
Signal
11
RF
Rl
8
7
+
C1
CF
10
R1
12
VCO
FSK
Comp.
Internal
Reference
0.1mF
0.1mF
14
13
R0
6
C0
+
Quad
Phase
Detect
LDOQ
LDOQN
3
RD
Lock
Detect
Comp.
CD
Figure 3. Generalized Circuit Connection for
FSK and Tone Detection
Rev. 3.01
7
5
XR-2211
DESIGN EQUATIONS
(All resistance in W, all frequency in Hz and all capacitance in farads, unless otherwise specified)
(See Figure 3 for definition of components)
1. VCO Center Frequency, fO:
fO +
1
R 0·C 0
2. Internal Reference Voltage, VREF (measured at pin 10):
V REF +
ǒV2 Ǔ–650mV in volts
CC
3. Loop Low-Pass Filter Time Constant, t:
t + C 1·R PP (seconds)
where:
R PP +
ǒRR)·RR Ǔ
1
F
1
F
if RF is 1 or CF reactance is 1, then RPP = R1
4. Loop Damping, j:
z+
Ǹǒ
1250·C 0
R 1·C 1
Ǔ
Note: For derivation/explanation of this equation, please see TAN-011.
5. Loop-tracking
Df
bandwidth, "+ f
0
Df + R 0
R1
f0
Tracking
Bandwidth
Df
fLL
f1
Df
fO
f2
fLH
Rev. 3.01
8
XR-2211
6. FSK Data filter time constant, tF:
tF +
RB · RF
·C (seconds)
( R B ) R F) F
7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 10 and pin11, per unit of
phase error at phase detector input):
Kd +
ƪ
ƫ
V REF · R 1 volt
10, 000·p radian
Note: For derivation/explanation of this equation, please see TAN-011.
8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin 11):
K0 +
–2p
+
V REF ·C 0 · R 1
ńsecond
ǒradianvolt
Ǔ
9. The filter transfer function:
F(s) +
1
at 0 Hz.
1 ) SR 1·C 1
S = Jw and w = 0
10. Total loop gain. KT:
K T + K O·K d·F(s) +
1
ƫ
ǒ5, 000·C R·(R ) R )Ǔƪseconds
F
0
1
F
11. Peak detector current IA:
IA +
V REF
(V REF in volts and I A in amps)
20, 000
Note: For derivation/explanation of this equation, please see TAN-011.
Rev. 3.01
9
XR-2211
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 10, the functions
of external components are defined as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth,
and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a one-pole post-detection filter for
the FSK data output. The resistor RB from pin 7 to pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
Design Instructions:
The circuit of Figure 10 can be tailored for any FSK decoding application by the choice of five key circuit components: R0,
R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, fO and f1, these parameters can be calculated as
follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Calculate PLL center frequency, fO:
f O + ǸF 1·F 2
b) Choose value of timing resistor R0, to be in the range of 10KW to 100KW. This choice is arbitrary. The recommended
value is R0 = 20KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX.
RO + RO )
RX
2
c) Calculate value of C0 from design equation (1) or from Figure 7:
CO +
1
R0 · f0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R1 +
R 0·f 0
·2
(f 1–f 2)
e) Calculate C1 to set loop damping. (See design equation 4):
Normally, j = 0.5 is recommended.
C1 +
1250·C 0
R1 · j2
Rev. 3.01
10
XR-2211
f)
The input to the XR-2211 may sometimes be too sensitive to noise conditions on the input line. Figure 4 illustrates
a method of de-sensitizing the XR-2211 from such noisy line conditions by the use of a resistor, Rx, connected
from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level.
V IN minimum (peak) + V a–V b + DV " 2.8mV offset + V REF
ǒ
V
20, 000
or R X + 20, 000 REF –1
(20, 000 ) R X)
DV
Ǔ
VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold)
VCC
Input
ÎÎ
To Phase
Detector
Va
Vb
2
20K
Rx
20K
ÎÎ
ÎÎ
VREF 10
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, CF:
R sum +
CF +
(R F ) R 1)·R B
( R 1 ) R F ) R B)
0.25
(R sum·Baud Rate)
Baud rate in
1
seconds
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
11
XR-2211
1.0
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
R0=5KW
15
R0=10KW
R0=5KΩ
C0( mF)
Supply vs. Current (mA)
20
10
0.1
R0=10KΩ
R0=20KW
R0=40KW
5
R0=80KW
R0>100K
R0=160KW
0
4
6
8 10
12 14 16
Supply Voltage,
0.01
100
18 20 22 24
1000
fO(HZ)
V+ (Volts)
Figure 5. Typical Supply Current vs. V+
(Logic Outputs Open Circuited)
10000
Figure 6. VCO Frequency vs. Timing Resistor
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
1,000
C0=0.001mF
Normalized Frequency
1.02
R0(KW )
C0=0.0033mF
100
C0=0.01mF
C0=0.1mF
C0=0.0331mF
10
1000
4
4
2
0.98
1
0.97
4
6
8
10
fO(Hz)
Normalized Frequency Drift (% of f O)
12
14
Figure 8. Typical fO vs. Power Supply
Characteristics
+1.0
1MΩ
R0=10K
+0.5
500K
R0=50K
50K
R0=500K
10K
V+ = 12V
R1 = 10 R0
fO = 1 kHz
R0=1MΩ
-1.0
-50
-25
0
R0
Curve
5K
1
10K
2
30K
3
100K
4
300K
5
16 18
20 22
V+ (Volts)
-0.5
25
50
75
100
125
Temperature (°C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 3.01
12
3
3
0.99
Figure 7. VCO Frequency vs. Timing Capacitor
5
2
10000
0
1
1.00
C0=0.33mF
0
fO = 1kHz
RF = 10R0
5
1.01
24
XR-2211
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.
Step 1: Calculate fO: from design instructions
(a) f O + Ǹ1200·2200 =1624
Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K. (See design instructions (b))
ǒ Ǔ
(b) R T + 10 ) 10 + 15K
2
Step 3: Calculate C0 from design instructions
(c) C O +
1
+ 39nF
15000·1624
Step 4: Calculate R1 : from design instructions
(d) R 1 + 20000·1624·2 + 51, 000
(2200–1200)
Step 5: Calculate C1 : from design instructions
(e) C 1 + 1250·39nF2 + 3.9nF
51000·0.5
Step 6: Calculate RF : RF should be at least five times R1, RF = 51,000⋅5 = 255 KW
Step 7: Calculate RB : RB should be at least five times RF, RB = 255,000⋅5 = 1.2 MW
Step 8: Calculate RSUM :
R SUM +
(R F ) R 1)·R B
+ 240KW
(R F ) R 1 ) R B )
Step 9: Calculate CF :
CF +
0.25
+ 1nF
ǒ R SUM·Baud Rate Ǔ
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
13
XR-2211
VCC
RB
11
Loop
Phase
Detect
13
14
27nF
CO
8
1.8m
5%
Rx
20K
RL
5.1K
5%
5%
7
CF
10%
Data
Output
FSK
Comp.
R1
35.2K
10
1%
0.1µF
R0
20K
1%
12
VCO
0.1µF
5%
1nF
C1
2.7nF
5%
2
Input
Signal
RF 178K
Internal
Reference
VCO
Fine
Tune
6
LDOQ
+
Quad
Phase
Detect
LDOQN
Lock
Detect
Comp.
5
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals
(Bell 202 Format)
VCC
RB
11
Loop
Phase
Detect
2
Input
Signal
0.1µF
RF
14
7
+
C1
VCO
8
CF
R1
12
10
0.1µF
13
RL
5.1k
FSK
Comp.
Internal
Reference
R0
C0
Rx
6 LDOQ
Quad
Phase
Detect
3
RD
CD
Lock
Detect
Comp.
5 LDOQN
Between 400K and 600K
Figure 11. External Connectors for FSK Demodulation with Carrier
Detect Capability
Rev. 3.01
14
XR-2211
VCC
Loop
Phase
Detect
8
11
12
2
VCO
0.1µF
14
FSK
Comp.
R1
200K
10
1%
0.1µF
Internal
Reference
R0
20K
1%
13
C0 5%
50nF
Tone
Input
7
+
C1
220pF
5%
Rx
5K
VCC
VCO
Fine
Tune
6 LDOQ
+
Quad
Phase
Detect
RL2
5.1K
RL3
5.1K
Logic Output
5 LDOQN
3
CD
80nF
RD
470K
Lock
Detect
Comp.
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect
frequency approaches the capture bandwidth.
Excessively large values of CD will slow the response time
of the lock detect output. For Caller I.D. applications
choose CD = 0.1mF.
The lock detect section of XR-2211 can be used as a
carrier detect option for FSK decoding.
The
recommended circuit connection for this application is
shown in Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “low” state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
Tone Detection
Figure 12 shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at “high” and “low” logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Note: Data Output is “Low” When No Carrier is Present.
The minimum value of the lock detect filter capacitance
CD is inversely proportional to the capture range, +Dfc.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C1. For most applications, Dfc
> Df/2. For RD = 470KW, the approximate minimum value
of CD can be determined by:
Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors RL2 and
RL3, as shown in Figure 12.
C D § 16 C in mF and f in Hz.
Df
With reference to Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
follows: R0 and C0 set VCO center frequency; R1 sets the
detection bandwidth; C1 sets the low pass-loop filter time
constant and the loop damping factor.
C in mF and f in Hz.
With values of CD that are too small, chatter can be
observed on the lock detect output as an incoming signal
Rev. 3.01
15
XR-2211
Design Instructions:
The circuit of Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components:
R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these parameters are calculated as follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 7 fS = fO:
CO +
1
R 0·fs
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0·f 0·2
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C1 for a given loop damping factor:
Normally, j = 0.5 is recommended.
C1 +
1250·C 0
R 1·j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D § 16
Df
C in mF
Increasing CD slows down the logic output response time.
Design Examples:
Tone detector with a detection band of + 100Hz:
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20 KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 6 fS = fO:
C0 +
1 +
1
+ 50nF
20, 000·1, 000
R 0·f S
Rev. 3.01
16
XR-2211
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0·f O·2
20, 000·1, 000·2
+
+ 400K
100
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C0 for a given loop damping factor:
Normally, j = 0.5 is recommended.
C1 +
–9
1250·C 0
+ 1250·50·10 2 + 6.25pF
400, 000·0.5
R 1·j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D + 16 w 16 w 80nF
200
Df
Increasing CD slows down the logic output response time.
f)
Fine tune center frequency with 5KW potentiometer, RX.
VCC
VCC
RF
0.1µF
100K
Loop
Phase
Detect
2
0.1µF
FM
Input
3
8
11
7
+
C1
12
VCO
14
13
R1
CF
FSK
Comp
.
Internal
Reference
10
0.1µF
4
+
1
2
11
LM324
R0
6
C0
LDOQ
+
Quad
Phase
Detect
LDOQN
Lock
Detect
Comp.
5
Figure 13. Linear FM Detector Using XR-2211 and an External Op Amp.
(See Section on Design Equation for Component Values.)
Rev. 3.01
17
Demodulated
Output
XR-2211
Linear FM Detection
XR-2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry
applications. The recommended circuit connection for
this application is shown in Figure 13. The demodulated
output is taken from the loop phase detector output (pin
11), through a post-detection filter made up of RF and CF,
and an external buffer amplifier. This buffer amplifier is
necessary because of the high impedance output at pin
11. Normally, a non-inverting unity gain op amp can be
used as a buffer amplifier, as shown in Figure 13.
The FM detector gain, i.e., the output voltage change per
unit of FM deviation can be given as:
V OUT +
R 1·V REF
100·R 0
where VR is the internal reference voltage (VREF = VCC /2
- 650mV). For the choice of external components R1, R0,
CD, C1 and CF, see the section on design equations.
V+
1
REF
Voltage
Output
20K
Input
2
10
Lock
Detect
Filter
B
10K
10K
From
VCO
B’
3
6
Lock Detect
Outputs
20K
5
Internal Voltage
Reference
2K
Input Preamplifier
and Limiter
Lock Detect
Comparator
Quadrature
Phase Detector
2K
8
A
Timing
Capacitor
A’
13 C0 14
B’
B
11
A
From
VCO
A’
FSK
Comparator
Loop
Input
Detector
Output
7
FSK
Data
Output
4
12
R0 Timing
Resistor
8K
Ground
Voltage Controlled
Oscillator
Loop Phase Detector
Figure 14. Equivalent Schematic Diagram
Rev. 3.01
18
FSK Comparator
XR-2211
14 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
14
8
1
7
E
E1
D
A1
Base
Plane
Seating
Plane
A
L
e
c
B
α
B1
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.100
0.200
2.54
5.08
A1
0.015
0.060
0.38
1.52
B
0.014
0.026
0.36
0.66
B1
0.045
0.065
1.14
1.65
c
0.008
0.018
0.20
0.46
D
0.685
0.785
17.40
19.94
E1
0.250
0.310
6.35
7.87
E
0.300 BSC
7.62 BSC
e
0.100 BSC
2.54 BSC
L
0.125
0.200
3.18
5.08
α
0°
15°
0°
Note: The control dimension is the inch column
15°
Rev. 3.01
19
XR-2211
14 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
14
8
1
7
E1
E
D
Seating
Plane
A2
A
L
α
A1
B
INCHES
SYMBOL
MIN
eA
eB
B1
e
MAX
MILLIMETERS
MIN
MAX
A
0.145
0.210
3.68
5.33
A1
0.015
0.070
0.38
1.78
A2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.725
0.795
18.42
20.19
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 3.01
20
C
XR-2211
14 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
14
8
E
H
1
7
C
A
Seating
Plane
α
e
B
A1
L
INCHES
SYMBOL
MIN
MAX
MILLIMETERS
MIN
MAX
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.337
0.344
8.55
8.75
E
0.150
0.157
3.80
4.00
e
0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
α
0°
8°
0°
Note: The control dimension is the millimeter column
Rev. 3.01
21
8°
XR-2211
Notes
Rev. 3.01
22
XR-2211
Notes
Rev. 3.01
23
XR-2211
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1995 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.01
24
LM555
Timer
General Description
Features
The LM555 is a highly stable device for generating accurate
time delays or oscillation. Additional terminals are provided
for triggering or resetting if desired. In the time delay mode of
operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator,
the free running frequency and duty cycle are accurately
controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms, and
the output circuit can source or sink up to 200mA or drive
TTL circuits.
n
n
n
n
n
n
n
n
n
Direct replacement for SE555/NE555
Timing from microseconds through hours
Operates in both astable and monostable modes
Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TTL compatible
Temperature stability better than 0.005% per ˚C
Normally on and normally off output
Available in 8-pin MSOP package
Applications
n
n
n
n
n
n
n
Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator
Schematic Diagram
DS007851-1
© 2000 National Semiconductor Corporation
DS007851
www.national.com
LM555 Timer
February 2000
LM555
Connection Diagram
Dual-In-Line, Small Outline
and Molded Mini Small Outline Packages
DS007851-3
Top View
Ordering Information
Package
8-Pin SOIC
8-Pin MSOP
8-Pin MDIP
www.national.com
Part Number
Package Marking
Media Transport
LM555CM
LM555CM
Rails
LM555CMX
LM555CM
2.5k Units Tape and Reel
LM555CMM
Z55
1k Units Tape and Reel
LM555CMMX
Z55
3.5k Units Tape and Reel
LM555CN
LM555CN
Rails
2
NSC Drawing
M08A
MUA08A
N08E
Soldering Information
Dual-In-Line Package
Soldering (10 Seconds)
260˚C
Small Outline Packages
(SOIC and MSOP)
Vapor Phase (60 Seconds)
215˚C
Infrared (15 Seconds)
220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Power Dissi