Analog-to-Digital (AD) Conversion[G-1, J-2, W-2]

5.2 Analog-to-Digital (AD) Conversion[G-1, J-2, W-2]

An analog-to-digital converter (ADC) takes an unknown analog input signal, most often a voltage V x , and converts it into an N -bit binary number D representing the ratio of V x to the converter’s full-scale voltage V FS .

Most ADCs use a DAC to vary the reference voltage V r and use a logic cir- cuit including one or more comparators to deteremine one of the 2 N possible

binary numbers D = d 1 d 2 ···d N (d i ’s: binary coefficients) which can represent the unknown voltage V x . The reference voltage V r can have 2 N different values as

where V FS is the DC reference voltage. The basic difference in converters consists in how to vary V r to determine the binary coefficients d i ’s such that the error |V x −V r | is minimized.

5.2.1 Counter (Stair-Step) Ramp ADC

The counter ramp ADC illustrated in Fig. 5.2(a) starts to increment the N -bit counter value from zero by one per clock period on the SOC (start of conver- sion) pulse till the reference voltage V r exceeds the unknown input voltage V x .

Analog input

+ Comparator V

V Inverter

EOC

Clock pulse V r –

(End of conversion)

of period 1/f c AND

SOC

N -bit

N -bit

t Digital output (Start of conversion)

SOC

1/f c

(a) Block diagram (b) Timing diagram

1 : One clock period ( f c : the clock frequency)

Analog input V x f c

Reference voltage V r

Conversion time

T C,9 T C,10 T C,11 Time Digital output D

1000 0111 0101 0101 0100 0100 0100 0101 0101 0110 1001 (c) A typical variation of the analog input, reference voltage,digital output, and conversion time

Fig. 5.2 Counter ramp ADC

252 5 Sampling and Reconstruction The sequentially increasing counter output is applied to the N -bit DAC, making

its output V r go up like a staircase as depicted in Fig. 5.2(b). The reference voltage

V r is applied to the − input terminal of the comparator and compared against V x (applied to the + input terminal) by the comparator. The comparator output keeps

to be ‘1’ so that the counter will continue to increase normally till V r exceeds V x . When V r ≥V x , the comparator output will be switched to ‘0’ so that no further clock pulse can increment the counter value and the EOC (end of conversion) signal becomes high to tell other devices that an A/D conversion cycle is completed and the counter value represents the converted (digital) value of the unknown analog voltage

V x . Fig. 5.2(c) shows typical variations of the analog input, reference voltage, digital output, and conversion time. Some features of this converter should be noted:

< Advantage> – The simple hardware makes the counter ramp ADC inexpensive to implement. < Disadvantages> – The conversion time is proportional to the value of V x . In the worst case where

V x is equal to or greater than the value of the maximum binary number, i.e., V x ≥ (1 − 2 −N )V FS , it becomes

C =2 / f c (2 clock periods) (5.2.2) where f c is the clock frequency and V FS is the full-scale DAC output voltage.

– The DAC output is not necessarily the closest to V x , but the smallest just over V x among the 2 N possible binary numbers.

5.2.2 Tracking ADC

The tracking ADC tries to improve the conversion performance by using an up-down counter with logic to force the DAC output V r to track changes in the analog input

V x (see Fig. 5.3). Depending on whether V r < V x or V r > V x (as indicated by the comparator output), the counter value is incremented or decremented by the clock pulse so that the DAC output will alternate between two values differing by one LSB value (2 −N ) when V x is constant. When the analog input V x varies, V r changes in the proper direction towards V x so that V r follows V x . Consequently, if

V x varies slowly enough, the DAC output V r is continuously close to V x and the A/D converted value may be read from the counter at any time. However, if V x varies too rapidly, the DAC output V r will not be able to catch up with V x quickly enough to make the counter value represent V x closely at any time. The main drawback is the

5.2 Analog-to-Digital (AD) Conversion[G-1, J-2, W-2] 253

Analog input V x

+ Comparator bit bobble

bit bobble of period 1/f c

Clock pulse V r –

t V FS

catch-up time

Updown counter

t (a) Block diagram

SOC

| 1/f

Digital output

(b) Timing diagram Fig. 5.3 Tracking ADC

phenomenon called ‘bit bobble’ that the output is never stable since it switches back and forth with every clock pulse even for a constant analog input V x = const.

5.2.3 Successive Approximation ADC

The successive approximation ADC uses a binary or bisectional search method to determine the best approximation to V x , requiring only N clock periods to complete an N -bit conversion. Figure 5.4 shows its block diagram and timing diagram. At the start of conversion, the SAR (successive approximation register) is reset with its MSB set to ‘1’, resulting in the DAC output

V r ←2 −1 V FS

At the next clock pulse, depending on whether V r < V x or V r > V x (as indicated by the comparator output), the MSB is left on (‘1’) or set to ‘0’ and the 2nd MSB is set to ‘1’, resulting in

V r ←V r +2 −2 V FS or V r ←V r −2 −2 V FS

Analog input V x

+ Comparator V –2 –3 V

2 –1 x

FS

V +2 –2 V –2 r V FS FS Clock pulse V r

V FS

– +2 –3 V FS of period 1/f c

approximation EOC EOC

SOC

Digital output

1/f c

(a) Block diagram (b) Timing diagram Fig. 5.4 Successive approximation ADC

254 5 Sampling and Reconstruction

Fig. 5.5 Binary code sequence of a 3-bit successive approximation DAC

Again, depending on V r < V x or V r > V x , the 2nd MSB is left on(‘1’) or set to ‘0’ and the 3rd MSB is set to ‘1’, resulting in

V r ←V r +2 −3 V FS or V r ←V r −2 −3 V FS

When the process has been carried out for every bit, the SAR contains the binary number representing V x and EOC line indicates that digital output is available. In this way, the 3-bit successive conversion is completed at the end of N clock periods for an N -bit ADC so that we have the A/D conversion time

(5.2.3) Figure 5.5 shows the binary code sequence of a 3-bit successive approximation

T C = N/ f c (N clock periods)

DAC. This type of converter is very popular due to its fast conversion rate. A problem with the SA ADC is that if the input does not remain constant during the full con- version period, the digital output may not be related to the value of the unknown input voltage V x . To avoid this problem, sample-and-hold circuits are usually used ahead of the ADC.

5.2.4 Dual-Ramp ADC

Figure 5.6 shows the organization and operation of the dual-ramp ADC. On the SOC pulse, the counter and RC integrator are reset. Then the analog input V x , connected

to the integrator input through switch S 1 , is (negatively) integrated during a fixed time interval of T 1 =2 N / f c . At the end of the integration period, the two switches S 1 / S 2 are turned off/on, respectively so that the reference input −V FS are connected to the integrator input through S 2 . Then the integrator output v o increases until it crosses zero to make the comparator output change. The length of the deintegration

period will be measured as T 2 =n 2 / f c (n 2 clock periods).

5.2 Analog-to-Digital (AD) Conversion[G-1, J-2, W-2] 255

Comparator output Analog

RC Integrator

t Input

S 1 R C Integration Deintegration +V

2 Clock pulse

FS

Fixed slope of period 1/f c 0 v Integration

output

propotional to V FS

Control

Clock pulse logic

N -bit

Digital output 1 2 N

SOC

(a) Block diagram (b) Timing diagram Fig. 5.6 Dual ramp ADC Noting that the charge accumulated in the capacitor from t = 0 + to T 1 will have

been completely discharged at t = T 1 +T 2 , we can write

where T 1 =2 N / f c and V x is the average of V x . This implies that the counter value

n 2 accumulated during the deintergration period is supposed to represent the average value of the analog input:

The value of RC constant does not matter as long as it remains constant throughout

the conversion cycle of duration T 1 +T 2 .

< Advantage> – Even if V x changes during the conversion cycle, the ADC output corresponding to

V x is still valid since it represents the average value of V x during the integration

period of duration T 1 =2 N / f c .

– Any sinusoidal input signals with frequencies K / T 1 =K2 −N f c (K : an integer)

will have integrals of zero so that they will not disturb the ADC output. This property is utilized in digital voltmeters which use dual-ramp converters with

T 1 =K/f o where f o is the power-line frequency (50 or 60Hz), so that har- monic noise at multiples of f o can be removed (‘good rejection of power-line interference’).

– Reversed polarity of the analog input V x can easily be dealt with by reversing the polarity of −V FS .

< Disadvantages> – The conversion time is variable and is as long as

C =T 1 +T 2 = (2 + n)/ f c (5.2.6)

256 5 Sampling and Reconstruction

5.2.5 Parallel (Flash) ADC

Figure 5.7 shows a 3-bit parallel (or flash) ADC in which the analog input V x is simultaneously compared with (2 3 − 1) different reference values and depending on the comparison results, one of the 2 3 digital values is chosen as the ADC output by the encoding logic circuit.

< Advantage> – The conversion speed is so fast that the parallel ADC can be thought of as

automatically tracking the input signal. – With the resistors of no-equal values, the parallel ADC can be designed so that

it performs a customized, nonlinear A/D conversion. No other ADC design is capable of such a nonlinear AD conversion.

< Disadvantage> – The cost is expensive and grows rapidly with resolution since 2 N −1 comparators

and reference voltages are required for an N -bit converter.

(cf.) Visit the web site [W-2] to see the delta-sigma (ΔΣ) ADC.

Analog input

Digital output

16 V FS

Combinatorial logic d 3

16 V FS

16 V FS

Fig. 5.7 Parallel (or flash)

R/2

ADC

5.3 Sampling 257