Methodology for Intrinsic Capacitance Modeling
7.2 Methodology for Intrinsic Capacitance Modeling
7.2.1 Basic Formulation
To ensure charge conservation, terminal charges instead of terminal voltages are used as state variables. The terminal charges Q g ,Q b ,Q s , and Q d are the charges associated with the gate, bulk, source, and drain termianls, respectively. The gate charge is comprised of mirror charges from these components: the channel charge (Q inv ), accumulation charge (Q acc ) and substrate depletion charge (Q sub ).
The accumulation charge and the substrate charge are associated with the substrate while the channel charge comes from the source and drain terminals
Q g =− ( Q sub + Q inv + Q acc )
Q b = Q acc + Q sub
Q inv = Q s + Q d
The substrate charge can be divided into two components: the substrate charge at zero source-drain bias (Q sub 0 ), which is a function of gate to substrate bias, and the additional non-uniform substrate charge in the
presence of a drain bias ( δ Q sub ). Q g now becomes
Q g =− ( Q inv + Q acc + Q sub 0 + δ Q sub )
The total charge is computed by integrating the charge along the channel. The threshold voltage along the channel is modified due to the non- uniform substrate charge by
V th () y = V th ()( 0 + A bulk − 1 ) V y
L active Q c = W active
L active
q c dy = − W active C oxe ( V A ∫ V ∫ gt − bulk y ) dy
L active Q g = W active
L active
∫ g = active oxe ∫ (
V gt + V th − V FB − Φ s − V y ) dy
q dy W C
L active Q b = W active
L active
∫ b = − active oxe ∫ ( th − FB − Φ s + ( bulk − ) y )
W C V V A 1 V dy
q dy
where V gt =V gse -V th and
dy =
dV y
where E y is expressed in (7.2.5)
W active µ eff C oxe
A bulk
V ds V ds = W active µ eff C oxe ( V gt − A bulk V y ) E y
ds =
V gt −
L active
All capacitances are derived from the charges to ensure charge conservation. Since there are four terminals, there are altogether 16 components. For each component
C ij = ∂ V j
where i and j denote the transistor terminals. C ij satisfies
∑ C ij = ∑ C ij = i 0 j
7.2.2 Short Channel Model
The long-channel charge model assume a constant mobility with no velocity saturation. Since no channel length modulation is considered, the channel charge remains constant in saturation region. Conventional long-
channel charge models assume V dsat,CV = V gt /A bulk and therefore is independent of channel length. If we define a drain bias, V dsat,CV , for capacitance modeling, at which the channel charge becomes constant, we
will find that V dsat,CV in general is larger than V dsat for I-V but smaller than the long-channel V dsat =V gt /A bulk . In other words,
V gsteff , CV
V dsat , IV < V dsat , CV < V dsat , IV Lactive → ∞ =
A bulk
and V dsat,CV is modeled by (7.2.8)
V dsat , CV =
V gsteff , CV
CLE
CLC
A bulk ⋅ 1 +
L active
V gse − V th − VOFFCV
Model parameters CLC and CLE are introduced to consider the effect of
V gsteff , CV = NOFF ⋅ nv t ⋅ ln 1 + exp
NOFF ⋅ nv t
channel-length modulation. A bulk for the capacitance model is modeled by (7.2.10)
A 0 ⋅ L eff
⋅ L eff + 2 XJ ⋅ X dep W eff ' + B 1 1 + KETA ⋅ V bseff
A bulk = 1 + F − doping ⋅
where
1 + LPEB L eff K 1 ox
F − doping = + K 2 ox − K 3 B Φ s
TOXE
2 Φ s − V bseff
W eff ' + W 0
7.2.3 Single Equation Formulation
Traditional MOSFET SPICE capacitance models use piece-wise equations. This can result in discontinuities and non-smoothness at transition regions. The following describes single-equation formulation for charge, capacitance and voltage modeling in capMod = 1 and 2.
(a) Transition from depletion to inversion region
The biggest discontinuity is at threshold voltage where the inversion capacitance changes abruptly from zero to C oxe . Concurrently, since the substrate charge is a constant, the substrate capacitance drops abruptly to The biggest discontinuity is at threshold voltage where the inversion capacitance changes abruptly from zero to C oxe . Concurrently, since the substrate charge is a constant, the substrate capacitance drops abruptly to
Q ()( V gst = Q V gsteff , CV )
For capacitance modeling (7.2.12)
C ()( V gst = C V gsteff , CV )
∂ V gsteff , CV
(b) Transition from accumulation to depletion region
An effective smooth flatband voltage V FBeff is used for the accumulation and depletion regions.
FBeff = V fbzb − 0 . 5 ( V fbzb − V gb − 0 . 02 )( + V fbzb − V gb − 0 . 02 ) + 0 . 08 V fbzb
where (7.2.14)
V fbzb = V th zero V bs and V ds − Φ s − K 1 Φ s
A bias-independent V th is used to calculate V fbzb for capMod = 1 and 2. For capMod = 0, VFBCV is used instead (refer to Appendix A).
(c) Transition from linear to saturation region
An effective V ds ,V cveff , is used to smooth out the transition between linear and saturation regions.
(7.2.15) V 2
cveff = V dsat , CV − 0 . 5 { V 4 + V 4 + 4 δ 4 V dsat , CV } where V 4 = V dsat , CV − V ds − δ 4 ; δ 4 = 0 . 02 V
7.2.4 Charge partitioning
The inversion charges are partitioned into Q inv =Q s +Q d . The ratio of Q d to Q s is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (XPART = 1, 0.5 and 0).
50/50 charge partition This is the simplest of all partitioning schemes in which the inversion
charges are assumed to be contributed equally from the source and drain terminals.
40/60 charge partition This is the most physical model of the three partitioning schemes in which
the channel charges are allocated to the source and drain terminals by assuming a linear dependence on channel position y.
L active
Q s = W active
∫ 0 L active
dy
L active
q c dy
Q d = W active
0 L active
0/100 charge partition In fast transient simulations, the use of a quasi-static model may result in a
large unrealistic drain current spike. This partitioning scheme is developed to artificially suppress the drain current spike by assigning all inversion charges in the saturation region to the source electrode. Notice that this charge partitioning scheme will still give drain current spikes in the linear region and aggravate the source current spike problem.