Nano open house Ken David SS
I n t e l N a n ot e ch n ology Vir t u a l Ope n H ou se
Silicon Nanotechnology
at Intel
Ken David
Direct or of Com ponent s Research
Technology and Manufact uring Group
I nt el Corporat ion
Oct ober 22, 2004
1
Moore’s Law Continues…
10,000,000,000
1.7B transistors (90nm Montecito)
1,000,000,000
Itanium® 2 Processor
Itanium® Processor
Pentium® III Processor
Pentium® Processor
386™ Processor
4004
Pentium® 4
Processor
486™ DX Processor
1,000,000
100,000
10,000
8080
8008
1970
10,000,000
Pentium® II Processor
286
8086
100,000,000
1,000
1980
1990
2000
2010
Source: Intel
Increase
in
microprocessor complexity owing to improvement in
In
t e l N a n ot e ch
nology
Vir t ua l Ope n H ouse
transistors, interconnect and packaging
2
Transistor Scaling
0.10
1000
0.5µm
0.35µm
Technology
0.25µm
Node
0.18µm
Transistor
0.13µm
Physical Gate
90nm
65nm
Length 130nm
45nm
70nm
30nm
Nanotechnology 50nm
100
Nanometer
Micrometer
1.00
30nm
20nm
0.01
1990
15nm
1995
2000
2005
10
2010
Scaling to improve device speed/frequency of
I n t e l N a n ot e ch nology
operation and to pack more transistors in a
Vir t ua l Ope n H ouse
microprocessor.
3
Nanotechnology Research at Intel
N a n osca le m a t e r ia ls, pr oce sse s a n d
t e ch n ologie s w ill con t in u e t h e
im pr ove m e n t of ou r pr odu ct s:
Tr a n sist or r e se a r ch – for im pr ove d
de vice pe r for m a n ce a n d sca lin g.
I n t e r con n e ct r e se a r ch – for im pr ove d
w ir e con du ct ivit y a n d sca lin g.
M a n u fa ct u r in g r e se a r ch – for
im pr ove d u se fu ln e ss of n a n om a t e r ia ls
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
4
Transistor Nanotechnology
Research at Intel
N ove l de vice a r ch it e ct u r e s, e .g. Tr i ga t e
Ca r bon N a n ot u be s
Si a n d N on - Si N a n ow ir e s
I I I - V M a t e r ia ls, e .g. I nSb
GOALS:
Con t in u e im pr ovin g de vice
spe e d/ clock fr e qu e n cy
M a in t a in / r e du ce pow e r con su m pt ion
Fu r t h e r dim e n sion a l sca lin g
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
5
New Device Architecture
Tri-gate
Lg
Si
(Planar)
TSi
T
Planar fully depleted SOI
Isolation
TSi
Lg
WSi
Double-gate (e.g. FINFET)
(Non-Planar)
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Lg
WSi
TSi
Most
Manufacturable
Tri-gate
(Non-Planar)
6
Nano-Device Structure Evolution
Conventional Planar Transistor
Tri-gate Transistor
SiO2
SiO2
Gate
Fully-Surround Gate
Transistor
Gate
Improved
Electrostatics
Best Electrostatics
and Scalability
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Improving electrostatics optimizes
power consumption and performance
7
Tri-Gate Architecture:
Template for the future
Si nanowires
(defined by lithography)
S G D
S
G D
Multiple
wires
Gate
Total Drive Current =
Sou r ce : I n t e l
Id per nanotube/nanowire x no. of
tubes/wires
Silicon body, nanowires, nanotubes, etc.
Source
Gate
Electrode
Gate
Drain
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Sou r ce : I n t e l
8
Carbon Nanotube Transistor
Drain
Carbon
Nanotube
-
D = 1.4 nm
Gate
L g = 75 nm
Source
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Chemically synthesized
semiconducting
nanotubes with
diameter=2nm
form the transistor
channel.
Sou r ce : I n t e l
9
Carbon Nanotube Research
Transistor Made at Intel
DRAIN CURRENT [A]
1.E-05
Carbon nanotube
P-ch Transistor
1.E-06
1.E-07
1.E-08
VDS
-1.5 V
-1.0 V
-0.5 V
1.E-09
1.E-10
1.E-11
1.E-12
-3
-2
-1
0
1
2
GATE VOLTAGE [V]
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Nanotubes show transistor action similar to Si CMOS
10
with excellent switching performance!
Relative performance benefit of
Carbon Nanotube transistors
Transistor
Speed
Potentially 3X faster
transistor at same size and
power consumption
with use of CNT
75nm Lg CNT
75nm Lg PMOS
(standard transistor)
CNT shows promise, but much device
engineering optimization still to come !
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
11
Semiconductor Nanowires
Chemically synthesized
silicon nanowires with
diameters
Silicon Nanotechnology
at Intel
Ken David
Direct or of Com ponent s Research
Technology and Manufact uring Group
I nt el Corporat ion
Oct ober 22, 2004
1
Moore’s Law Continues…
10,000,000,000
1.7B transistors (90nm Montecito)
1,000,000,000
Itanium® 2 Processor
Itanium® Processor
Pentium® III Processor
Pentium® Processor
386™ Processor
4004
Pentium® 4
Processor
486™ DX Processor
1,000,000
100,000
10,000
8080
8008
1970
10,000,000
Pentium® II Processor
286
8086
100,000,000
1,000
1980
1990
2000
2010
Source: Intel
Increase
in
microprocessor complexity owing to improvement in
In
t e l N a n ot e ch
nology
Vir t ua l Ope n H ouse
transistors, interconnect and packaging
2
Transistor Scaling
0.10
1000
0.5µm
0.35µm
Technology
0.25µm
Node
0.18µm
Transistor
0.13µm
Physical Gate
90nm
65nm
Length 130nm
45nm
70nm
30nm
Nanotechnology 50nm
100
Nanometer
Micrometer
1.00
30nm
20nm
0.01
1990
15nm
1995
2000
2005
10
2010
Scaling to improve device speed/frequency of
I n t e l N a n ot e ch nology
operation and to pack more transistors in a
Vir t ua l Ope n H ouse
microprocessor.
3
Nanotechnology Research at Intel
N a n osca le m a t e r ia ls, pr oce sse s a n d
t e ch n ologie s w ill con t in u e t h e
im pr ove m e n t of ou r pr odu ct s:
Tr a n sist or r e se a r ch – for im pr ove d
de vice pe r for m a n ce a n d sca lin g.
I n t e r con n e ct r e se a r ch – for im pr ove d
w ir e con du ct ivit y a n d sca lin g.
M a n u fa ct u r in g r e se a r ch – for
im pr ove d u se fu ln e ss of n a n om a t e r ia ls
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
4
Transistor Nanotechnology
Research at Intel
N ove l de vice a r ch it e ct u r e s, e .g. Tr i ga t e
Ca r bon N a n ot u be s
Si a n d N on - Si N a n ow ir e s
I I I - V M a t e r ia ls, e .g. I nSb
GOALS:
Con t in u e im pr ovin g de vice
spe e d/ clock fr e qu e n cy
M a in t a in / r e du ce pow e r con su m pt ion
Fu r t h e r dim e n sion a l sca lin g
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
5
New Device Architecture
Tri-gate
Lg
Si
(Planar)
TSi
T
Planar fully depleted SOI
Isolation
TSi
Lg
WSi
Double-gate (e.g. FINFET)
(Non-Planar)
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Lg
WSi
TSi
Most
Manufacturable
Tri-gate
(Non-Planar)
6
Nano-Device Structure Evolution
Conventional Planar Transistor
Tri-gate Transistor
SiO2
SiO2
Gate
Fully-Surround Gate
Transistor
Gate
Improved
Electrostatics
Best Electrostatics
and Scalability
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Improving electrostatics optimizes
power consumption and performance
7
Tri-Gate Architecture:
Template for the future
Si nanowires
(defined by lithography)
S G D
S
G D
Multiple
wires
Gate
Total Drive Current =
Sou r ce : I n t e l
Id per nanotube/nanowire x no. of
tubes/wires
Silicon body, nanowires, nanotubes, etc.
Source
Gate
Electrode
Gate
Drain
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Sou r ce : I n t e l
8
Carbon Nanotube Transistor
Drain
Carbon
Nanotube
-
D = 1.4 nm
Gate
L g = 75 nm
Source
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Chemically synthesized
semiconducting
nanotubes with
diameter=2nm
form the transistor
channel.
Sou r ce : I n t e l
9
Carbon Nanotube Research
Transistor Made at Intel
DRAIN CURRENT [A]
1.E-05
Carbon nanotube
P-ch Transistor
1.E-06
1.E-07
1.E-08
VDS
-1.5 V
-1.0 V
-0.5 V
1.E-09
1.E-10
1.E-11
1.E-12
-3
-2
-1
0
1
2
GATE VOLTAGE [V]
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
Nanotubes show transistor action similar to Si CMOS
10
with excellent switching performance!
Relative performance benefit of
Carbon Nanotube transistors
Transistor
Speed
Potentially 3X faster
transistor at same size and
power consumption
with use of CNT
75nm Lg CNT
75nm Lg PMOS
(standard transistor)
CNT shows promise, but much device
engineering optimization still to come !
I n t e l N a n ot e ch nology
Vir t ua l Ope n H ouse
11
Semiconductor Nanowires
Chemically synthesized
silicon nanowires with
diameters