Index of /intel-research/silicon SEMI Ken David 0403
Intel Corporation
Silicon Technology Review
Ken David
Director, Components Research
SEMI – Strategic Business Conference
April 2003
Agenda
y Corporate Mission
– Leadership in Technology
– Leadership in Integration
y How do we continue to succeed?
– Investments
– Research and Development
– Manufacturing Excellence
y Supplier Expectations
y Summary
2
Entering A New Era
Converged
Computing and
Communications
Microprocessors
Memory
3
Leadership by Technology
Desktop
Server
4
Leadership by Integration
Intel® PXA800F Processor
Intel®
MicroSignal
Architecture
Power Management
Intel®
OnChip
Flash
4MB/512kB
Intel® Mobile Technology
GSM/GPRS &
Intel®
XScale™
Core
Peripherals
SRAM
512kB/64kB
5
How do we continue to lead?
y Commitment through investments
y Commitment through advanced research and
development – new technologies
y Continued, successful implementation of
Moore’s Law
y Commitment through manufacturing excellence
6
Intel Capital Expenses
Capital Ex: Intel v. Competitors (00 - 03)
*Estimate
Billions($)
25
20
15
10
5
0
Intel
Competitor 1
Competitor 2
Competitor 3
Source: Intel
7
Intel R&D Investment ($M)
$4,000 $4,000 est.
$3,897 $3,800
$3,111
$2,509
$2,347
$1,808
$517
$618
$780
$970
$1,296
$1,111
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
Source: Intel Annual Report
8
Worldwide Intel R&D Presence
75+ labs and over 7,000 R&D
professionals
Copenhagen,
Denmark
Washington
USA
Oregon
USA
Glasgow,
Scotland
Illinois
USA
Swindon,
Swindon, UK
Stockholm,
Sweden
Gdansk, Poland
Shannon, Ireland
Nice, France
California
USA
New Mexico, USA
Arizona
USA
Nizhny
Novgorod,
Sarov
Russia
Braunschweig,
Braunschweig,
Ulm
Germany
Beijing
Shanghai
China
Barcelona,
Spain
Haifa, Israel
Delhi
Bangalore
Mumbai
India
Tsukuba
Tokyo
Japan
Decentralized
DecentralizedApproach
ApproachFosters
FostersInnovation
Innovation
9
Technology Focus:
Microprocessor Products
• Research Groups are de-centralized
• Multiple sites
• Central Technology Development groups
• Logic: Hillsboro, Oregon
• Memory: Santa Clara, California
• Packaging: Chandler, Arizona
• Copy Exactly! from Development into
Manufacturing
• Fastest and Highest Volume Manufacturing
Ramp
10
Technology Focus: Logic
Actual
Forecast
Process Name
P858 Px60 P1262 P1264 P1266 P1268 P1270
1st Production
1999 2001 2003
2005 2007
2009 2011
Lithography Node
180
130
90
65
45
32
22nm
Gate Length
130
70
50
30
20
15
10nm
Fab
Development
Copy Exactly!
Research
Pathfinding
11
Leadership through
Technology
y Mission – to continue to provide leading edge
technology in computing and communications
y Financial Challenges
y Technology Challenges
– Increasing chip complexity
– aggressive scaling
– new materials
– added features (integrated capabilities)
– New concerns: Power, heat
12
Moore’s Law.... in the
beginning
1965 Transistor Projection
1975 Transistor Projection
13
Moore’s Law Today
1,000,000,000
100,000,000
Itanium ® Processor
1,000,000
Pentium® 4 Processor
Pentium® III Processor
Pentium® II Processor
Pentium® Processor
486™ DX Processor
100,000
386™ Processor
286
10,000,000
10,000
410 Million
8086
8080
1,000 8008
1970
1980
1990
2000
2010
Heading toward 1 billion transistors in 2007
14
Moore’s Law Economics
(Source: Intel, VLSIR)
1993
1998
2003
200
200
300
Fab cost, $B 0.9
2
3
Fab
capacity,
kwpm
20
40
$B/kwpm
0.04
0.05
30 - 35
~77 (200mmequivalent)
0.04
Wafer size,
mm
15
Evolution of Intel Process
Node
1997
1999
2001
0.25µm 0.18 µm 130nm
2003
90nm
2005
65nm
2007
45nm
2009
32nm
2011
22nm
193/157
?
?
Litho
DUV
Æ
193nm
Æ
Æ
Metal
Al
Æ
Cu
Æ
Æ
Æ
Æ
?
ILD
SiO2
SiOF
Æ
SiOC
Æ
Æ
?
?
Gate Ox
SiO2
Æ
Æ
Æ
High-k?
?
?
?
Gate
Electrode Poly
Æ
Æ
Æ
Æ
Metal?
?
New
Materials
New
Structures
New
Processes
?
Extending
Moore’s
Law!
16
Success in 90nm development
Silicide
Layer
Low K
ILD
Silicon
Gate
Electrode
Low K
etch stop
1.2 nm
SiO2 Gate
Oxide
50nm
Advanced
Cu barriers
Cu
interconnects
Strained
Silicon
17
Driving Moore’s Law Further
90nm Node
2003
65nm Node
2005
45nm Node
2007
50nm Length
(IEDM2002)
32nm Node
2009
30nm Prototype
(IEDM2000)
25 nm
20nm Prototype
(VLSI2001)
22nm Node
2011
15nm
15nm Prototype
(IEDM2001)
10nm Prototype
(ITJ 2002)
18
Working on Advanced Transistor Architecture
Î New ProcessÎ Need New Materials
Gate
Drain
Source
World record breaking NMOS
performance demonstrated today!
19
Intel Lithography Roadmap
1000
1/2 Pitch (nm)
ITRS “Nodes”
130nm Node
90nm Node
100
65nm Node
45nm Node
32nm Node
“Dual Wavelength Strategy”
10
i-line
DUV
i-line
DUV
DUV 193nm 193nm 193nm 157nm EUV EUV
DUV
193nm 157nm
EUV
1993
1995
1997
1999
2013
2001
2003
2005
2007
2009
2011
20
157nm Lithography
1999
2000
2001
157nm lithography is maturing:
z
Research tools shipping in 2003
z
Development tools scheduled for 2004
z
Single layer resists are making rapid progress
21
EUV Lithography - Full Field ETS images
(using 0.1 NA system)
100 nm Elbows 1:1
80 nm Elbows 1:1
200 mm Wafer
100 nm contacts 1:1
4x5 matrix
24 x 32.5 mm2 field
152 mm2, 4X
Reflective Mask
Printing 80 nm images at 0.1 NA is equivalent
to printing 32 nm with 0.25 NA production system
22
Leadership By Integration
Computing + Communications on One Chip
Silicon Level Integration
Functions combined on single chip
Package Level Integration
Stacked discrete chips and packages
Functions on Discrete Chips
Flash, Applications processors, Cellular chipsets
2002
2004
2006
23
Wireless Internet on a Chip
by Flash+Logic Integration
Intel® PXA800F Processor
Flash
Power Management
0.16µm2 Flash Cell
Intel®
OnChip
Flash
4MB/512kB
Intel®
MicroSignal
Architecture
GSM/GPRS &
Intel®
XScale™
Core
Logic
90nm
Peripherals
90nm Transistor Gate
SRAM
512kB/64kB
24
Continued Manufacturing
Excellence
y 0.13 µm manufacturing leadership
y Worldwide Presence
y Intel Manufacturing Philosophy
– Technology Development and Manufacturing Linked
– Copy Exact! Transfer of Processes
– Manufacturing Efficiency Æ 300mm Production
– Leading Edge Capacity
25
Intel’s High Volume Manufacturing Sites
Washington
Ireland
Systems Mfg.
Colorado
Fab 23
Oregon
Mass.
Dev D1C/D1D
Fab 15/20
Board Mfg.
China
Fab 14/24
Fab 17
Pudong A/T
Sub-con Mfg.
Israel
Fab 8/18
California
Dev D2
Sub-con Mfg.
Arizona
New Mexico
Fab12/22
A/T Dev
Fab 11/11X
Costa Rica
San Jose A/T
Taiwan
Thailand
Sub-con Mfg.
Malaysia
Penang A/T
Kulim A/T
Kulim Board/Module Mfg.
Brazil
Sub-con Mfg.
Sub-con Mfg.
Sub-con Mfg.
Philippines
Manila A/T
Cavite A/T
26
0.13µm(130nm) Leadership
Breaking Away from the competition
300mm
Wafer Starts
F11X
200mm
F17
D1C
F22
F20 D2
Q1
Q2
Q3
2001
Nearest CPU
Competitor
Q4
Q1
Q2
Q3
2002
Source: Intel
Q4
Q1
Q2
Q3
Q4
2003
27
Logic Development:
Linking 300mm Research, Development, and
Production
D1D: 300mm
65nm Development
RP1: 300mm
Research
D1C/F25:D1C:
300mm
300mm
0.13µm130nm
Production
Production
90nm Development
90nm Development
and Production
F20:300mm
200mm
RP1:
0.13µm
Production
Research
Source: Intel
28
Manufacturing Efficiency
Capital spending per die of
output capacity
$
.18um
.13um
200 mm
Source: Intel
.13um
.09um
300 mm
29
Scale: Leading Edge Capacity
90nm
0.13u
F24
WSPW
F11X
300mm
D1C
300mm
F11X
F22
D1C
Q
F20
F17
D2
Q+1
Q+2
Q+3
Q+4
Q+5
Q+6
Q+7
(Quarter in Ramp)
**Source: Intel Estimates
30
Supplier Expectations
y Manufacturing excellence
– Timely, cost-efficient support during HVM ramp
– Quality systems
y Advanced Development
– New equipment and capabilities matched with Intel’s
roadmap
– Process Development
y Research
– Collaborative efforts to foster innovation
31
Summary
Intel is committed to the future technologies
Success starts with the present
• 90nm technology innovation
• 90nm ramp in 2H’03
...and leads to the future
• continued extension of Moore’s Law
• Package level integration
• System on a chip
32
For further information on Intel's silicon technology
and Moore’s Law, please visit the Silicon Showcase
at www.intel.com/research/silicon
33
Silicon Technology Review
Ken David
Director, Components Research
SEMI – Strategic Business Conference
April 2003
Agenda
y Corporate Mission
– Leadership in Technology
– Leadership in Integration
y How do we continue to succeed?
– Investments
– Research and Development
– Manufacturing Excellence
y Supplier Expectations
y Summary
2
Entering A New Era
Converged
Computing and
Communications
Microprocessors
Memory
3
Leadership by Technology
Desktop
Server
4
Leadership by Integration
Intel® PXA800F Processor
Intel®
MicroSignal
Architecture
Power Management
Intel®
OnChip
Flash
4MB/512kB
Intel® Mobile Technology
GSM/GPRS &
Intel®
XScale™
Core
Peripherals
SRAM
512kB/64kB
5
How do we continue to lead?
y Commitment through investments
y Commitment through advanced research and
development – new technologies
y Continued, successful implementation of
Moore’s Law
y Commitment through manufacturing excellence
6
Intel Capital Expenses
Capital Ex: Intel v. Competitors (00 - 03)
*Estimate
Billions($)
25
20
15
10
5
0
Intel
Competitor 1
Competitor 2
Competitor 3
Source: Intel
7
Intel R&D Investment ($M)
$4,000 $4,000 est.
$3,897 $3,800
$3,111
$2,509
$2,347
$1,808
$517
$618
$780
$970
$1,296
$1,111
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
Source: Intel Annual Report
8
Worldwide Intel R&D Presence
75+ labs and over 7,000 R&D
professionals
Copenhagen,
Denmark
Washington
USA
Oregon
USA
Glasgow,
Scotland
Illinois
USA
Swindon,
Swindon, UK
Stockholm,
Sweden
Gdansk, Poland
Shannon, Ireland
Nice, France
California
USA
New Mexico, USA
Arizona
USA
Nizhny
Novgorod,
Sarov
Russia
Braunschweig,
Braunschweig,
Ulm
Germany
Beijing
Shanghai
China
Barcelona,
Spain
Haifa, Israel
Delhi
Bangalore
Mumbai
India
Tsukuba
Tokyo
Japan
Decentralized
DecentralizedApproach
ApproachFosters
FostersInnovation
Innovation
9
Technology Focus:
Microprocessor Products
• Research Groups are de-centralized
• Multiple sites
• Central Technology Development groups
• Logic: Hillsboro, Oregon
• Memory: Santa Clara, California
• Packaging: Chandler, Arizona
• Copy Exactly! from Development into
Manufacturing
• Fastest and Highest Volume Manufacturing
Ramp
10
Technology Focus: Logic
Actual
Forecast
Process Name
P858 Px60 P1262 P1264 P1266 P1268 P1270
1st Production
1999 2001 2003
2005 2007
2009 2011
Lithography Node
180
130
90
65
45
32
22nm
Gate Length
130
70
50
30
20
15
10nm
Fab
Development
Copy Exactly!
Research
Pathfinding
11
Leadership through
Technology
y Mission – to continue to provide leading edge
technology in computing and communications
y Financial Challenges
y Technology Challenges
– Increasing chip complexity
– aggressive scaling
– new materials
– added features (integrated capabilities)
– New concerns: Power, heat
12
Moore’s Law.... in the
beginning
1965 Transistor Projection
1975 Transistor Projection
13
Moore’s Law Today
1,000,000,000
100,000,000
Itanium ® Processor
1,000,000
Pentium® 4 Processor
Pentium® III Processor
Pentium® II Processor
Pentium® Processor
486™ DX Processor
100,000
386™ Processor
286
10,000,000
10,000
410 Million
8086
8080
1,000 8008
1970
1980
1990
2000
2010
Heading toward 1 billion transistors in 2007
14
Moore’s Law Economics
(Source: Intel, VLSIR)
1993
1998
2003
200
200
300
Fab cost, $B 0.9
2
3
Fab
capacity,
kwpm
20
40
$B/kwpm
0.04
0.05
30 - 35
~77 (200mmequivalent)
0.04
Wafer size,
mm
15
Evolution of Intel Process
Node
1997
1999
2001
0.25µm 0.18 µm 130nm
2003
90nm
2005
65nm
2007
45nm
2009
32nm
2011
22nm
193/157
?
?
Litho
DUV
Æ
193nm
Æ
Æ
Metal
Al
Æ
Cu
Æ
Æ
Æ
Æ
?
ILD
SiO2
SiOF
Æ
SiOC
Æ
Æ
?
?
Gate Ox
SiO2
Æ
Æ
Æ
High-k?
?
?
?
Gate
Electrode Poly
Æ
Æ
Æ
Æ
Metal?
?
New
Materials
New
Structures
New
Processes
?
Extending
Moore’s
Law!
16
Success in 90nm development
Silicide
Layer
Low K
ILD
Silicon
Gate
Electrode
Low K
etch stop
1.2 nm
SiO2 Gate
Oxide
50nm
Advanced
Cu barriers
Cu
interconnects
Strained
Silicon
17
Driving Moore’s Law Further
90nm Node
2003
65nm Node
2005
45nm Node
2007
50nm Length
(IEDM2002)
32nm Node
2009
30nm Prototype
(IEDM2000)
25 nm
20nm Prototype
(VLSI2001)
22nm Node
2011
15nm
15nm Prototype
(IEDM2001)
10nm Prototype
(ITJ 2002)
18
Working on Advanced Transistor Architecture
Î New ProcessÎ Need New Materials
Gate
Drain
Source
World record breaking NMOS
performance demonstrated today!
19
Intel Lithography Roadmap
1000
1/2 Pitch (nm)
ITRS “Nodes”
130nm Node
90nm Node
100
65nm Node
45nm Node
32nm Node
“Dual Wavelength Strategy”
10
i-line
DUV
i-line
DUV
DUV 193nm 193nm 193nm 157nm EUV EUV
DUV
193nm 157nm
EUV
1993
1995
1997
1999
2013
2001
2003
2005
2007
2009
2011
20
157nm Lithography
1999
2000
2001
157nm lithography is maturing:
z
Research tools shipping in 2003
z
Development tools scheduled for 2004
z
Single layer resists are making rapid progress
21
EUV Lithography - Full Field ETS images
(using 0.1 NA system)
100 nm Elbows 1:1
80 nm Elbows 1:1
200 mm Wafer
100 nm contacts 1:1
4x5 matrix
24 x 32.5 mm2 field
152 mm2, 4X
Reflective Mask
Printing 80 nm images at 0.1 NA is equivalent
to printing 32 nm with 0.25 NA production system
22
Leadership By Integration
Computing + Communications on One Chip
Silicon Level Integration
Functions combined on single chip
Package Level Integration
Stacked discrete chips and packages
Functions on Discrete Chips
Flash, Applications processors, Cellular chipsets
2002
2004
2006
23
Wireless Internet on a Chip
by Flash+Logic Integration
Intel® PXA800F Processor
Flash
Power Management
0.16µm2 Flash Cell
Intel®
OnChip
Flash
4MB/512kB
Intel®
MicroSignal
Architecture
GSM/GPRS &
Intel®
XScale™
Core
Logic
90nm
Peripherals
90nm Transistor Gate
SRAM
512kB/64kB
24
Continued Manufacturing
Excellence
y 0.13 µm manufacturing leadership
y Worldwide Presence
y Intel Manufacturing Philosophy
– Technology Development and Manufacturing Linked
– Copy Exact! Transfer of Processes
– Manufacturing Efficiency Æ 300mm Production
– Leading Edge Capacity
25
Intel’s High Volume Manufacturing Sites
Washington
Ireland
Systems Mfg.
Colorado
Fab 23
Oregon
Mass.
Dev D1C/D1D
Fab 15/20
Board Mfg.
China
Fab 14/24
Fab 17
Pudong A/T
Sub-con Mfg.
Israel
Fab 8/18
California
Dev D2
Sub-con Mfg.
Arizona
New Mexico
Fab12/22
A/T Dev
Fab 11/11X
Costa Rica
San Jose A/T
Taiwan
Thailand
Sub-con Mfg.
Malaysia
Penang A/T
Kulim A/T
Kulim Board/Module Mfg.
Brazil
Sub-con Mfg.
Sub-con Mfg.
Sub-con Mfg.
Philippines
Manila A/T
Cavite A/T
26
0.13µm(130nm) Leadership
Breaking Away from the competition
300mm
Wafer Starts
F11X
200mm
F17
D1C
F22
F20 D2
Q1
Q2
Q3
2001
Nearest CPU
Competitor
Q4
Q1
Q2
Q3
2002
Source: Intel
Q4
Q1
Q2
Q3
Q4
2003
27
Logic Development:
Linking 300mm Research, Development, and
Production
D1D: 300mm
65nm Development
RP1: 300mm
Research
D1C/F25:D1C:
300mm
300mm
0.13µm130nm
Production
Production
90nm Development
90nm Development
and Production
F20:300mm
200mm
RP1:
0.13µm
Production
Research
Source: Intel
28
Manufacturing Efficiency
Capital spending per die of
output capacity
$
.18um
.13um
200 mm
Source: Intel
.13um
.09um
300 mm
29
Scale: Leading Edge Capacity
90nm
0.13u
F24
WSPW
F11X
300mm
D1C
300mm
F11X
F22
D1C
Q
F20
F17
D2
Q+1
Q+2
Q+3
Q+4
Q+5
Q+6
Q+7
(Quarter in Ramp)
**Source: Intel Estimates
30
Supplier Expectations
y Manufacturing excellence
– Timely, cost-efficient support during HVM ramp
– Quality systems
y Advanced Development
– New equipment and capabilities matched with Intel’s
roadmap
– Process Development
y Research
– Collaborative efforts to foster innovation
31
Summary
Intel is committed to the future technologies
Success starts with the present
• 90nm technology innovation
• 90nm ramp in 2H’03
...and leads to the future
• continued extension of Moore’s Law
• Package level integration
• System on a chip
32
For further information on Intel's silicon technology
and Moore’s Law, please visit the Silicon Showcase
at www.intel.com/research/silicon
33