Gordon Moore ISSCC 021003
NO EXPONENTIAL IS FOREVER . . .
Gordon E. Moore
Worldwide Semiconductor Revenues
$B
1000
100
10
1
'68 ’70 '72 '74 '76 '78 '80 '82 '84 '86 '88 ’90 '92 '94 '96 '98 '00 '02
Source: Intel/WSTS,12/02
Transistors Shipped Per Year
1018
1017
1016
1015
14
Units 10
1013
1012
1011
1010
10 9
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
Source: Dataquest/Intel, 12/02
Average Transistor Price By Year
$
10
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
'68
'70
'72
'74
'76
'78
'80
'82
'84
'86
Source: Dataquest/Intel12/02
'88
'90
'92
'94
'96
'98
'00
'02
1” Wafer Of Planar Transistors, ~1959
The First Planar Integrated Circuit, 1961
1965 Transistor Projection
Integrated Circuit Complexity
Transistors
Per Die
1010
109
1965 Actual Data
MOS Arrays
MOS Logic 1975 Actual Data
108
107
106
105
104
103
102
101
100
1960
1965
1970
1975
1980
1985
Source: Intel
1990
1995
2000
2005
2010
Integrated Circuit Complexity
Transistors
Per Die
1010
109
1965 Actual Data
MOS Arrays
MOS Logic 1975 Actual Data
108
1975 Projection
107
106
105
104
103
102
101
100
1960
1965
1970
1975
1980
1985
Source: Intel
1990
1995
2000
2005
2010
Integrated Circuit Complexity
Transistors
Per Die
1010
109
108
107
1G 2G
256M 512M
™
128M
Itanium
64M
Pentium® 4
16M
Pentium® III
4M
® II
Pentium
Pentium®
i486™
1965 Actual Data
MOS Arrays
MOS Logic 1975 Actual Data
1975 Projection
Memory
S Microprocessor
1M
106
256K
64K
105
4K
104
1K
103
16K
80286
4G
i386™
8086
8080
4004
102
101
100
1960
1965
1970
1975
1980
1985
Source: Intel
1990
1995
2000
2005
2010
300mm Wafer
Projected 2000 Wafer, circa 1975
57"
Moore was not always accurate
90 nm Generation Interconnects
M7
Low-k CDO
Dielectric
M6
M5
Copper
Interconnects
M4
M3
M2
M1
Combination of copper + low-k dielectric now
meeting performance and manufacturing goals
Minimum Feature Size
Feature Size
(microns)
100
Examples
Human hair, 100 µm
**
Amoeba, 15 µm
10
Red blood cell, 7 µm
1
Intel [update 5/20/02]
ITRS [2001 edition]
0.1
AIDS virus, 0.1 µm
0.01
'60
'65
'70
** Planar Transistor; remaining data points are ICs.
Source: Intel, post ‘96 trend data provided by SIA
International Technology Roadmap for Semiconductors (ITRS)
^ [ITRS DRAM HalfHalf-Pitch vs. Intel “Lithography”]
'75
’80
'85
'90
'95
’00
'05
Projected
Buckyball, 0.001 µm
'10
1 µm2 SRAM Cell
P501 Contact
P501 Contact
P501
Contact
1978
1978
P1262 SRAM Cell
2002
P1262 SRAM Cell
2002
1 µm
50nm Resist Lines With 193nm Light
-0.2um focus
-0.3um focus
+0.2um focus
+0.3um focus
“best focus”
193nm Step and Scan Production Tool
Minimum Insulator Thickness vs Time
Oxide Thickness
(Nanometers)
100
1.0µ
0.35µ
0.25µ
0.18µ
0.13µ
10
Electrical
Physical
1
'69
'72
'75
'78
'90
Source: Intel
'93
'96
'99
'02
'05
High K for Gate Dielectrics
Gate
Gate
1.2nm SiO2
3.0nm High-k
Silicon substrate
Silicon substrate
90nm process
Capacitance
1X
Leakage
1X
Source: Intel
Experimental high-k
1.6X
< 0.01X
Processor Performance (MIPS)
100000
10000
Pentium® 4
Pentium® 2
1000
100
MIPS
486
386
10
1
0.1
Pentium®
286
8086
8080
8008
4004
0.01
1970
1975
1980
1985
1990
1995
2000
2005
Processor Power (Watts) - Active & Leakage
1000
Power (W)
100
Active
10
1
Leakage
0.1
0.01
0.001
1960
1970
1980
1990
2000
2010
Processor Supply Voltage
Power Supply (Volt)
100
10
1
1970
1980
1990
2000
2010
New Materials and Device Structures
Extending Transistor Scaling
Changes
Made
Future
Options
Gate
High-k
Gate
Dielectric
Silicide
Added
Channel
Strained
Silicon
New
Transistor
Structure
Transistor
Tri-Gate Transistor Structure
Lg
WSi
Drain
Current
Gate
Tox
Source
HSi
SiO2
Technology Generations to Come
Double the Density
Reduce Line Width by 0.7x
130nm¼90nm¼60nm¼45nm¼30nm¼?
2 or 3 years between generations
~10 ± 2 Years
EUV Printed and Etched Lines
100 nm, k1 = 0.75
80 nm, k1 = 0.60
50 nm dense, k1 = 0.37
Extreme Ultraviolet (EUV) Lithography
Lithography Tool Cost ( $ )
Litho Tool Cost ( $ )
Exp+08
Exp+07
Exp+06
Exp+05
Exp+04
1960
1970
1980
1990
2000
2010
NO EXPONENTIAL IS FOREVER . . .
BUT
WE CAN DELAY “FOREVER”
Gordon E. Moore
Worldwide Semiconductor Revenues
$B
1000
100
10
1
'68 ’70 '72 '74 '76 '78 '80 '82 '84 '86 '88 ’90 '92 '94 '96 '98 '00 '02
Source: Intel/WSTS,12/02
Transistors Shipped Per Year
1018
1017
1016
1015
14
Units 10
1013
1012
1011
1010
10 9
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
Source: Dataquest/Intel, 12/02
Average Transistor Price By Year
$
10
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
'68
'70
'72
'74
'76
'78
'80
'82
'84
'86
Source: Dataquest/Intel12/02
'88
'90
'92
'94
'96
'98
'00
'02
1” Wafer Of Planar Transistors, ~1959
The First Planar Integrated Circuit, 1961
1965 Transistor Projection
Integrated Circuit Complexity
Transistors
Per Die
1010
109
1965 Actual Data
MOS Arrays
MOS Logic 1975 Actual Data
108
107
106
105
104
103
102
101
100
1960
1965
1970
1975
1980
1985
Source: Intel
1990
1995
2000
2005
2010
Integrated Circuit Complexity
Transistors
Per Die
1010
109
1965 Actual Data
MOS Arrays
MOS Logic 1975 Actual Data
108
1975 Projection
107
106
105
104
103
102
101
100
1960
1965
1970
1975
1980
1985
Source: Intel
1990
1995
2000
2005
2010
Integrated Circuit Complexity
Transistors
Per Die
1010
109
108
107
1G 2G
256M 512M
™
128M
Itanium
64M
Pentium® 4
16M
Pentium® III
4M
® II
Pentium
Pentium®
i486™
1965 Actual Data
MOS Arrays
MOS Logic 1975 Actual Data
1975 Projection
Memory
S Microprocessor
1M
106
256K
64K
105
4K
104
1K
103
16K
80286
4G
i386™
8086
8080
4004
102
101
100
1960
1965
1970
1975
1980
1985
Source: Intel
1990
1995
2000
2005
2010
300mm Wafer
Projected 2000 Wafer, circa 1975
57"
Moore was not always accurate
90 nm Generation Interconnects
M7
Low-k CDO
Dielectric
M6
M5
Copper
Interconnects
M4
M3
M2
M1
Combination of copper + low-k dielectric now
meeting performance and manufacturing goals
Minimum Feature Size
Feature Size
(microns)
100
Examples
Human hair, 100 µm
**
Amoeba, 15 µm
10
Red blood cell, 7 µm
1
Intel [update 5/20/02]
ITRS [2001 edition]
0.1
AIDS virus, 0.1 µm
0.01
'60
'65
'70
** Planar Transistor; remaining data points are ICs.
Source: Intel, post ‘96 trend data provided by SIA
International Technology Roadmap for Semiconductors (ITRS)
^ [ITRS DRAM HalfHalf-Pitch vs. Intel “Lithography”]
'75
’80
'85
'90
'95
’00
'05
Projected
Buckyball, 0.001 µm
'10
1 µm2 SRAM Cell
P501 Contact
P501 Contact
P501
Contact
1978
1978
P1262 SRAM Cell
2002
P1262 SRAM Cell
2002
1 µm
50nm Resist Lines With 193nm Light
-0.2um focus
-0.3um focus
+0.2um focus
+0.3um focus
“best focus”
193nm Step and Scan Production Tool
Minimum Insulator Thickness vs Time
Oxide Thickness
(Nanometers)
100
1.0µ
0.35µ
0.25µ
0.18µ
0.13µ
10
Electrical
Physical
1
'69
'72
'75
'78
'90
Source: Intel
'93
'96
'99
'02
'05
High K for Gate Dielectrics
Gate
Gate
1.2nm SiO2
3.0nm High-k
Silicon substrate
Silicon substrate
90nm process
Capacitance
1X
Leakage
1X
Source: Intel
Experimental high-k
1.6X
< 0.01X
Processor Performance (MIPS)
100000
10000
Pentium® 4
Pentium® 2
1000
100
MIPS
486
386
10
1
0.1
Pentium®
286
8086
8080
8008
4004
0.01
1970
1975
1980
1985
1990
1995
2000
2005
Processor Power (Watts) - Active & Leakage
1000
Power (W)
100
Active
10
1
Leakage
0.1
0.01
0.001
1960
1970
1980
1990
2000
2010
Processor Supply Voltage
Power Supply (Volt)
100
10
1
1970
1980
1990
2000
2010
New Materials and Device Structures
Extending Transistor Scaling
Changes
Made
Future
Options
Gate
High-k
Gate
Dielectric
Silicide
Added
Channel
Strained
Silicon
New
Transistor
Structure
Transistor
Tri-Gate Transistor Structure
Lg
WSi
Drain
Current
Gate
Tox
Source
HSi
SiO2
Technology Generations to Come
Double the Density
Reduce Line Width by 0.7x
130nm¼90nm¼60nm¼45nm¼30nm¼?
2 or 3 years between generations
~10 ± 2 Years
EUV Printed and Etched Lines
100 nm, k1 = 0.75
80 nm, k1 = 0.60
50 nm dense, k1 = 0.37
Extreme Ultraviolet (EUV) Lithography
Lithography Tool Cost ( $ )
Litho Tool Cost ( $ )
Exp+08
Exp+07
Exp+06
Exp+05
Exp+04
1960
1970
1980
1990
2000
2010
NO EXPONENTIAL IS FOREVER . . .
BUT
WE CAN DELAY “FOREVER”