ATD press briefing IDF 091803
Delivering Package
Innovations to Enable
Future Products
Introducing
Introducing the
the Industry’s
Industry’s First
First 90nm
90nm -- Low
Low K
K
Organic
Organic Flip
Flip Chip
Chip Package
Package
Dan Belton & Johanna Swan
Assembly Technology Development
Technology Manufacturing Group
Chandler, Arizona
1
Agenda
y Packaging @ Intel
y Convergence… Changing the Role of
Packaging
y Packaging Challenges & Innovations Intel
is Delivering
y Summary
2
Assembly Technology Development
Chandler Campus
Printing
Pick & Place
Dispense
W ire
Bonder
The Assem bly Technology
Research Lab… exploring
new assem bly capabilities
ATD’s main R&D facility located in
Chandler, AZ
Our
OurMission
Mission--Identify,
Identify,Develop
Developan
anDeliver
DeliverTotal
Total
Interconnect
InterconnectSolutions
Solutionsto
toMeet
MeetIntel’s
Intel’sBusiness
BusinessNeeds
Needs
3
Intel’s Global Packaging Development
California
Folsom
Pathfinding
China
Shanghai*
Japan
Tsukuba
Stacked Package
Pathfinding
Wire Bond & Stacked Die
Development
Philippines
Cavite*
Arizona
Chandler
Flip Chip CPU Pathfinding
& Development
Core Competency Base
Malaysia
Penang*
Wire Bond &
Stacked Die
Development
Flip Chip Chipsets &
Communications
Development
Distributed
Distributedcenters
centersof
ofexcellence
excellenceworldwide
worldwide
* Also Intel Assembly and Test Site
4
From Transistors to Systems
… Innovation in All Areas
Transistor-to-Transistor
Our
OurGoal
Goal
Innovative,
Innovative,Efficient,
Efficient,High
High
Performance,
-cost
Performance,Low
Low-cost
Packages
Packagesthat
thatGives
GivesIntel
Intel
Silicon
SiliconaaSignificant
Significant
Competitive
CompetitiveAdvantage
Advantage
Chip-to-Package
Package-to-Board
Board-to-System
Convergence… Changing
the Role of Packaging
6
Convergence Driving
New Innovations
Any Time,
Anywhere,
Any Device
Demand
COMPUTING
1985
COMMUNICATIONS
1990
1995
2000
2005
Innovation
7
Logic
90nm
90nm Transistor Gate
on 0.13µm Process
Intel®
MicroSignal
Architecture
Integration via Silicon (SoC)
S
R
A
M
Flash
Power mgmt
& peripherals
0.16µm2 Flash Cell
Cell
phone
stds.
Flash+Logic
Density,
Density, Speed,
Speed, &
& Power
Power Consumption
Consumption are
are
Increasing…
Increasing… Packaging
Packaging Must
Must Adapt
Adapt to
to Manage
Manage
Integration
Integration of
of New
New Features
Features
Source: Intel
8
Converged Devices Require
Mips
Mips &
& Mbit
Mbit // milliwatt
milliwatt &
& millimeter
millimeter33
Communications
Computing
Memory
y Combination of stacking
and integration required
y x, y, z dimensions shrinking
z
x
y Bigger “M’s” and smaller
“m’s” are better
y
Convergence
Convergence Increases
Increases Silicon
Silicon Usage
Usage and
and
Need
Need for
for System
System in
in Package
Package Solutions
Solutions
9
The Solution… Intel Brings it all Together
Packages
Motherboard
Silicon
Architectural Changes to Silicon Design
Enhance Package / Substrates
Enabling Technology on Motherboards
Novel Cooling & Power Delivery Solutions
System Integration & Enabling
Power Delivery
& Heat
Removal
Systems
10
Packaging Challenges &
Innovations Intel is
Delivering
11
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches to
enable new product features
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
Goal
Goal::Bring
Bringtechnology
technologyinnovation
innovationinto
into
High
HighVolume
VolumeAssembly
Assemblyat
ataaLow
LowCost
Cost
12
Inner Layer Dielectric Strength
Silicon & Package Integration
More Complex
Time
y The Industry Challenge
y Circuit Signal Speed is impacted as silicon feature sizes are reduced
(delay is proportional to 1/RC)
y Transition to Lower K dielectric materials is required to reduce
capacitance (charging delays)
y Successful Integration of Low K Dielectric Material into Silicon &
Flip Chip Package Technologies requires a significant reduction
in Inner Layer Dielectric Stress (ILD)
13
Silicon & Package Integration
Solutions
Stress on I LD
Stress Level on ILD too High
Existing
Technology
Silicon
Process
Improvement
Stress Level on ILD OK
Assembly
Process
Improvement
Existing Process
Design &
Materials
Improvement
Stress Reduction on Inner Layer
Dielectric
New Process
Intel’s
Intel’sAssembly
AssemblyTechnology
TechnologyDevelopment
DevelopmentCapabilities
Capabilities
Enable
EnableUnderstanding
Understandingand
andIntegration
Integrationof
ofAll
AllDesign,
Design,
Process
Processand
andMaterials
MaterialsAspects
Aspects
14
Introducing the Industry’s First
90nm Low K
Organic Flip Chip Package
WE
WE ARE
ARE NOW
NOW SAMPLING
SAMPLING on
on 90nm
90nm Technology
Technology
15
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
16
Cooling
Total Package + System Solution Thermal Budget
Temp – Package
Temp – Silicon
Case (Tc)
(Tj)
Temp – Ambient
(Ta)
Temperature Gradient
Packaging
Provide Solutions
for this interface
of the budget :
Smooth out Hot Spots
OEM Heat Sink
Provide Solutions
for this interface
of the budget
Integrated
IntegratedThermal
ThermalSolutions
SolutionsIn
InThe
ThePackage
Package
Reduce
ReduceHeat
HeatFlux
Flux –– Easier
EasierTo
ToCool
CoolIn
InThe
TheSystem
System
17
Package Thermal Resistance
Cooling Complexity Increases
1
2
3
Package Thermal
Resistance
‘99
‘01
‘03
Adjusting Material Formulation
(filler size, loading, distribution)
to Improve Thermal Conductivity
Continuing to Reduce Thermal Resistance by Optimizing
Polymer Interface Material Fillers is an Industry Challenge
Intel Focused On Fundamental Materials Formulation
Research & Reducing Process Variability
18
Solder Thermal Interface Material
Heat Spreader Lid
Lid Plating
Pb-Free Solder
TIM
Thermal Interface
Material (TIM)
Back-Side Metal
Die
Die
IHS (or Lid)
PING
P
I
H
W S essors
O
N
E
RPackage
roc
A
P
E
™
W
e on
X
®
l
Inte
Introducing
Introducing––Industry’s
Industry’sFirst
FirstHigh
HighVolume
VolumeSolder
SolderThermal
Thermal
Interface
InterfaceMaterial
MaterialProcess
Processon
onOrganic
OrganicPackaging
Packaging 19
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling Complexity Increases
3. Interconnect scaling needs novel approaches
to enable new product features
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
20
Package Interconnect Scaling
I/O per mm
1999
2001
2001
2003
2005
New
New Features
Features Drive
Drive Higher
Higher
Wiring
Wiring Density
Density
Lines ~ 1/3 width of
human hair (60um)
21
Package Interconnect Scaling
Intel 845
Intel 845G
Discrete MCH
Single DDR Channel
593 Ball count/358 I/O
Integrated Graphics
Single DDR Channel
760 Ball count/368 I/O
Flip Chip BGA
1.27 mm solder ball pitch
1.00 mm solder ball pitch
Increased I/O Capability
28% Increase!
G
Intel 865G/875P
IPPIN
H
S
Integrated
WGraphics
s e ts
O
p
i
N
h
RE DDR8Channel
ADual
5P C
7
WE 932
G&
Count/529 I/O
865Ball
Intel
‘Balls Anywhere’ Pattern
& Advanced Routing Design
Increased I/O Capability 44%!
Intel Maintained Constant 37.5 mm Package Size while Increasing Features
Enhancing
EnhancingProduct
ProductFeatures
FeaturesWhile
WhileMaintaining
Maintaining
Packaging
Packagingand
andMotherboard
MotherboardTechnology
TechnologyCost
CostStructure
Structure
22
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
23
Chip Scale Packaging Trends
y Chip Scale Package Pitch Reduction to .5mm (for those
ready)
y Memory and System in Package
g
n
i
t
pu
om
C
,
y Stacked Die and Stacked Packages
ry
o
m
Me
,
e
y Last year we said they
cwere comingpace
n
a
3 s
m
r
o
f
r HERE r mm
y Now theyP- e
ARE
er
lle
t
a
a
e
m
Gr Die… Was
y Stacked
in s2 Die, Went to 3 Die, Going to 4,5,6 Die
y Thin, thin, thin
y 2002 was .150 mm die
y Now Sampling in .075 mm die
y Tomorrow…. Less than that
24
Integration via Packaging - Thinning
Thinning &
&
100%
(1.4mm Max)
% Total Thickness
Stacking
Stacking
4 Die
Stack
Package Budget
80%
60%
40%
4 Die Stack with Large
Overhang
Die Budget
20%
0%
1
2
3
4
5
6
7
8
9
Number of Stacked Die
Thin Die Enables Thinner Packages
But
But Challenges
Challenges to
to Handling,
Handling,
Bonding,
Bonding, &
& Stacking
Stacking
Die Thinning and Stacking is Critical to Achieve SIP
Intel has Developed Assembly Processes to Reduce
Overall Die and Package Thickness
25
Introducing Ultra-Thin Packaging (Intel® UT-SCSP)
• Extending the envelope with more die in less space
Ongoing
Research
• 4 to 5 Die in 1mm to 1.2 mm Package Height
• High Volume Capability with High Reliability
Intel® UT-SCSP
8 Die Stack
50 µm Die
>150 M Units
Shipped
4 to 5 Die
1 to 1.2 mm
75 µm Die Thinness
2 to 3 Die
1.2mm
125 - 175 µm Die
Thickness
2 Die
1.4mm Package Height
26
The Ultimate Flexibility
Introducing
Introducing Intel®
Intel® Folded
Folded Stacked
Stacked Chip
Chip Scale
Scale Package
Package
Industry’s First !! - Intel® Folded
Stacked Chip Scale Package
A system in Package
hat
t
2
0
n 20 ing
i
d
e
pl
unc
m
o
a
n
S
n
We A ould Be
ING
L
W
P
e
W
SAM
W
O
EN
R
A
WE
Many Configurations of Logic & Memory Possible
27
Logic - Memory System-in-a-Package
Several Flavors Being Developed
Intel® Stacked Chip Scale
Package (CSP)
ING
P
P
I
SH
263
A
X
P
62,
2
A
X
1, P
6
2
A
PX
Intel® Folded-SCSP
ING
L
P
SAM
28
Flip Chip in CSPs
Array of Flip Chip Bumps on Chip
Molded Plastic
Chip
Die Bumps
Package Substrate
Flip Chip Enables
FC-CSP with
Exposed Die
Pkg Solder
Balls
y Higher frequencies and R/F
performance
Intel® Centrino™ with
y Reduction inCommunication
package bodyDie
size
in Flip Chip CSP
y Higher I/O in smaller chip area
29
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches
4. Wireless packaging - System-in-a-package
5. The Road to Lead free
30
Industry Pb-free Challenges
y Reliability of Pb-free Solutions Across Industry at
Elevated Temperature
y Capable at Pb-free Board Process Temp. (260C Pb-free vs 220C SnPb)
y Compatibility of multiple solders in sub-components in Pb-free board
process
y Pb-free Industry Infrastructure Readiness
y Supply chain readiness Æ100% BOM availability
y Availability/ HVM capacity of Pb-free components and materials
y Management of conversion logistics and dual-line (Pb and Pb-free)
y Pb-free Platform Cost
Intel
Intelis
isCommitted
Committedto
toFinding
FindingAppropriate
Appropriateand
andCost
CostEffective
EffectiveWays
Waysto
toReduce
ReduceLead
Leadin
inits
itsProducts
Products
31
The Road to Pb-Free
y Several Pb-free products are available and shipping
today
y Intel certified its first Pb-free product in October 2001 and
shipped its first Pb-free product October 2002
y Packages include: Very Thin Profile Fine Pitch BGA (VF BGA),
Intel® Stacked Chip Scale Package , P-BGA
y Pb-free Second Level Interconnect development for
Flip-Chip Packaging technology is underway
y Focused on newer technologies under development
y Reduction of Hazardous Substances (RoHS) compliant
product introductions will occur in phases
32
Summary
33
Summary
y Many Challenges are Being Met…
y Silicon/Package Integration… Transition to new dielectric materials
y Cooling Complexity… New products require better Interface Materials
y Interconnect Scaling… New features require more interconnect
y System in Package… Thinner Die and Packages
y Road to Lead Free… Intel is committed to the Industry Challenge
Intel’s
Intel’sIntegrated
IntegratedDesign,
Design,Silicon,
Silicon, Packaging
Packaging Technology
Technology
Development
DevelopmentEnable
Enablethe
theDelivery
Deliveryof
ofOptimized
OptimizedSolutions
Solutions
into
intoHigh
HighVolume
Volume
34
For more information, please visit ….
http://www.intel.com/research/silicon/packaging.htm
http://developer.intel.com/technology/itj/
Search for packaging articles
35
Innovations to Enable
Future Products
Introducing
Introducing the
the Industry’s
Industry’s First
First 90nm
90nm -- Low
Low K
K
Organic
Organic Flip
Flip Chip
Chip Package
Package
Dan Belton & Johanna Swan
Assembly Technology Development
Technology Manufacturing Group
Chandler, Arizona
1
Agenda
y Packaging @ Intel
y Convergence… Changing the Role of
Packaging
y Packaging Challenges & Innovations Intel
is Delivering
y Summary
2
Assembly Technology Development
Chandler Campus
Printing
Pick & Place
Dispense
W ire
Bonder
The Assem bly Technology
Research Lab… exploring
new assem bly capabilities
ATD’s main R&D facility located in
Chandler, AZ
Our
OurMission
Mission--Identify,
Identify,Develop
Developan
anDeliver
DeliverTotal
Total
Interconnect
InterconnectSolutions
Solutionsto
toMeet
MeetIntel’s
Intel’sBusiness
BusinessNeeds
Needs
3
Intel’s Global Packaging Development
California
Folsom
Pathfinding
China
Shanghai*
Japan
Tsukuba
Stacked Package
Pathfinding
Wire Bond & Stacked Die
Development
Philippines
Cavite*
Arizona
Chandler
Flip Chip CPU Pathfinding
& Development
Core Competency Base
Malaysia
Penang*
Wire Bond &
Stacked Die
Development
Flip Chip Chipsets &
Communications
Development
Distributed
Distributedcenters
centersof
ofexcellence
excellenceworldwide
worldwide
* Also Intel Assembly and Test Site
4
From Transistors to Systems
… Innovation in All Areas
Transistor-to-Transistor
Our
OurGoal
Goal
Innovative,
Innovative,Efficient,
Efficient,High
High
Performance,
-cost
Performance,Low
Low-cost
Packages
Packagesthat
thatGives
GivesIntel
Intel
Silicon
SiliconaaSignificant
Significant
Competitive
CompetitiveAdvantage
Advantage
Chip-to-Package
Package-to-Board
Board-to-System
Convergence… Changing
the Role of Packaging
6
Convergence Driving
New Innovations
Any Time,
Anywhere,
Any Device
Demand
COMPUTING
1985
COMMUNICATIONS
1990
1995
2000
2005
Innovation
7
Logic
90nm
90nm Transistor Gate
on 0.13µm Process
Intel®
MicroSignal
Architecture
Integration via Silicon (SoC)
S
R
A
M
Flash
Power mgmt
& peripherals
0.16µm2 Flash Cell
Cell
phone
stds.
Flash+Logic
Density,
Density, Speed,
Speed, &
& Power
Power Consumption
Consumption are
are
Increasing…
Increasing… Packaging
Packaging Must
Must Adapt
Adapt to
to Manage
Manage
Integration
Integration of
of New
New Features
Features
Source: Intel
8
Converged Devices Require
Mips
Mips &
& Mbit
Mbit // milliwatt
milliwatt &
& millimeter
millimeter33
Communications
Computing
Memory
y Combination of stacking
and integration required
y x, y, z dimensions shrinking
z
x
y Bigger “M’s” and smaller
“m’s” are better
y
Convergence
Convergence Increases
Increases Silicon
Silicon Usage
Usage and
and
Need
Need for
for System
System in
in Package
Package Solutions
Solutions
9
The Solution… Intel Brings it all Together
Packages
Motherboard
Silicon
Architectural Changes to Silicon Design
Enhance Package / Substrates
Enabling Technology on Motherboards
Novel Cooling & Power Delivery Solutions
System Integration & Enabling
Power Delivery
& Heat
Removal
Systems
10
Packaging Challenges &
Innovations Intel is
Delivering
11
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches to
enable new product features
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
Goal
Goal::Bring
Bringtechnology
technologyinnovation
innovationinto
into
High
HighVolume
VolumeAssembly
Assemblyat
ataaLow
LowCost
Cost
12
Inner Layer Dielectric Strength
Silicon & Package Integration
More Complex
Time
y The Industry Challenge
y Circuit Signal Speed is impacted as silicon feature sizes are reduced
(delay is proportional to 1/RC)
y Transition to Lower K dielectric materials is required to reduce
capacitance (charging delays)
y Successful Integration of Low K Dielectric Material into Silicon &
Flip Chip Package Technologies requires a significant reduction
in Inner Layer Dielectric Stress (ILD)
13
Silicon & Package Integration
Solutions
Stress on I LD
Stress Level on ILD too High
Existing
Technology
Silicon
Process
Improvement
Stress Level on ILD OK
Assembly
Process
Improvement
Existing Process
Design &
Materials
Improvement
Stress Reduction on Inner Layer
Dielectric
New Process
Intel’s
Intel’sAssembly
AssemblyTechnology
TechnologyDevelopment
DevelopmentCapabilities
Capabilities
Enable
EnableUnderstanding
Understandingand
andIntegration
Integrationof
ofAll
AllDesign,
Design,
Process
Processand
andMaterials
MaterialsAspects
Aspects
14
Introducing the Industry’s First
90nm Low K
Organic Flip Chip Package
WE
WE ARE
ARE NOW
NOW SAMPLING
SAMPLING on
on 90nm
90nm Technology
Technology
15
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
16
Cooling
Total Package + System Solution Thermal Budget
Temp – Package
Temp – Silicon
Case (Tc)
(Tj)
Temp – Ambient
(Ta)
Temperature Gradient
Packaging
Provide Solutions
for this interface
of the budget :
Smooth out Hot Spots
OEM Heat Sink
Provide Solutions
for this interface
of the budget
Integrated
IntegratedThermal
ThermalSolutions
SolutionsIn
InThe
ThePackage
Package
Reduce
ReduceHeat
HeatFlux
Flux –– Easier
EasierTo
ToCool
CoolIn
InThe
TheSystem
System
17
Package Thermal Resistance
Cooling Complexity Increases
1
2
3
Package Thermal
Resistance
‘99
‘01
‘03
Adjusting Material Formulation
(filler size, loading, distribution)
to Improve Thermal Conductivity
Continuing to Reduce Thermal Resistance by Optimizing
Polymer Interface Material Fillers is an Industry Challenge
Intel Focused On Fundamental Materials Formulation
Research & Reducing Process Variability
18
Solder Thermal Interface Material
Heat Spreader Lid
Lid Plating
Pb-Free Solder
TIM
Thermal Interface
Material (TIM)
Back-Side Metal
Die
Die
IHS (or Lid)
PING
P
I
H
W S essors
O
N
E
RPackage
roc
A
P
E
™
W
e on
X
®
l
Inte
Introducing
Introducing––Industry’s
Industry’sFirst
FirstHigh
HighVolume
VolumeSolder
SolderThermal
Thermal
Interface
InterfaceMaterial
MaterialProcess
Processon
onOrganic
OrganicPackaging
Packaging 19
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling Complexity Increases
3. Interconnect scaling needs novel approaches
to enable new product features
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
20
Package Interconnect Scaling
I/O per mm
1999
2001
2001
2003
2005
New
New Features
Features Drive
Drive Higher
Higher
Wiring
Wiring Density
Density
Lines ~ 1/3 width of
human hair (60um)
21
Package Interconnect Scaling
Intel 845
Intel 845G
Discrete MCH
Single DDR Channel
593 Ball count/358 I/O
Integrated Graphics
Single DDR Channel
760 Ball count/368 I/O
Flip Chip BGA
1.27 mm solder ball pitch
1.00 mm solder ball pitch
Increased I/O Capability
28% Increase!
G
Intel 865G/875P
IPPIN
H
S
Integrated
WGraphics
s e ts
O
p
i
N
h
RE DDR8Channel
ADual
5P C
7
WE 932
G&
Count/529 I/O
865Ball
Intel
‘Balls Anywhere’ Pattern
& Advanced Routing Design
Increased I/O Capability 44%!
Intel Maintained Constant 37.5 mm Package Size while Increasing Features
Enhancing
EnhancingProduct
ProductFeatures
FeaturesWhile
WhileMaintaining
Maintaining
Packaging
Packagingand
andMotherboard
MotherboardTechnology
TechnologyCost
CostStructure
Structure
22
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches
4. Chip Scale Packaging - System-in-a-package
5. The Road to Lead free
23
Chip Scale Packaging Trends
y Chip Scale Package Pitch Reduction to .5mm (for those
ready)
y Memory and System in Package
g
n
i
t
pu
om
C
,
y Stacked Die and Stacked Packages
ry
o
m
Me
,
e
y Last year we said they
cwere comingpace
n
a
3 s
m
r
o
f
r HERE r mm
y Now theyP- e
ARE
er
lle
t
a
a
e
m
Gr Die… Was
y Stacked
in s2 Die, Went to 3 Die, Going to 4,5,6 Die
y Thin, thin, thin
y 2002 was .150 mm die
y Now Sampling in .075 mm die
y Tomorrow…. Less than that
24
Integration via Packaging - Thinning
Thinning &
&
100%
(1.4mm Max)
% Total Thickness
Stacking
Stacking
4 Die
Stack
Package Budget
80%
60%
40%
4 Die Stack with Large
Overhang
Die Budget
20%
0%
1
2
3
4
5
6
7
8
9
Number of Stacked Die
Thin Die Enables Thinner Packages
But
But Challenges
Challenges to
to Handling,
Handling,
Bonding,
Bonding, &
& Stacking
Stacking
Die Thinning and Stacking is Critical to Achieve SIP
Intel has Developed Assembly Processes to Reduce
Overall Die and Package Thickness
25
Introducing Ultra-Thin Packaging (Intel® UT-SCSP)
• Extending the envelope with more die in less space
Ongoing
Research
• 4 to 5 Die in 1mm to 1.2 mm Package Height
• High Volume Capability with High Reliability
Intel® UT-SCSP
8 Die Stack
50 µm Die
>150 M Units
Shipped
4 to 5 Die
1 to 1.2 mm
75 µm Die Thinness
2 to 3 Die
1.2mm
125 - 175 µm Die
Thickness
2 Die
1.4mm Package Height
26
The Ultimate Flexibility
Introducing
Introducing Intel®
Intel® Folded
Folded Stacked
Stacked Chip
Chip Scale
Scale Package
Package
Industry’s First !! - Intel® Folded
Stacked Chip Scale Package
A system in Package
hat
t
2
0
n 20 ing
i
d
e
pl
unc
m
o
a
n
S
n
We A ould Be
ING
L
W
P
e
W
SAM
W
O
EN
R
A
WE
Many Configurations of Logic & Memory Possible
27
Logic - Memory System-in-a-Package
Several Flavors Being Developed
Intel® Stacked Chip Scale
Package (CSP)
ING
P
P
I
SH
263
A
X
P
62,
2
A
X
1, P
6
2
A
PX
Intel® Folded-SCSP
ING
L
P
SAM
28
Flip Chip in CSPs
Array of Flip Chip Bumps on Chip
Molded Plastic
Chip
Die Bumps
Package Substrate
Flip Chip Enables
FC-CSP with
Exposed Die
Pkg Solder
Balls
y Higher frequencies and R/F
performance
Intel® Centrino™ with
y Reduction inCommunication
package bodyDie
size
in Flip Chip CSP
y Higher I/O in smaller chip area
29
Packaging Challenges
1. Industry Silicon & Package integration becomes
more complex at 90nm and beyond
2. Cooling complexity increases
3. Interconnect scaling needs novel approaches
4. Wireless packaging - System-in-a-package
5. The Road to Lead free
30
Industry Pb-free Challenges
y Reliability of Pb-free Solutions Across Industry at
Elevated Temperature
y Capable at Pb-free Board Process Temp. (260C Pb-free vs 220C SnPb)
y Compatibility of multiple solders in sub-components in Pb-free board
process
y Pb-free Industry Infrastructure Readiness
y Supply chain readiness Æ100% BOM availability
y Availability/ HVM capacity of Pb-free components and materials
y Management of conversion logistics and dual-line (Pb and Pb-free)
y Pb-free Platform Cost
Intel
Intelis
isCommitted
Committedto
toFinding
FindingAppropriate
Appropriateand
andCost
CostEffective
EffectiveWays
Waysto
toReduce
ReduceLead
Leadin
inits
itsProducts
Products
31
The Road to Pb-Free
y Several Pb-free products are available and shipping
today
y Intel certified its first Pb-free product in October 2001 and
shipped its first Pb-free product October 2002
y Packages include: Very Thin Profile Fine Pitch BGA (VF BGA),
Intel® Stacked Chip Scale Package , P-BGA
y Pb-free Second Level Interconnect development for
Flip-Chip Packaging technology is underway
y Focused on newer technologies under development
y Reduction of Hazardous Substances (RoHS) compliant
product introductions will occur in phases
32
Summary
33
Summary
y Many Challenges are Being Met…
y Silicon/Package Integration… Transition to new dielectric materials
y Cooling Complexity… New products require better Interface Materials
y Interconnect Scaling… New features require more interconnect
y System in Package… Thinner Die and Packages
y Road to Lead Free… Intel is committed to the Industry Challenge
Intel’s
Intel’sIntegrated
IntegratedDesign,
Design,Silicon,
Silicon, Packaging
Packaging Technology
Technology
Development
DevelopmentEnable
Enablethe
theDelivery
Deliveryof
ofOptimized
OptimizedSolutions
Solutions
into
intoHigh
HighVolume
Volume
34
For more information, please visit ….
http://www.intel.com/research/silicon/packaging.htm
http://developer.intel.com/technology/itj/
Search for packaging articles
35