Teknik digital
COMBINATIONAL LOGIC FUNCTIONS Contents
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.2 A Half-Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.3 A Full-Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
9.4 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
9.5 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9.6 Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
9.7 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
9.8 Using multiple combinational circuits . . . . . . . . . . . . . . . . . . . . . 294
Original author: David Zitzelsberger
9.1 Introduction
The term ”combinational” comes to us from mathematics. In mathematics a combination is an unordered set, which is a formal way to say that nobody cares which order the items came in. Most games work this way, if you rolled dice one at a time and get a 2 followed by a 3 it is the same as if you had rolled a 3 followed by a 2. With combinational logic, the circuit produces the same output regardless of the order the inputs are changed. There are circuits which depend on the when the inputs change, these circuits are called sequential logic. Even though you will not find the term ”sequential logic” in the chapter titles, the next several chapters will discuss sequential logic. Practical circuits will have a mix of combinational and sequential logic, with sequential logic making sure everything happens in order and combinational logic performing functions like arithmetic, logic, or conversion.
274
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS You have already used combinational circuits. Each logic gate discussed previously is a combinational logic function. Lets follow how two NAND gate works if we provide them inputs in different orders. We begin with both inputs being 0.
00
1
1 We then set one input high.
10
1
1 We then set the other input high.
11 So NAND gates do not care about the order of the inputs, and you will find the same true of all the other gates covered up to this point (AND, XOR, OR, NOR, XNOR, and NOT).
9.2 A Half-Adder
As a first example of useful combinational logic, let’s build a device that can add two binary digits together. We can quickly calculate what the answers should be:
9.3. A FULL-ADDER 275
0+0=00+1=11+0=11 + 1 = 10
2 So we well need two inputs (a and b) and two outputs. The low order output will be called
because it represents the sum, and the high order output will be called C out because it represents the carry out. The truth table is out
C A B
00
10
1
10
1
01
1
1 Simplifying boolean equations or making some Karnaugh map will produce the same circuit
shown below, but start by looking at the results. The column is our familiar XOR gate, while the C out column is the AND gate. This device is called a half-adder for reasons that will make sense in the next section.
A B out
C
or in ladder logic
1
2 L L A B
A B out
A B C
9.3 A Full-Adder The half-adder is extremely useful until you want to add more that one binary digit quantities.
The slow way to develop a two binary digit adders would be to make a truth table and reduce it. Then when you decide to make a three binary digit adder, do it again. Then when you decide to
276
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS make a four digit adder, do it again. Then when ... The circuits would be fast, but development time would be slow. Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits.
11
11
11
- 110
Look at how many inputs the middle column uses. Our adder needs three inputs; a, b, and the carry from the previous sum, and we can use our two-input adder to build a three input adder. is the easy part. Normal arithmetic tells us that if = a + b + C in and
1 = a + b, then
= 1 + C in .
1 A
HA
1 B C
HA C
2 in
C
1
2 L L
1 A B A B
1 A B C
1
C in
1 C in
1 C in C
2 What do we do with C 1 and C 2 ? Let’s look at three input sums and quickly calculate:
C in + a + b = ? 0+0+0=00+0+1= 10+1+0= 1 1 + 1 = 10
0+
9.3. A FULL-ADDER 277
1+0+0=1 1 + 0 + 1 = 10 1 + 1 + 0 = 10 1+ 1 + 1 = 11 If you have any concern about the low order bit, please confirm that the circuit and ladder calculate it correctly.
In order to calculate the high order bit, notice that it is 1 in both cases when a + b produces a C
1 . Also, the high order bit is 1 when a + b produces a 1 and C in is a 1. So We will have a
carry when C
1 OR (
1 AND C in ). Our complete three input adder is:
1 A
HA B HA
in
C
out
C
1
2 L L
1 A B A B
1 A B C
1
C in
1 C in
1 C in C
2
1 2 out
C C C
For some designs, being able to eliminate one or more types of gates can be important, and you can replace the final OR gate with an XOR gate without changing the results.
278
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS
A
HA
B
1
1 A
FA C out B
1
1
2 L L
A B
A B
1 A B C
1
1
1 A B T
1
1 A B
1
1
1 A B TC
1
1
1 T C
1
1 T C
1
1
1 T C TP
1 1 out TC TP C
A is the low order bit of A, A
1 is the high order bit of A, B is the low order bit of B, B 1 is
the high order bit of B, is the low order bit of the sum,
1 is the high order bit of the sum, and C out is the Carry.
A two binary digit adder would never be made this way. Instead the lowest order bits would also go through a full adder too.
9.3. A FULL-ADDER 279 in
C A FA B
1 A
1 FA out
C
1 B
280
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS L
1 A
1 A
1 C
whether the lowest order carry should be included in the sum. This allows for the chaining of even larger sums. Consider two different ways to look at a four bit sum. 1111<-+ 11<+- 0110| 01 | 10 1011| 10 | 11
2 There are several reasons for this, one being that we can then allow a circuit to determine
T L
1 T 1 TC
1 TP C
1
TC
1 C out
1 TP
1 TP
1 C
1 C
1 A
A A T T TC TC A
1 B
TP B
in
C
in
C
in
B B C
1 B
1 T 1 T 1 T 1 TC
1 B
9.3. A FULL-ADDER 281
- | --- | --- 100011 +-100 +-101
If we allow the program to add a two bit number and remember the carry for later, then use that carry in the next sum the program can add any number of bits the user wants even though we have only provided a two-bit adder. Small PLCs can also be chained together for larger numbers. These full adders can also can be expanded to any number of bits space allows. As an example, here’s how to do an 8 bit adder.
1 2
3
4 5 6 7 out C in
C FA FA FA FA FA FA FA FA
1
1
2
2
3
3
4
4
5
5
6
6
7
7 A B A B A B A B A B A B A B A B
This is the same result as using the two 2-bit adders to make a 4-bit adder and then us- ing two 4-bit adders to make an 8-bit adder or re-duplicating ladder logic and updating the numbers. 7
1 2 3 4 5 6 out C
in FA FA FA FA FA FA FA FA
C 2+ 2+ 2+ 2+
4+ 4+
1
1
2
2
3
3
4
4
5
5
6
6
7
7 A B A B A B A B A B A B A B A B
Each ”2+” is a 2-bit adder and made of two full adders. Each ”4+” is a 4-bit adder and made of two 2-bit adders. And the result of two 4-bit adders is the same 8-bit adder we used full adders to build. For any large combinational circuit there are generally two approaches to design: you can take simpler circuits and replicate them; or you can design the complex circuit as a complete device. Using simpler circuits to build complex circuits allows a you to spend less time designing but then requires more time for signals to propagate through the transistors. The 8-bit adder design above has to wait for all the Cxout signals to move from A + B up to the inputs of 7 . If a designer builds an 8-bit adder as a complete device simplified to a sum of products, then each signal just travels through one NOT gate, one AND gate and one OR gate. A seventeen input device has a truth table with 131,072 entries, and reducing 131,072 entries to a sum of products will take some time. When designing for systems that have a maximum allowed response time to provide the final result, you can begin by using simpler circuits and then attempt to replace portions of the circuit that are too slow. That way you spend most of your time on the portions of a circuit that matter.
282
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS
9.4 Decoder
A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the reverse of encoding, but we will begin our study of encoders and decoders with decoders because they are simpler to design. A common type of decoder is the line decoder which takes an n-digit binary number and
n
decodes it into 2 data lines. The simplest is the 1-to-2 line decoder. The truth table is
1 A D D
001 11 0
A is the address and D is the dataline. D is NOT A and D
1 is A. The circuit looks like A D
1 D
L
1 L
2 A D
1 A D Only slightly more complex is the 2-to-4 line decoder. The truth table is
1
3
2
1 A A D D D D
00
1
01
1
10
1
11
1
9.4. DECODER 283
A A
1 D
1 D
2 D
3 L
1 A
1 A
D
1 A
1 A
A A A D D
1 D
2 D
3 L
2 Larger line decoders can be designed in a similar fashion, but just like with the binary adder there is a way to make larger decoders by combining smaller decoders. An alternate circuit for the 2-to-4 line decoder is
1 A
284
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS D A
1-to-2 Decoder
1 D
A
1
1-to-2 Decoder
2 D
D
3 Replacing the 1-to-2 Decoders with their circuits will show that both circuits are equivalent.
In a similar fashion a 3-to-8 line decoder can be made from a 1-to-2 line decoder and a 2-to-4 line decoder, and a 4-to-16 line decoder can be made from two 2-to-4 line decoders.
You might also consider making a 2-to-4 decoder ladder from 1-to-2 decoder ladders. If you do it might look something like this:
9.4. DECODER 285
1
2 L L
A T 0,0
0,1
A T
1 1,0
A T
A1 T 1,1 1,0 0,0
T T D
1,0 0,1
1 T T D 1,1 0,0
2 T T D 1,1 0,1
3 T T D For some logic it may be required to build up logic like this. For an eight-bit adder we only know how to sum eight bits by summing one bit at a time. Usually it is easier to design ladder logic from boolean equations or truth tables rather than design logic gates and then ”translate” that into ladder logic. A typical application of a line decoder circuit is to select among multiple devices. A circuit needing to select among sixteen devices could have sixteen control lines to select which device should ”listen”. With a decoder only four control lines are needed.
286
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS
9.5 Encoder
An encoder is a circuit that changes a set of signals into a code. Lets begin making a 2-to-1 line encoder truth table by reversing the 1-to-2 decoder truth table.
1 D D A
10
1
01 table.
This truth table is a little short. A complete truth table would be
1 D D A
10
1
01
1
1 One question we need to answer is what to do with those other inputs? Do we ignore them?
Do we have them generate an additional error output? In many circuits this problem is solved by adding sequential logic in order to know not just what input is active but also which order the inputs became active.
A more useful application of combinational encoder design is a binary to 7-segment encoder. The seven segments are given according
D
1
2 D D
D
3
4 D
5 D
6 D
01
1
01
1
1
1
1
01
1
01
01
01
01
1
1
1
01
01
1
01
01
1
1
01
01
01
01
01
1
1
01
1
01
01
1
1
9.5. ENCODER 287
I
3 I
2 I
1 I D
6 D
5 D
4 D
3 D
2 D
1 D
01
1
1
01
01
1
1
1
1
1
1
1
1
01
1
1
01
1
1
1
01
01 Deciding what to do with the remaining six entries of the truth table is easier with this
- I
- I
- I
- I
- I
- I
= I
D
3
= I
3
1 I + I
2 I
1 D
4
= I
1 I + I
2 I
1 I
D
5
3
2 I
2
6
= I
3
1 I + I
3 I
2 I
1
3 I
2 I
1 I + I
3 I
2 I
1 I and the circuit is
1 I
3 I
1
1 I
01
1
1
1
1
circuit. This circuit should not be expected to encode an undefined combination of inputs, so we can leave them as ”don’t care” when we design the circuit. The boolean equations are
D = I
3
1
3 I
2 I
1 I + I
3 I
2 I
D
1 I + I
1
= I
3
2 I
1
2 I
1
2 I
D
2
= I
2
3 I
2 I
- I
- I
- I D
- I
- I
288
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS D D
3 D
1 D
4
D2 I
1 Figure 9.1: Seven-segment decoder gate level diagram.
I I
2 I
3
D5 D
6
9.6. DEMULTIPLEXERS
L 1 I 3 I 1 I 3 I 3 I 3 I 2 I 2 I 2 I 2 I 3 I 3 I 3 I 1 I 2 I 1 I 2 I 3 I 2 I
I 3 I 1 I 3 I 3 I 3 I
I 2 I 2 I 2 I 1 I 1 I 1 I
I D 6 I
I 1 I
I 1 I D 5 D 4 I 2 I 2 I 1 I 1 I
I D 3 I 1 I 1 I D 2 I 2 I 2 I 1 I 1 I
I D 1 D L 2
289
9.6 Demultiplexers
A demultiplexer, sometimes abbreviated dmux, is a circuit that has one input and more than one output. It is used when a circuit wishes to send a signal to one of many devices. This
290
1
1
I D D
1 Using our 1-to-2 decoder as part of the circuit, we can express this circuit easily
1
1 D
1 D
1 A
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS description sounds similar to the description given for a decoder, but a decoder is used to select among many devices while a demultiplexer is used to send a signal among many devices.
1
1 I
D D
The truth table for a 1-to-2 demultiplexer is
I A
A demultiplexer is used often enough that it has its own schematic symbol
1-to-2 line
decoder9.6. DEMULTIPLEXERS 291
1
2 L L
I A D
1 A D This circuit can be expanded two different ways. You can increase the number of signals that get transmitted, or you can increase the number of inputs that get passed through. To increase the number of inputs that get passed through just requires a larger line decoder. Increasing the number of signals that get transmitted is even easier. As an example, a device that passes one set of two signals among four signals is a ”two-bit 1-to-2 demultiplexer”. Its circuit is
I D
1 I
2 D
D
1
3 D
1-to-2 1-to-2 decoder decoder A
292
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS I D D
1 D
2 D
3 A
I
1 L
1 I A
A
I
A
D D1 D
2 D
3 L
2 shows that it could be two one-bit 1-to-2 demultiplexers without changing its expected be- havior. A 1-to-4 demultiplexer can easily be built from 1-to-2 demultiplexers as follows.
1 A
9.7. MULTIPLEXERS 293
9.7 Multiplexers A multiplexer, abbreviated mux, is a device that has multiple inputs and one output.
The schematic symbol for multiplexers is
I D
1 I
A
The truth table for a 2-to-1 multiplexer is
I A D
1 I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Using a 1-to-2 decoder as part of the circuit, we can express this circuit easily.
I D
I
1
1-to-2 line decoder
294
CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS
1
2 L L
A
I D
I
Multiplexers can also be expanded with the same naming conventions as demultiplexers. A1 A
4-to-1 multiplexer circuit is That is the formal definition of a multiplexer. Informally, there is a lot of confusion. Both demultiplexers and multiplexers have similar names, abbreviations, schematic symbols and circuits, so confusion is easy. The term multiplexer, and the abbreviation mux, are often used to also mean a demultiplexer, or a multiplexer and a demultiplexer working together. So when you hear about a multiplexer, it may mean something quite different.
9.8 Using multiple combinational circuits
As an example of using several circuits together, we are going to make a device that will have 16 inputs, representing a four digit number, to a four digit 7-segment display but using just one binary-to-7-segment encoder.
First, the overall architecture of our circuit provides what looks like our the description provided.
9.8. USING MULTIPLE COMBINATIONAL CIRCUITS 295
7-segment encoder
Follow this circuit through and you can confirm that it matches the description given above. There are 16 primary inputs. There are two more inputs used to select which digit will be displayed. There are 28 outputs to control the four digit 7-segment display. Only four of the primary inputs are encoded at a time. You may have noticed a potential question though.
When one of the digits are selected, what do the other three digits display? Review the circuit for the demultiplexers and notice that any line not selected by the A input is zero. So the other three digits are blank. We don’t have a problem, only one digit displays at a time.
Let’s get a perspective on just how complex this circuit is by looking at the equivalent ladder logic.
296 L 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 I 3 I 1 I 3 I 3 I 3 I 2 I 2 I 2 I 2 I 3 I 3 I 3 I 1 I 2 I 1 I 2 I 3 I 2 I x I I 1 I I 1 I D 5 D 4 I 2 I 2 I 1 I 1 I I D 3 I 1 I 1 I D 2 I 2 I 2 I 1 I 1 I I D A 1 A A A A A A A A A A A A A A A D 0,0 D 1,0 D 2,0 D 3,0 D 0,1 D 1,1 D 2,1 D 3,1 D 0,2 D 1,2 D 2,2 D 3,2 D 0,3 D 1,3 D 2,3 D 3,3 I CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS L 2 x
I I I I 1 I 1 I 1 I 1 I 2 I 2 I 2 I 2 I 3 I 3 I 3 I 3 D I 3 I 1 I 3 I 3 I 3 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 A 1 I I 2 I 2 I A 2 A A A A A A A A A A A A A A A A A A A A A A A A A A A I 1 I 1 I D 1 D D D D 1 D 1 D 1 D 1 D 2 D 2 D 2 D 2 D 3 D 3 D 3 D 3 D 4 D 4 D 4 D 4 D 5 D 5 D 5 D 5 D 6 D 6 D 6 D 6 I I Q 0,0 Q 0,1 Q 0,2 Q 0,3 Q 1,0 Q 1,1 Q 1,2 Q 1,3 Q 2,0 Q 2,1 Q 2,2 Q 2,3 Q 3,0 Q 3,1 Q 3,2 Q 3,3 Q 4,0 Q 4,1 Q 4,2 Q 4,3 Q 5,0 Q 5,1 Q 5,2 Q 5,3 Q 6,0 Q 6,1 Q 6,2 Q 6,3 D 6 xx xx
Notice how quickly this large circuit was developed from smaller parts. This is true of most complex circuits: they are composed of smaller parts allowing a designer to abstract away some complexity and understand the circuit as a whole. Sometimes a designer can even take components that others have designed and remove the detail design work. In addition to the added quantity of gates, this design suffers from one additional weakness. You can only see one display one digit at a time. If there was some way to rotate through the
9.8. USING MULTIPLE COMBINATIONAL CIRCUITS 297 four digits quickly, you could have the appearance of all four digits being displayed at the same time. That is a job for a sequential circuit, which is the subject of the next several chapters.
COUNTERS Contents
11.1 Binary count sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
11.2 Asynchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
11.3 Synchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
11.4 Counter modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
- INCOMPLETE ***
11.1 Binary count sequence
If we examine a four-bit binary count sequence from 0000 to 1111, a definite pattern will be evident in the ”oscillations” of the bits between 0 and 1:
324 CHAPTER 11. COUNTERS
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Note how the least significant bit (LSB) toggles between 0 and 1 for every step in the count sequence, while each succeeding bit toggles at one-half the frequency of the one before it. The most significant bit (MSB) only toggles once during the entire sixteen-step count sequence: at the transition between 7 (0111) and 8 (1000).
If we wanted to design a digital circuit to ”count” in four-bit binary, all we would have to do is design a series of frequency divider circuits, each circuit dividing the frequency of a square-wave pulse by a factor of 2:
1
1
1
1
1
1
1
1 (LSB)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 (MSB) 0
J-K flip-flops are ideally suited for this task, because they have the ability to ”toggle” their output state at the command of a clock pulse when both J and K inputs are made ”high” (1):
11.2. ASYNCHRONOUS COUNTERS 325
Vdd signal B J Q signal A
C
K Q A1
1
1
1
1
1 B
1
1
1
1
1
1 If we consider the two signals (A and B) in this circuit to represent two bits of a binary
number, signal A being the LSB and signal B being the MSB, we see that the count sequence is backward: from 11 to 10 to 01 to 00 and back again to 11. Although it might not be counting in the direction we might have assumed, at least it counts! The following sections explore different types of counter circuits, all made with J-K flip- flops, and all based on the exploitation of that flip-flop’s toggle mode of operation.
- REVIEW:
- Binary count sequences follow a pattern of octave frequency division: the frequency of oscillation for each bit, from LSB to MSB, follows a divide-by-two pattern. In other words, the LSB will oscillate at the highest frequency, followed by the next bit at one-half the LSB’s frequency, and the next bit at one-half the frequency of the bit before it, etc.
- Circuits may be built that ”count” in a binary sequence, using J-K flip-flops set up in the ”toggle” mode.
11.2 Asynchronous counters
In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two- bit binary sequence, from 11 to 10 to 01 to 00. Since it would be desirable to have a circuit that could count forward and not just backward, it would be worthwhile to examine a forward count sequence again and look for more patterns that might indicate how to build such a circuit. Since we know that binary count sequences follow a pattern of octave (factor of 2) fre- quency division, and that J-K flip-flop multivibrators set up for the ”toggle” mode are capable of performing this type of frequency division, we can envision a circuit made up of several J-K flip-flops, cascaded to produce four bits of output. The main problem facing us is to determine how to connect these flip-flops together so that they toggle at the right times to produce the
326 CHAPTER 11. COUNTERS proper binary sequence. Examine the following binary count sequence, paying attention to patterns preceding the ”toggling” of a bit between 0 and 1:
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Note that each bit in this four-bit sequence toggles when the bit before it (the bit having a lesser significance, or place-weight), toggles in a particular direction: from 1 to 0. Small arrows indicate those points in the sequence where a bit toggles, the head of the arrow pointing to the previous bit transitioning from a ”high” (1) state to a ”low” (0) state:
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Starting with four J-K flip-flops connected in such a way to always be in the ”toggle” mode, we need to determine how to connect the clock inputs in such a way so that each succeeding bit toggles when the bit before it transitions from 1 to 0. The Q outputs of each flip-flop will serve
11.2. ASYNCHRONOUS COUNTERS 327 as the respective binary bits of the final, four-bit count:
Q Q Q Q 1 2 3 Vdd Vdd Vdd Vdd J Q J Q J Q J Q C C C C
? ? ? K Q K Q K Q K Q
If we used flip-flops with negative-edge triggering (bubble symbols on the clock inputs), we could simply connect the clock input of each flip-flop to the Q output of the flip-flop before it, so that when the bit before it changes from a 1 to a 0, the ”falling edge” of that signal would ”clock” the next flip-flop to toggle the next bit:
A four-bit "up" counter
Q Q 1 Q 2 Q 3 Vdd Vdd Vdd Vdd J Q J Q J Q J Q C C C C K Q K Q K Q K QThis circuit would yield the following output waveforms, when ”clocked” by a repetitive source of pulses from an oscillator:
Clock Q
1
1
1
1
1
1
1
1 Q
1
1
1
1
1
1
1
1
1 Q
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3 Q
1 The first flip-flop (the one with the Q output), has a positive-edge triggered clock input,
so it toggles with each rising edge of the clock signal. Notice how the clock signal in this example has a duty cycle less than 50%. I’ve shown the signal in this manner for the purpose of
328 CHAPTER 11. COUNTERS demonstrating how the clock signal need not be symmetrical to obtain reliable, ”clean” output bits in our four-bit binary sequence. In the very first flip-flop circuit shown in this chapter, I used the clock signal itself as one of the output bits. This is a bad practice in counter design, though, because it necessitates the use of a square wave signal with a 50% duty cycle (”high” time = ”low” time) in order to obtain a count sequence where each and every step pauses for the same amount of time. Using one J-K flip-flop for each output bit, however, relieves us of the necessity of having a symmetrical clock signal, allowing the use of practically any variety of high/low waveform to increment the count sequence.
As indicated by all the other arrows in the pulse diagram, each succeeding output bit is toggled by the action of the preceding bit transitioning from ”high” (1) to ”low” (0). This is the pattern necessary to generate an ”up” count sequence.
A less obvious solution for generating an ”up” sequence using positive-edge triggered flip- flops is to ”clock” each flip-flop using the Q’ output of the preceding flip-flop rather than the Q output. Since the Q’ output will always be the exact opposite state of the Q output on a J-K flip-flop (no invalid states with this type of flip-flop), a high-to-low transition on the Q output will be accompanied by a low-to-high transition on the Q’ output. In other words, each time the Q output of a flip-flop transitions from 1 to 0, the Q’ output of the same flip-flop will transition from 0 to 1, providing the positive-going clock pulse we would need to toggle a positive-edge triggered flip-flop at the right moment:
A different way of making a four-bit "up" counter
Q Q Q Q 1 2 3 Vdd Vdd Vdd Vdd J Q J Q J Q J QC C C C
K Q K Q K Q K QOne way we could expand the capabilities of either of these two counter circuits is to regard the Q’ outputs as another set of four binary bits. If we examine the pulse diagram for such a circuit, we see that the Q’ outputs generate a down-counting sequence, while the Q outputs generate an up-counting sequence:
11.2. ASYNCHRONOUS COUNTERS 329
A simultaneous "up" and "down" counter Q Q 1 Q 2 Q 3 Vdd Vdd Vdd Vdd J Q J Q J Q J Q C C C C K Q K Q K Q K Q Q Q 1 Q 2 Q 3
"Up" count sequence Q
1
1
1
1
1
1
1
1 Q
1
1
1
1
1
1
1
1
1 Q
2
1
1
1
1
1
1
1
1 Q
3
1
1
1
1
1
1
1
1 "Down" count sequence Q
1
1
1
1
1
1
1
1 Q
1
1
1
1
1
1
1
1
1 Q
2
1
1
1
1
1
1
1
1 Q
3
1
1
1
1
1
1
1
1 Unfortunately, all of the counter circuits shown thusfar share a common problem: the ripple
effect. This effect is seen in certain types of binary adder and data conversion circuits, and is due to accumulative propagation delays between cascaded gates. When the Q output of a flip- flop transitions from 1 to 0, it commands the next flip-flop to toggle. If the next flip-flop toggle is a transition from 1 to 0, it will command the flip-flop after it to toggle as well, and so on. However, since there is always some small amount of propagation delay between the command to toggle (the clock pulse) and the actual toggle response (Q and Q’ outputs changing states), any subsequent flip-flops to be toggled will toggle some time after the first flip-flop has toggled. Thus, when multiple bits toggle in a binary count sequence, they will not all toggle at exactly
330 CHAPTER 11. COUNTERS the same time:
Pulse diagram showing (exaggerated) propagation delays Q 0 1
1
1
1
1
1
1
1
00
1
1
1
1
1
1
1
1 Q
1
00
1
1
1
1
1
1
1
1
2 Q
00
1
1
1
1
1
1
1
1 Q
3 Accumulated delay
As you can see, the more bits that toggle with a given clock pulse, the more severe the accumulated delay time from LSB to MSB. When a clock pulse occurs at such a transition point (say, on the transition from 0111 to 1000), the output bits will ”ripple” in sequence from LSB to MSB, as each succeeding bit toggles and commands the next bit to toggle as well, with a small amount of propagation delay between each bit toggle. If we take a close-up look at this effect during the transition from 0111 to 1000, we can see that there will be false output counts generated in the brief time period that the ”ripple” effect takes place:
Count Count False
7
8 counts
Q
1 delay
Q
1
1
1
delay
Q
2
1
1
1 delay
Q
3
1 Instead of cleanly transitioning from a ”0111” output to a ”1000” output, the counter circuit
will very quickly ripple from 0111 to 0110 to 0100 to 0000 to 1000, or from 7 to 6 to 4 to 0 and
11.2. ASYNCHRONOUS COUNTERS 331 then to 8. This behavior earns the counter circuit the name of ripple counter, or asynchronous counter.
In many applications, this effect is tolerable, since the ripple happens very, very quickly (the width of the delays has been exaggerated here as an aid to understanding the effects). If all we wanted to do was drive a set of light-emitting diodes (LEDs) with the counter’s outputs, for example, this brief ripple would be of no consequence at all. However, if we wished to use this counter to drive the ”select” inputs of a multiplexer, index a memory pointer in a microprocessor (computer) circuit, or perform some other task where false outputs could cause spurious errors, it would not be acceptable. There is a way to use this type of counter circuit in applications sensitive to false, ripple-generated outputs, and it involves a principle known as strobing.