Metal Gate Process Refining Using Gate First And Gate Last Technology For 22nm N-MOSFET.
METAL GATE PROCESS REFINING USING GATE FIRST AND GATE LAST
TECHNOLOGY FOR 22nm N-MOSFET
NOR IDAYU BINTI CHE HUSSIN
This report is submitted in partial fulfillment of requirements for the Bachelor
Degree of Electronic Engineering (Computer Engineering)
Faculty of Electronic Engineering and Computer Engineering
Universiti Teknikal Malaysia Melaka
JUNE 2015
ii
iii
iv
v
This thesis is dedicated to
My family for their supports
and guide me throughout my academic career
vi
ACKNOWLEDGEMENT
Bismillahirrahmanirrahim.
Alhamdulillah, thanks to the almighty god ALLAH SWT, for His help and
blessing for giving me this opportunity to complete my final year project entitle
“Metal Gate Process Refining Using Gate First and Gate Last Technology for 22nm
nMOSFET”.
First and foremost, I would like to express my heartily gratitude to my
supervisor, Puan Niza Binti Mohd Idris for the guidance and enthusiasm given
throughout the progress of this project. I am most grateful for her willingness to offer
help to the very end of this project.
My appreciation also goes to my family who has been so supportive mentally
and financially throughout this project and also providing me the opportunity
to study in UTeM Melaka and provide support in terms of spirit and financial.
I would not been able to further my studies to this level without them.
Nevertheless, my great appreciation dedicated to my friends and those whom
involve directly or indirectly with this project. There is no such meaningful word
than Thank You So Much.
Last but not least I would like to thank all the members of Computer
and Electronic Engineering Faculty for providing this course and giving me this
golden chance to take a depth knowledge on nanotechnology.
vii
ABSTRACT
This research has been done to improve the performance of 22nm nMOSFET using two approaches which is gate-first and gate-last technology. Gatefirst technology was initially developed by Sematech and the IBM-led Fishkill
Alliance and found that it has flaws with their design. In gate-first technology,
directly deposited gate has caused the gate damage due to the high temperature (over
1000°C) during the annealing process. To fix the flaws, gate-last technology has
been proposed. Gate-last technology was introduced by Intel, implementing it in its
45nm technology. Gate-last technology overcomes the problem by depositing the
dummy gate to withstand the high temperature throughout the annealing process then
replace the gate with the real gate at the last process. Basically, metal gate is always
pair up with high-k dielectric. Unfortunately, high-k dielectric is not defined by the
simulation tools that we used. Thus, we use SiO2 (silicon dioxide) as a dielectric
constant for both processes. The metal gate used for this 22nm n-MOSFET is
Titanium Nitrate (TiN). NMOS transistor was simulated using fabrication tool
Silvaco ATHENA and the electrical characteristic was simulated using Silvaco
ATLAS. The objective of this experiment is to design and compare the performance
of 22nm n-MOSFET using gate-first and gate-last process. The results indicate that
the gate-last process improves the performance of 22nm n-MOSFET in comparison
with gate-first process. This is due to the undamaged metal gate during the annealing
process.
viii
ABSTRAK
Kajian ini telah dijalankan untuk menambah baik pencapaian bagi 22nm nMOSFET mengunakan dua pendekatan, iaitu teknologi gate-first dan gate-last. Pada
awalnya, teknologi gate-first telah dimulakan oleh Sematech dan IBM-led Fishkill
Alliance dan didapati mempunyai kelemahan dalam reka bentuknya. Dalam
teknologi gate-first, metal gate telah didepositkan secara langsung yang
menyebabkan kerosakan gate kerana telah terdedah kepada suhu yang tinggi
(melebihi 1000°C) semasa proses annealing. Untuk mengatasi kelemahan tersebut,
teknologi gate-last telah dicadangkan. Teknologi gate-last telah diperkenalkan oleh
Intel, yang mana telah dilaksanakan untuk teknologi 45nm. Teknologi gate last
mengatasi masalah ini dengan mendepositkan dummy gate untuk menahan suhu yang
tinggi semasa proses annealing kemudian menggantikannya dengan metal gate yang
sebenar di akhir proses tersebut. Pada dasarnya, metal gate selalu digabungkan
dengan pemalar dielektrik yang tinggi. Malangnya, pemalar dielektrik yang tinggi
tidak ditakrifkan oleh alat simulasi yang digunakan. Oleh itu, SiO2 (silicon dioksida)
telah digunakan sebagai pemalar dielektrik untuk kedua-dua proses. Metal gate yang
digunakan untuk 22nm n-MOSFET adalah Titanium Nitrat (TiN). NMOS transistor
telah disimulasikan menggunakan alat fabrikasi Silvaco ATHENA dan ciri-ciri
elektrik telah disimulasikan menggunakan Silvaco ATLAS. Objektif kajian ni adalah
untuk mereka bentuk dan membandingkan pencapaian 22nm n-MOSFET yang
menggunakan teknologi gate-first dan gate-last. Keputusan menunjukkan bahawa
proses gate-last dapat meningkatkan pencapaian 22nm n-MOSFET jika dibanding
dengan proses gate-first. Hal ini disebabkan oleh metal gate yang tidak rosak semasa
proses annealing.
ix
TABLE OF CONTENTS
CONTENTS
PAGE
Project Title
ii
Supervisor Declaration
iii
Student Declaration
iv
Dedication
v
Acknowledgement
vi
Abstract
vii
Abstrak
viii
Table of Contents
ix
List of tables
xiii
List of figures
xiv
List of abbreviations
xvii
CHAPTER 1 Introduction
1.1 Project introduction
1
1.2 Problem statements
2
1.3 Objectives
3
1.4 Scope of project
3
1.5 Thesis Outline
4
CHAPTER 2 Literature Review
x
2.0 Introduction
5
2.1 Introduction to the Mosfet
6
2.1.1 Basic MOSFET operation
2.2 N-channel Mosfet fabrication Process
2.2.1 Gate-first versus gate-last approaches
7
9
16
2.3 Mosfet scaling
17
2.4 Equivalent oxide thickness (EOT)
19
2.5 Drain induced barrier lowering
21
2.6 Threshold Voltage
22
2.7 Leakage Current
22
CHAPTER 3 Methodology
3.1 Introduction
23
3.2 Overall Process Flow Diagram
24
3.3 Overall Operation of Fabrication using Silvaco.
25
3.3.1 Device Specification
26
3.4 MOSFET Design Process
27
3.5 Process Development using ATHENA
28
3.5.1 Defining initial grid
28
3.5.2 Substrate doping
29
3.5.3 Gate First Fabrication Process
30
3.5.3.1 Deposit oxide as a mask layer
30
3.5.3.2 Source and drain ion implantation
30
3.5.3.3 EOT and Gate Deposition
31
3.5.3.4 Anneal to Activate Source and Drain.
32
3.5.3.5 Contact Formation and Specification of
33
Electrodes
3.5.4 Gate Last Fabrication Process
35
3.5.4.1 Polysilicon Gate Deposition
35
3.5.4.2 Source and Drain Ion Implantation
36
3.5.4.3 Removal of Dummy Gate
37
xi
3.5.4.4 EOT and New Gate Deposition
38
3.5.4.5 Spacer Formation and Aluminium
39
Deposition
3.5.5 Device Simulation using ATLAS
41
CHAPTER 4 Result and Discussion
4.0 Introduction
42
4.1 Structure of the Device
42
4.2 Gate-First Technology
44
4.2.1 Linear Drain Current Graph
44
4.2.2 Log Drain Current Graph
46
4.2.3 High versus Low Drain Current Graph
47
4.2.4 Extract Value for Gate First Design
49
4.3 Gate-Last Technology
49
4.3.1 Linear Drain Current Graph
49
4.3.2 Log Drain Current Graph
51
4.3.3 High versus Low Drain Current Graph
52
4.3.4 Extract Value for Gate Last Design
54
4.4 Comparison between Gate First and Gate Last Design.
54
4.4.1 Structure Design
55
4.4.2 Drain Current Linear Graph
55
4.4.3 Drain Current Log Graph
56
4.4.4 Extracted Values for Gate First and Gate Last
56
Design
4.5 Discussion
57
CHAPTER 5 Conclusion and Recommendation
5.0 Introduction
59
5.1 Conclusion
60
xii
5.2 Recommendation for Future Works
References
Appendix A
Appendix B
Appendix C
Appendix D
60
61
xiii
LIST OF TABLES
Table No.
2.1
Title
ITRS 2011 for High-performance Logic Technology
Page
18
Requirement
3.1
Details on the 22nm N-Type MOSFET Design
27
4.1
Parameter details for 22nm N-Type MOSFET.
44
4.2
Extract values for gate-first design.
49
4.3
Extract values for gate-last design.
54
4.4
Extract values for gate-first and gate-last design.
56
xiv
LIST OF FIGURES
Figure No
Title
Page
2.1
Source terminal short-circuit to the body (p-substrate)
6
2.2
Basic n-Type MOSFET Structure
7
2.3
Pure Silicon
9
2.4
P-type impurity s lightly doped.
9
2.5
SiO2 Deposited over Si Surface
10
2.6
Photoresist is deposited over SiO2 layer
10
2.7
Photoresist layer is exposed to UV Light through a mask
11
2.8
Etching (using HF acid) will removed SiO2 layer which is
11
indirect contact with etching solution
2.9
A thin layer of SiO2 grown over the entire chip surface
12
2.10
A thin layer of polysilicon is grown over the entire chip
12
surface to form gate
2.11
A layer of photoresist is grown over polysilicon layer
13
2.12
n+ doping to form source and drain.
13
2.13
A thick layer of SiO2 (1μm) is again grown.
14
2.14
Photoresist is grown over thick SiO2.
14
2.15
Metal (aluminium) is deposited over the surface of whole
15
chip (1μm thickness)
2.16
Final n-MOS transistor
15
2.17
Principle of MOSFET constant-electric-field scaling.
17
2.18
EOT scaling road map of various structure MOS
19
transistors (ITRS 2008).
xv
2.19
Band gap versus dielectric constant plot of various high-k
20
materials studied for gate insulator.
2.20
Annealing temperature versus EOT plot of 2 type gate
21
electrodes, Ta and TaN.
3.1
Summary of the project.
24
3.2
Flow Diagram for both Gate-First and Gate-Last
25
Fabrication Process
3.3
Flow of designing the MOSFET
27
3.4
View grid window
29
3.5
Initial silicon substrate
29
3.6
Deposit oxide as mask layer
30
3.7
Source and drain ion implantation.
31
3.8
EOT and gate deposition
32
3.9
Source/ Drain Annealing
33
3.10
Aluminium deposited
34
3.11
Complete gate first structure
35
3.12
Polysilicon gate deposition
36
3.13
Source/Drain Implantation
37
3.14
Removed dummy gate
38
3.15
New gate formation
39
3.16
Aluminium Deposition
40
3.17
Complete gate last structure
41
4.1
22nm N-MOSFET Design using Gate-First Technology
43
4.2
22nm N-MOSFET Design using Gate-Last Technology
43
4.3
High Drain Current Graph
45
4.4
Low Drain Current Graph
45
4.5
Log Graph of High Drain Current
46
4.6
Log Graph of Low Drain Current
47
4.7
Linear graph of high versus low drain current
48
4.8
Log graph of high versus low drain current
48
4.9
High Drain Current Graph
50
4.10
Low Drain Current Graph
50
4.11
Log Graph of High Drain Current
51
xvi
4.12
Log Graph of Low Drain Current
52
4.13
Linear graph of high versus low drain current
53
4.14
Log graph of high versus low drain current
53
4.15
MOSFET design structure for gate first and gate last
55
4.16
Linear drain current graph overlay of gate first and gate
55
last
4.17
Log drain current graph overlay of gate first and gate last
56
xvii
LIST OF ABBREVIATIONS
MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor
CMOS
Complementary Metal-Oxide-Semiconductor
NMOS
N-channel Metal-Oxide-Semiconductor
FET
Field-Effect Transistor
ITRS
International Technology Roadmap for Semiconductors
EOT
Equivalent Oxide Thickness
RTA
Rapid Thermal Anneal
SiO2
Silicon Dioxide
HfO2
Hafnium Dioxide
HK/MG
High-k Metal Gate
TCAD
Technology Computer Aided Design
IL
Interfacial Layer
Vds
Source-Drain Voltage
Vg
Gate Voltage
Vth
Threshold Voltage
C
Capacitance
I
Current
V
Voltage
CHAPTER 1
INTRODUCTION
1.1 Project Introduction
MOSFET (metal-oxide semiconductor field-effect transistor) is a four terminal
device with source (S), drain (D), gate (G), and body (B) terminals. The body or
substrate of the MOSFET is often connected to the source terminal, whereby make it
a three terminal device like another field-effect transistor (FET). The MOSFET is the
most common transistor in both digital and analogue circuits.
The MOSFET is a special type of FET that works by electronically varying the
width of a channel along which charge carriers (electrons or holes) flow. The charge
carriers enter the channel at the source, and exit through the drain. The width of the
channel is controlled by the voltage on an electrode called the gate, which is located
physically between the source and the drain and is insulated from the channel by an
2
extremely thin layer of metal oxide. The MOSFET is useful for power amplifiers and
also well suited to high-speed switching applications. Most integrated circuits (IC)
contain nano MOSFETs and mostly used in electronic devices.
Several integration schemes are being considered with the two main approaches
being “gate-last” and “gate-first”. The gate-last approach is considered a lowtemperature process since the metal is not exposed to high temperatures [1]. The
major advantage of this approach is that metals with known work functions can be
integrated with a relatively simple process flow without exposure to a high thermal
budget. In the gate-first integration flow, a standard transistor process is used.
The specification of the 22nm n-MOSFET has been designed according to the
ITRS (International Technology Roadmap Semiconductors) 2011 requirements.
Generally, this research is to measure the performance of 22nm n-MOSFET that has
been carefully designed using Silvaco simulator. The results is measure by
comparing the IV-Characteristic of the two processes regarding the drive current,
leakage current, subthreshold slope and threshold voltage. MOSFET structure is
designed using the Silvaco simulator ATHENA whereas the graph is plotted using
Silvaco ATLAS.
1.2 Problem Statements
The MOSFET has continually been scaled down in size. Small MOSFETs exhibit
higher leakage current and lower output resistance [1]. The difficulties with
decreasing the size of the MOSFET have been associated with the semiconductor
device fabrication process, the need to use very low voltages, and with poorer
electrical performance, it is necessary to redesign the circuit.
Since the scaling of the CMOS transistor has been the primary factor driving the
improvements in microprocessor performance, choosing the best gate engineering
technologies is required in order to maintain this rapid rate of improvement. One of
the important parts is to design the devices in perfect gate technologies to improve its
performance in nano scales devices [1].
3
Gate-first technology means that the metal gate is formed at early stage of
fabrication process and the gate itself acts as a mask for the source and drain
implantation. During the gate-first fabrication, the high temperature in the anneal
step can cause the gate damage thus destroy the long-term integrity of the gate stack
that will affect the performance of the MOSFET.
Gate-last technology is introduced to overcome this problem. Gate-last
technology uses a sacrificial polysilicon instead of the actual gate to mask the
implantation. After the high temperature source-drain annealing cycles, the dummy
gate was removed and metal gate electrodes were deposited and anneal at lower
temperature.
1.3 Objectives
The main objectives of this project are:
To design the 22nm NMOSFET using gate-first and gate-last technology.
To analyse the electrical characteristics of the devices regarding to drive
current (Ion), leakage current (Ioff), subthreshold slope (SS), and threshold
voltage (Vth).
To compare the performance of 22nm NMOSFET using metal gate with gatefirst and gate-last technology.
1.4 Scope of Project
The scopes of the project are as the following:
Focusing on refining process of the metal gate (Titanium Nitrate) using gatefirst and gate-last technology.
The device will be designed and simulate for 22nm n-type MOSFET.
Simulation tools using Silvaco TCAD software, including Athena for design
the structure and Atlas to plot the graph.
4
1.5 Thesis Outline
The outline of this project is planned to ensure that the flow of this research
study is presented properly. Besides that, this outline also can help the readers to
fully understand the project research all about from the first chapter to the last
chapter.
Chapter 1 includes the project introduction, problem statements, objectives,
scope of this project and the thesis outline. Theory and literature review is discussed
in chapter 2.
Chapter 2 discussed about the MOSFET and the differential in its electrical
performances. This chapter also states the research on the fabrication process of the
N-Type MOSFET using these two processes, gate-first and gate-last. Besides,
MOSFET scaling and Equivalent Oxide Thickness (EOT) that is related to the device
characteristic performance is also outlined. This chapter will be the knowledge
source to gain the understanding about the gate process theories.
The methodology and software implementation of this project is thoroughly
discussed in chapter 3. The software to complete this research is SILVACO TCAD
and it has two parts which are ATHENA and ATLAS.
Chapter 4 elaborate the results and discussions produced by the simulation. It
consists of the findings and explanations of the data and problems occurs along this
research is conducted. The finding is presented in form of the designed structure and
graph comparison.
Lastly, in chapter 5 conclusion and recommendations are outlined. In this chapter, it
concludes the overall project and makes a suggestion for the future work regarding
this study.
CHAPTER 2
LITERATURE REVIEW
2.0 Introduction
This chapter review on fundamental and basic concepts of MOSFET,
MOSFET operation, characteristics and its electrical performance. The objective of
this research is to compare the performance of n-type MOSFET using two different
technologies known as gate-first and gate-last technology. Therefore, this review has
been highlighted on theories, processes of fabrication and specifications used related
to this project through readings and research on previous study. Next, some
explanation about EOT (Equivalent Oxide Thickness), mosfet scaling, fabrication
process, and several electrical characteristics are thoroughly elaborated.
6
2.1 Introduction to the MOSFET
The metal-oxide-silicon field effect transistor (MOSFET) consists of four
terminals, namely the source, gate, drain, and substrate (body). It is, in its very
simplest form, a simple extension of the MOS capacitor, in which the gate electrode
and the semiconductor channel constitute the parallel capacitor plates and the
isolating oxide layer is equivalent to the dielectric material [2]. Although the
MOSFET has a four-terminal device with source (S), gate (G), drain (D), and body
(B) terminals [3], the body (substrate) of the MOSFET is commonly connected to the
source terminal, making it three terminal devices like other field-effect transistors.
Since these two terminals are normally connected to each other internally, it caused
them to be short-circuited. Thus, only three terminals appear in electrical diagrams as
illustrated in Figure 2.1.
Figure 2.1: Source terminal short-circuit to the body (p-substrate) [6]
The drain and source terminals are connected to the heavily doped regions
whereby the gate is connected on top of the oxide layer and the body terminal or
substrate is connected to the intrinsic semiconductor [7]. The MOSFET is capable for
voltage gain and signal power gain [7]. The inversion layer is formed between the
source and drain terminal due to the flow of the carriers in it, the current flows in
MOSFET are controlled by gate voltage. Thus it is known as a voltage controlled
device.
7
N-type MOSFET is known by having n-channel region between source and
drain. The source and drain is heavily doped n+ region (arsenic or phosphorus) with
concentration of 1018/cm3 and the substrate used is p-type substrate (Boron). The
nMOS device is operated by setting a bias on the drain contact and using the gate
voltage to control the flow of electrons from the source to the drain [2]. The current
flows due to the flow of the negatively charged electrons. The gate voltage controls
the electron concentration in the n-channel MOSFET is preferred over p-channel
MOSFET as the mobility of electrons is higher than the holes. The basic structure of
n-type MOSFET is shown in Figure 2.2.
Figure 2.2: Basic n-Type MOSFET Structure [7]
2.1.1 Basic MOSFET operation
In the MOSFET, an inversion layer at the semiconductor – oxide interface
acts as a conducting channel. For instance, in an n-channel MOSFET, the substrate is
p-type silicon and the inversion charge consists of electrons that form a conducting
channel between the n+ ohmic source and the drain contacts. At DC (direct current)
conditions, the depletion regions and the neutral substrate provide isolation between
devices fabricated on the same substrate.
TECHNOLOGY FOR 22nm N-MOSFET
NOR IDAYU BINTI CHE HUSSIN
This report is submitted in partial fulfillment of requirements for the Bachelor
Degree of Electronic Engineering (Computer Engineering)
Faculty of Electronic Engineering and Computer Engineering
Universiti Teknikal Malaysia Melaka
JUNE 2015
ii
iii
iv
v
This thesis is dedicated to
My family for their supports
and guide me throughout my academic career
vi
ACKNOWLEDGEMENT
Bismillahirrahmanirrahim.
Alhamdulillah, thanks to the almighty god ALLAH SWT, for His help and
blessing for giving me this opportunity to complete my final year project entitle
“Metal Gate Process Refining Using Gate First and Gate Last Technology for 22nm
nMOSFET”.
First and foremost, I would like to express my heartily gratitude to my
supervisor, Puan Niza Binti Mohd Idris for the guidance and enthusiasm given
throughout the progress of this project. I am most grateful for her willingness to offer
help to the very end of this project.
My appreciation also goes to my family who has been so supportive mentally
and financially throughout this project and also providing me the opportunity
to study in UTeM Melaka and provide support in terms of spirit and financial.
I would not been able to further my studies to this level without them.
Nevertheless, my great appreciation dedicated to my friends and those whom
involve directly or indirectly with this project. There is no such meaningful word
than Thank You So Much.
Last but not least I would like to thank all the members of Computer
and Electronic Engineering Faculty for providing this course and giving me this
golden chance to take a depth knowledge on nanotechnology.
vii
ABSTRACT
This research has been done to improve the performance of 22nm nMOSFET using two approaches which is gate-first and gate-last technology. Gatefirst technology was initially developed by Sematech and the IBM-led Fishkill
Alliance and found that it has flaws with their design. In gate-first technology,
directly deposited gate has caused the gate damage due to the high temperature (over
1000°C) during the annealing process. To fix the flaws, gate-last technology has
been proposed. Gate-last technology was introduced by Intel, implementing it in its
45nm technology. Gate-last technology overcomes the problem by depositing the
dummy gate to withstand the high temperature throughout the annealing process then
replace the gate with the real gate at the last process. Basically, metal gate is always
pair up with high-k dielectric. Unfortunately, high-k dielectric is not defined by the
simulation tools that we used. Thus, we use SiO2 (silicon dioxide) as a dielectric
constant for both processes. The metal gate used for this 22nm n-MOSFET is
Titanium Nitrate (TiN). NMOS transistor was simulated using fabrication tool
Silvaco ATHENA and the electrical characteristic was simulated using Silvaco
ATLAS. The objective of this experiment is to design and compare the performance
of 22nm n-MOSFET using gate-first and gate-last process. The results indicate that
the gate-last process improves the performance of 22nm n-MOSFET in comparison
with gate-first process. This is due to the undamaged metal gate during the annealing
process.
viii
ABSTRAK
Kajian ini telah dijalankan untuk menambah baik pencapaian bagi 22nm nMOSFET mengunakan dua pendekatan, iaitu teknologi gate-first dan gate-last. Pada
awalnya, teknologi gate-first telah dimulakan oleh Sematech dan IBM-led Fishkill
Alliance dan didapati mempunyai kelemahan dalam reka bentuknya. Dalam
teknologi gate-first, metal gate telah didepositkan secara langsung yang
menyebabkan kerosakan gate kerana telah terdedah kepada suhu yang tinggi
(melebihi 1000°C) semasa proses annealing. Untuk mengatasi kelemahan tersebut,
teknologi gate-last telah dicadangkan. Teknologi gate-last telah diperkenalkan oleh
Intel, yang mana telah dilaksanakan untuk teknologi 45nm. Teknologi gate last
mengatasi masalah ini dengan mendepositkan dummy gate untuk menahan suhu yang
tinggi semasa proses annealing kemudian menggantikannya dengan metal gate yang
sebenar di akhir proses tersebut. Pada dasarnya, metal gate selalu digabungkan
dengan pemalar dielektrik yang tinggi. Malangnya, pemalar dielektrik yang tinggi
tidak ditakrifkan oleh alat simulasi yang digunakan. Oleh itu, SiO2 (silicon dioksida)
telah digunakan sebagai pemalar dielektrik untuk kedua-dua proses. Metal gate yang
digunakan untuk 22nm n-MOSFET adalah Titanium Nitrat (TiN). NMOS transistor
telah disimulasikan menggunakan alat fabrikasi Silvaco ATHENA dan ciri-ciri
elektrik telah disimulasikan menggunakan Silvaco ATLAS. Objektif kajian ni adalah
untuk mereka bentuk dan membandingkan pencapaian 22nm n-MOSFET yang
menggunakan teknologi gate-first dan gate-last. Keputusan menunjukkan bahawa
proses gate-last dapat meningkatkan pencapaian 22nm n-MOSFET jika dibanding
dengan proses gate-first. Hal ini disebabkan oleh metal gate yang tidak rosak semasa
proses annealing.
ix
TABLE OF CONTENTS
CONTENTS
PAGE
Project Title
ii
Supervisor Declaration
iii
Student Declaration
iv
Dedication
v
Acknowledgement
vi
Abstract
vii
Abstrak
viii
Table of Contents
ix
List of tables
xiii
List of figures
xiv
List of abbreviations
xvii
CHAPTER 1 Introduction
1.1 Project introduction
1
1.2 Problem statements
2
1.3 Objectives
3
1.4 Scope of project
3
1.5 Thesis Outline
4
CHAPTER 2 Literature Review
x
2.0 Introduction
5
2.1 Introduction to the Mosfet
6
2.1.1 Basic MOSFET operation
2.2 N-channel Mosfet fabrication Process
2.2.1 Gate-first versus gate-last approaches
7
9
16
2.3 Mosfet scaling
17
2.4 Equivalent oxide thickness (EOT)
19
2.5 Drain induced barrier lowering
21
2.6 Threshold Voltage
22
2.7 Leakage Current
22
CHAPTER 3 Methodology
3.1 Introduction
23
3.2 Overall Process Flow Diagram
24
3.3 Overall Operation of Fabrication using Silvaco.
25
3.3.1 Device Specification
26
3.4 MOSFET Design Process
27
3.5 Process Development using ATHENA
28
3.5.1 Defining initial grid
28
3.5.2 Substrate doping
29
3.5.3 Gate First Fabrication Process
30
3.5.3.1 Deposit oxide as a mask layer
30
3.5.3.2 Source and drain ion implantation
30
3.5.3.3 EOT and Gate Deposition
31
3.5.3.4 Anneal to Activate Source and Drain.
32
3.5.3.5 Contact Formation and Specification of
33
Electrodes
3.5.4 Gate Last Fabrication Process
35
3.5.4.1 Polysilicon Gate Deposition
35
3.5.4.2 Source and Drain Ion Implantation
36
3.5.4.3 Removal of Dummy Gate
37
xi
3.5.4.4 EOT and New Gate Deposition
38
3.5.4.5 Spacer Formation and Aluminium
39
Deposition
3.5.5 Device Simulation using ATLAS
41
CHAPTER 4 Result and Discussion
4.0 Introduction
42
4.1 Structure of the Device
42
4.2 Gate-First Technology
44
4.2.1 Linear Drain Current Graph
44
4.2.2 Log Drain Current Graph
46
4.2.3 High versus Low Drain Current Graph
47
4.2.4 Extract Value for Gate First Design
49
4.3 Gate-Last Technology
49
4.3.1 Linear Drain Current Graph
49
4.3.2 Log Drain Current Graph
51
4.3.3 High versus Low Drain Current Graph
52
4.3.4 Extract Value for Gate Last Design
54
4.4 Comparison between Gate First and Gate Last Design.
54
4.4.1 Structure Design
55
4.4.2 Drain Current Linear Graph
55
4.4.3 Drain Current Log Graph
56
4.4.4 Extracted Values for Gate First and Gate Last
56
Design
4.5 Discussion
57
CHAPTER 5 Conclusion and Recommendation
5.0 Introduction
59
5.1 Conclusion
60
xii
5.2 Recommendation for Future Works
References
Appendix A
Appendix B
Appendix C
Appendix D
60
61
xiii
LIST OF TABLES
Table No.
2.1
Title
ITRS 2011 for High-performance Logic Technology
Page
18
Requirement
3.1
Details on the 22nm N-Type MOSFET Design
27
4.1
Parameter details for 22nm N-Type MOSFET.
44
4.2
Extract values for gate-first design.
49
4.3
Extract values for gate-last design.
54
4.4
Extract values for gate-first and gate-last design.
56
xiv
LIST OF FIGURES
Figure No
Title
Page
2.1
Source terminal short-circuit to the body (p-substrate)
6
2.2
Basic n-Type MOSFET Structure
7
2.3
Pure Silicon
9
2.4
P-type impurity s lightly doped.
9
2.5
SiO2 Deposited over Si Surface
10
2.6
Photoresist is deposited over SiO2 layer
10
2.7
Photoresist layer is exposed to UV Light through a mask
11
2.8
Etching (using HF acid) will removed SiO2 layer which is
11
indirect contact with etching solution
2.9
A thin layer of SiO2 grown over the entire chip surface
12
2.10
A thin layer of polysilicon is grown over the entire chip
12
surface to form gate
2.11
A layer of photoresist is grown over polysilicon layer
13
2.12
n+ doping to form source and drain.
13
2.13
A thick layer of SiO2 (1μm) is again grown.
14
2.14
Photoresist is grown over thick SiO2.
14
2.15
Metal (aluminium) is deposited over the surface of whole
15
chip (1μm thickness)
2.16
Final n-MOS transistor
15
2.17
Principle of MOSFET constant-electric-field scaling.
17
2.18
EOT scaling road map of various structure MOS
19
transistors (ITRS 2008).
xv
2.19
Band gap versus dielectric constant plot of various high-k
20
materials studied for gate insulator.
2.20
Annealing temperature versus EOT plot of 2 type gate
21
electrodes, Ta and TaN.
3.1
Summary of the project.
24
3.2
Flow Diagram for both Gate-First and Gate-Last
25
Fabrication Process
3.3
Flow of designing the MOSFET
27
3.4
View grid window
29
3.5
Initial silicon substrate
29
3.6
Deposit oxide as mask layer
30
3.7
Source and drain ion implantation.
31
3.8
EOT and gate deposition
32
3.9
Source/ Drain Annealing
33
3.10
Aluminium deposited
34
3.11
Complete gate first structure
35
3.12
Polysilicon gate deposition
36
3.13
Source/Drain Implantation
37
3.14
Removed dummy gate
38
3.15
New gate formation
39
3.16
Aluminium Deposition
40
3.17
Complete gate last structure
41
4.1
22nm N-MOSFET Design using Gate-First Technology
43
4.2
22nm N-MOSFET Design using Gate-Last Technology
43
4.3
High Drain Current Graph
45
4.4
Low Drain Current Graph
45
4.5
Log Graph of High Drain Current
46
4.6
Log Graph of Low Drain Current
47
4.7
Linear graph of high versus low drain current
48
4.8
Log graph of high versus low drain current
48
4.9
High Drain Current Graph
50
4.10
Low Drain Current Graph
50
4.11
Log Graph of High Drain Current
51
xvi
4.12
Log Graph of Low Drain Current
52
4.13
Linear graph of high versus low drain current
53
4.14
Log graph of high versus low drain current
53
4.15
MOSFET design structure for gate first and gate last
55
4.16
Linear drain current graph overlay of gate first and gate
55
last
4.17
Log drain current graph overlay of gate first and gate last
56
xvii
LIST OF ABBREVIATIONS
MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor
CMOS
Complementary Metal-Oxide-Semiconductor
NMOS
N-channel Metal-Oxide-Semiconductor
FET
Field-Effect Transistor
ITRS
International Technology Roadmap for Semiconductors
EOT
Equivalent Oxide Thickness
RTA
Rapid Thermal Anneal
SiO2
Silicon Dioxide
HfO2
Hafnium Dioxide
HK/MG
High-k Metal Gate
TCAD
Technology Computer Aided Design
IL
Interfacial Layer
Vds
Source-Drain Voltage
Vg
Gate Voltage
Vth
Threshold Voltage
C
Capacitance
I
Current
V
Voltage
CHAPTER 1
INTRODUCTION
1.1 Project Introduction
MOSFET (metal-oxide semiconductor field-effect transistor) is a four terminal
device with source (S), drain (D), gate (G), and body (B) terminals. The body or
substrate of the MOSFET is often connected to the source terminal, whereby make it
a three terminal device like another field-effect transistor (FET). The MOSFET is the
most common transistor in both digital and analogue circuits.
The MOSFET is a special type of FET that works by electronically varying the
width of a channel along which charge carriers (electrons or holes) flow. The charge
carriers enter the channel at the source, and exit through the drain. The width of the
channel is controlled by the voltage on an electrode called the gate, which is located
physically between the source and the drain and is insulated from the channel by an
2
extremely thin layer of metal oxide. The MOSFET is useful for power amplifiers and
also well suited to high-speed switching applications. Most integrated circuits (IC)
contain nano MOSFETs and mostly used in electronic devices.
Several integration schemes are being considered with the two main approaches
being “gate-last” and “gate-first”. The gate-last approach is considered a lowtemperature process since the metal is not exposed to high temperatures [1]. The
major advantage of this approach is that metals with known work functions can be
integrated with a relatively simple process flow without exposure to a high thermal
budget. In the gate-first integration flow, a standard transistor process is used.
The specification of the 22nm n-MOSFET has been designed according to the
ITRS (International Technology Roadmap Semiconductors) 2011 requirements.
Generally, this research is to measure the performance of 22nm n-MOSFET that has
been carefully designed using Silvaco simulator. The results is measure by
comparing the IV-Characteristic of the two processes regarding the drive current,
leakage current, subthreshold slope and threshold voltage. MOSFET structure is
designed using the Silvaco simulator ATHENA whereas the graph is plotted using
Silvaco ATLAS.
1.2 Problem Statements
The MOSFET has continually been scaled down in size. Small MOSFETs exhibit
higher leakage current and lower output resistance [1]. The difficulties with
decreasing the size of the MOSFET have been associated with the semiconductor
device fabrication process, the need to use very low voltages, and with poorer
electrical performance, it is necessary to redesign the circuit.
Since the scaling of the CMOS transistor has been the primary factor driving the
improvements in microprocessor performance, choosing the best gate engineering
technologies is required in order to maintain this rapid rate of improvement. One of
the important parts is to design the devices in perfect gate technologies to improve its
performance in nano scales devices [1].
3
Gate-first technology means that the metal gate is formed at early stage of
fabrication process and the gate itself acts as a mask for the source and drain
implantation. During the gate-first fabrication, the high temperature in the anneal
step can cause the gate damage thus destroy the long-term integrity of the gate stack
that will affect the performance of the MOSFET.
Gate-last technology is introduced to overcome this problem. Gate-last
technology uses a sacrificial polysilicon instead of the actual gate to mask the
implantation. After the high temperature source-drain annealing cycles, the dummy
gate was removed and metal gate electrodes were deposited and anneal at lower
temperature.
1.3 Objectives
The main objectives of this project are:
To design the 22nm NMOSFET using gate-first and gate-last technology.
To analyse the electrical characteristics of the devices regarding to drive
current (Ion), leakage current (Ioff), subthreshold slope (SS), and threshold
voltage (Vth).
To compare the performance of 22nm NMOSFET using metal gate with gatefirst and gate-last technology.
1.4 Scope of Project
The scopes of the project are as the following:
Focusing on refining process of the metal gate (Titanium Nitrate) using gatefirst and gate-last technology.
The device will be designed and simulate for 22nm n-type MOSFET.
Simulation tools using Silvaco TCAD software, including Athena for design
the structure and Atlas to plot the graph.
4
1.5 Thesis Outline
The outline of this project is planned to ensure that the flow of this research
study is presented properly. Besides that, this outline also can help the readers to
fully understand the project research all about from the first chapter to the last
chapter.
Chapter 1 includes the project introduction, problem statements, objectives,
scope of this project and the thesis outline. Theory and literature review is discussed
in chapter 2.
Chapter 2 discussed about the MOSFET and the differential in its electrical
performances. This chapter also states the research on the fabrication process of the
N-Type MOSFET using these two processes, gate-first and gate-last. Besides,
MOSFET scaling and Equivalent Oxide Thickness (EOT) that is related to the device
characteristic performance is also outlined. This chapter will be the knowledge
source to gain the understanding about the gate process theories.
The methodology and software implementation of this project is thoroughly
discussed in chapter 3. The software to complete this research is SILVACO TCAD
and it has two parts which are ATHENA and ATLAS.
Chapter 4 elaborate the results and discussions produced by the simulation. It
consists of the findings and explanations of the data and problems occurs along this
research is conducted. The finding is presented in form of the designed structure and
graph comparison.
Lastly, in chapter 5 conclusion and recommendations are outlined. In this chapter, it
concludes the overall project and makes a suggestion for the future work regarding
this study.
CHAPTER 2
LITERATURE REVIEW
2.0 Introduction
This chapter review on fundamental and basic concepts of MOSFET,
MOSFET operation, characteristics and its electrical performance. The objective of
this research is to compare the performance of n-type MOSFET using two different
technologies known as gate-first and gate-last technology. Therefore, this review has
been highlighted on theories, processes of fabrication and specifications used related
to this project through readings and research on previous study. Next, some
explanation about EOT (Equivalent Oxide Thickness), mosfet scaling, fabrication
process, and several electrical characteristics are thoroughly elaborated.
6
2.1 Introduction to the MOSFET
The metal-oxide-silicon field effect transistor (MOSFET) consists of four
terminals, namely the source, gate, drain, and substrate (body). It is, in its very
simplest form, a simple extension of the MOS capacitor, in which the gate electrode
and the semiconductor channel constitute the parallel capacitor plates and the
isolating oxide layer is equivalent to the dielectric material [2]. Although the
MOSFET has a four-terminal device with source (S), gate (G), drain (D), and body
(B) terminals [3], the body (substrate) of the MOSFET is commonly connected to the
source terminal, making it three terminal devices like other field-effect transistors.
Since these two terminals are normally connected to each other internally, it caused
them to be short-circuited. Thus, only three terminals appear in electrical diagrams as
illustrated in Figure 2.1.
Figure 2.1: Source terminal short-circuit to the body (p-substrate) [6]
The drain and source terminals are connected to the heavily doped regions
whereby the gate is connected on top of the oxide layer and the body terminal or
substrate is connected to the intrinsic semiconductor [7]. The MOSFET is capable for
voltage gain and signal power gain [7]. The inversion layer is formed between the
source and drain terminal due to the flow of the carriers in it, the current flows in
MOSFET are controlled by gate voltage. Thus it is known as a voltage controlled
device.
7
N-type MOSFET is known by having n-channel region between source and
drain. The source and drain is heavily doped n+ region (arsenic or phosphorus) with
concentration of 1018/cm3 and the substrate used is p-type substrate (Boron). The
nMOS device is operated by setting a bias on the drain contact and using the gate
voltage to control the flow of electrons from the source to the drain [2]. The current
flows due to the flow of the negatively charged electrons. The gate voltage controls
the electron concentration in the n-channel MOSFET is preferred over p-channel
MOSFET as the mobility of electrons is higher than the holes. The basic structure of
n-type MOSFET is shown in Figure 2.2.
Figure 2.2: Basic n-Type MOSFET Structure [7]
2.1.1 Basic MOSFET operation
In the MOSFET, an inversion layer at the semiconductor – oxide interface
acts as a conducting channel. For instance, in an n-channel MOSFET, the substrate is
p-type silicon and the inversion charge consists of electrons that form a conducting
channel between the n+ ohmic source and the drain contacts. At DC (direct current)
conditions, the depletion regions and the neutral substrate provide isolation between
devices fabricated on the same substrate.