Chau high k metal gate conf paper 110603
Gate Dielectric Scaling for High-Performance CMOS: from SiO 2 to High-K
Robert Chau, Suman Datta, Mark Doczy, Jack Kavalieros and Matthew Metz
Intel Corporation
5200 N.E. Elam Young Parkway, Hillsboro, OR 97124, USA. Mail-stop: RA3-252
503-613-6141, robert.s.chau@intel.com
Abstract
We have successfully demonstrated very high-performance
PMOS and NMOS transistors with high-K/metal-gate gate
stacks with the right threshold voltages for both p- and nchannels on bulk Si. We believe that high-K/metal-gate is an
option for the 45nm high-performance logic technology node.
1. Introduction
The silicon industry has been scaling SiO2 aggressively for
the past 15 years for low-power, high-performance CMOS
logic applications. SiO2 as thin as 1.2nm (physical Tox) has
already been successfully implemented in the 90nm logic
technology node [ref. 1]. Research transistors with 0.8nm
SiO2 have also been demonstrated in the laboratory [ref. 2-3].
However, continual gate dielectric scaling will require highK, as SiO2 will eventually run out of atoms for further
scaling. Most of the high-K gate dielectrics investigated are
Hf-based and Zr-based [ref. 4-6]. Both polySi and metals are
being evaluated as gate electrodes for the high-K dielectrics
[ref. 7-9]. There are many challenges reported in literature in
replacing SiO2 with high-K for high-performance CMOS [ref.
10-12]. This paper will present results on the 0.8nm SiO2 and
very high-performance PMOS and NMOS transistors with
high-K/metal-gate for high-performance logic applications.
2. SiO2 Scaling
The physical thickness of SiO2 has been scaled aggressively
for low-power, high-performance logic applications. Figure 1
shows the physical thickness trend of SiO2 for the various
logic generations. 1.2nm physical SiO2 has already been
successfully implemented in the 90nm logic node [ref. 1]. In
addition, 0.8nm physical SiO2 has also been produced [ref. 23]. TEM cross sections of the 1.2nm and 0.8nm SiO2 gate
oxides are shown in Figures 2-3. The electrical C-V and IgVg characteristics of the 0.8nm SiO2 are shown in Figures 45. Figures 6-7 show the device characteristics of the
experimental 15nm (physical gate length) NMOS transistor
with 0.8nm SiO2 . The data shows that the 15nm transistor
with 0.8nm physical SiO2 has well-controlled short-channel
characteristics.
3. High-K Dielectrics
It has been reported in literature [ref. 12] that Fermi level
pinning at the high-K/polySi interface causes high threshold
voltages in MOSFET transistors. It has also been reported
that high-K/polySi transistor exhibits severely degraded
channel mobility due to the coupling of low energy surface
optical (SO) phonon modes arising from the polarization of
the high-K to the inversion channel charge carriers [ref. 13],
and that metal gate may be more effective in screening the
high-K SO phonons from coupling to the channel under
inversion conditions [ref. 13-14]. On the other hand, the use
of high-K/metal-gate requires a p-type metal and a n-type
metal with the right work functions for high-performance
CMOS logic applications on bulk Si [ref. 15].
We have successfully fabricated high-performance PMOS
and NMOS transistors with high-K/metal-gate stacks. The
transistors have physical gate length (Lg) of 80nm and the
electrical oxide thickness (Toxe) is 1.45nm measured at
inversion. Figure 8 compares the leakage characteristics of
the high-K/metal-gate stacks with the conventional
SiO2 /polySi. Figures 9-10 show the device characteristics of
the PMOS transistor with high-K/metal-gate, while Figures
11-12 show the device characteristics of the NMOS transistor
with high-K/metal-gate. Both the high-K/metal-gate PMOS
and NMOS transistors show very high drive performance
(Idsat) with the right Vth for both p- and n-channel
devices on bulk Si, with very low gate leakage.
4. From SiO2 to High-K
We have implemented 1.2nm physical SiO2 in our 90nm
logic technology node [1], and have scaled physical SiO2
further down to 0.8nm and integrated it in research transistors
with 15nm physical gate length which show well-controlled
short-channel characteristics. We have also successfully
demonstrated very high-performance PMOS and NMOS
transistors with high-K/metal-gate gate stacks with the right
Vth for both p- and n-channels on bulk Si, with very low gate
leakage. We believe high-K/metal-gate is an option for the
45nm logic technology node for high-performance CMOS.
5. References
[1] S. Thompson et al., IEDM Technical Digest, p.61, 2002.
[2] R. Chau et al., IEDM Technical Digest, p.45, 2000.
[3] R. Chau et al., Physica E, Low-dimensional Systems and Nanostructures,
Vol. 19, Issues 1-2, p.1, 2003.
[4] R. Choi et al., IEDM Technical Digest, p.613, 2002.
[5] G. Lucovsky et al., IEDM Technical Digest, p.617, 2002.
[6] S. Inumiya et al., Symp. of VLSI Technology, p.17, 2003.
[7] Y. Kim et al., Symp. of VLSI Technology, p.167, 2003.
[8] J.H. Lee et al., IEDM Technical Digest, p.359, 2002.
[9] S.B. Samavedam et al., IEDM Technical Digest, p.433, 2002.
[10] R.M. Wallace, G. Wilk, MRS Bulletin, Vol. 27, No. 3, p.192, 2002.
[11] V. Mistra et al., MRS Bulletin, Vol. 27, No. 3, p.212, 2002.
[12] C. Hobbs et al., Symp. of VLSI Technology, p.9, 2003.
[13] M. Fischetti et al., J. Appl. Phys., Vol. 90, p.4587, 2001.
[14] S. Datta et al., to be presented at 2003 IEDM.
[15] I. De at al., Solid State Electron., Vol. 44, p.1077, 2000.
100
Thickness (Å)
Gate
1.2nm SiO2
Silicon substrate
90 nm
130 nm
180 nm
350nm
250 nm
10
Fig. 2 High resolution TEM cross section of 1.2nm
physical SiO 2 gate oxide at the 90nm logic technology
node.
Capacitance
Capacitance ( µF/cm²)
(µF/cm²)
Fig. 1 Scaling of physical thickness of SiO 2 gate oxide
across technology generations.
PolySi
2.0
1.5
NMOS
NMOS
PMOS
PMOS
1.0
0.5
0.8nm
0.0
Silicon
-1
-0.5
0
Vg
Vg (V)
0.5
1
Inversion Capacitance
Fig. 3 High resolution TEM cross section of
physical SiO 2 gate oxide.
0.8nm
Fig. 4 Inversion split C-V measurements of 0.8nm
physical SiO 2 gate oxide for NMOS and PMOS.
1E+3
500
1E+2
µA/ µm)
1E-1
NMOS
Inversion
NMOS
1E-2
1E-4
PMOS
Inversion
Drain Current (
J g (A/cm²)
1E+0
1E-3
Vg = 0.8V
15nm NMOS
1E+1
1E-5
400
0.7V
300
0.6V
200
0.5V
0.4V
100
0.3V
1E-6
-1
-0.5
0
0.5
1
V g (Volts)
0
0
0.2
0.4
0.6
0.8
Drain Voltage (V)
Fig. 5 Inversion gate leakage measurements of 0.8nm
physical SiO 2 gate oxide for NMOS and PMOS.
Fig. 6 Id-Vds characteristics of 15nm Lg experimental
NMOS transistor with 0.8nm physical SiO 2 gate oxide.
1.E+02
15nm NMOS
Vd = 0.8V
SiO2/polySi
1.E+01
1.E-04
Vd = 0.05V
1.E-05
S.S. = 95mV/decade
DIBL = 100mV/V
Ioff = 180nA/um
1.E-06
1.E-07
Jox [A/cm 2 ]
Drain Current (A/µm)
1.E-03
1.E+00
1.E-01
1.E-02
High-K/metal-gate
1.E-03
1.E-04
1.E-08
0
0
0.2
0.4
0.6
0.8
Gate Voltage (V)
Fig. 7 Id-Vg characteristics of 15nm Lg experimental
NMOS transistor with 0.8nm physical SiO 2 gate oxide.
15
20
25
-7.E-04
Vd =1.3V
1E -04
Vd =0.05V
1E -05
1E -06
Ion = 693 µA/µ m
Ioff = 25 n A /µ m
1E -07
1E -08
0.E+00
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vg (V)
Fig. 10 Id-Vds characteristics of the 80 nm Lg PMOS
transistors with high-K/metal-gate gate stack.
0.0016
0.0014
Ion = 1.5 mA/µm
Ioff = 43 nA/µm
Lg = 80nm
Toxe = 14.5A
0.0012
Id (A/µm)
1.E-05
1.E-07
Vds (V)
Vd=0.05V
1.E-04
1.E-06
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vd=1.3V
1.E-03
-3.E-04
-1.E-04
1E -10
1.E-02
-4.E-04
-2.E-04
Tox
T
o x ien v = 14A
14.5A
Fig. 9 Id-Vg characteristics of the 80 nm Lg PMOS
transistors with high-K/metal-gate gate stack at Vcc=1.3V.
Toxe = 14.5A
-5.E-04
Lg = 80nm
1E -09
Lg = 80nm
-6.E-04
Id (A/µm)
Id (A/µm)
10
tox,acc [A]
Fig. 8 Accumulation gate leakage as a function of electrical
thickness for high-K/metal-gate gate stacks. Also shown for
comparison is leakage for SiO 2/polySi gate stack.
1E -03
Id (A/µm)
5
0.001
0.0008
0.0006
1.E-08
Lg = 80nm
0.0004
1.E-09
Toxe = 14.5A
0.0002
0
1.E-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Vg (V)
Fig. 11 Id-Vg characteristics of the 80 nm Lg NMOS
transistors with high-K/metal-gate gate stack at Vcc=1.3V.
0
0.2 0.4 0.6 0.8
1
1.2 1.4
Vd (V)
Fig. 12 Id-Vds characteristics of the 80 nm Lg NMOS
transistors with high-K/metal-gate gate stack.
Robert Chau, Suman Datta, Mark Doczy, Jack Kavalieros and Matthew Metz
Intel Corporation
5200 N.E. Elam Young Parkway, Hillsboro, OR 97124, USA. Mail-stop: RA3-252
503-613-6141, robert.s.chau@intel.com
Abstract
We have successfully demonstrated very high-performance
PMOS and NMOS transistors with high-K/metal-gate gate
stacks with the right threshold voltages for both p- and nchannels on bulk Si. We believe that high-K/metal-gate is an
option for the 45nm high-performance logic technology node.
1. Introduction
The silicon industry has been scaling SiO2 aggressively for
the past 15 years for low-power, high-performance CMOS
logic applications. SiO2 as thin as 1.2nm (physical Tox) has
already been successfully implemented in the 90nm logic
technology node [ref. 1]. Research transistors with 0.8nm
SiO2 have also been demonstrated in the laboratory [ref. 2-3].
However, continual gate dielectric scaling will require highK, as SiO2 will eventually run out of atoms for further
scaling. Most of the high-K gate dielectrics investigated are
Hf-based and Zr-based [ref. 4-6]. Both polySi and metals are
being evaluated as gate electrodes for the high-K dielectrics
[ref. 7-9]. There are many challenges reported in literature in
replacing SiO2 with high-K for high-performance CMOS [ref.
10-12]. This paper will present results on the 0.8nm SiO2 and
very high-performance PMOS and NMOS transistors with
high-K/metal-gate for high-performance logic applications.
2. SiO2 Scaling
The physical thickness of SiO2 has been scaled aggressively
for low-power, high-performance logic applications. Figure 1
shows the physical thickness trend of SiO2 for the various
logic generations. 1.2nm physical SiO2 has already been
successfully implemented in the 90nm logic node [ref. 1]. In
addition, 0.8nm physical SiO2 has also been produced [ref. 23]. TEM cross sections of the 1.2nm and 0.8nm SiO2 gate
oxides are shown in Figures 2-3. The electrical C-V and IgVg characteristics of the 0.8nm SiO2 are shown in Figures 45. Figures 6-7 show the device characteristics of the
experimental 15nm (physical gate length) NMOS transistor
with 0.8nm SiO2 . The data shows that the 15nm transistor
with 0.8nm physical SiO2 has well-controlled short-channel
characteristics.
3. High-K Dielectrics
It has been reported in literature [ref. 12] that Fermi level
pinning at the high-K/polySi interface causes high threshold
voltages in MOSFET transistors. It has also been reported
that high-K/polySi transistor exhibits severely degraded
channel mobility due to the coupling of low energy surface
optical (SO) phonon modes arising from the polarization of
the high-K to the inversion channel charge carriers [ref. 13],
and that metal gate may be more effective in screening the
high-K SO phonons from coupling to the channel under
inversion conditions [ref. 13-14]. On the other hand, the use
of high-K/metal-gate requires a p-type metal and a n-type
metal with the right work functions for high-performance
CMOS logic applications on bulk Si [ref. 15].
We have successfully fabricated high-performance PMOS
and NMOS transistors with high-K/metal-gate stacks. The
transistors have physical gate length (Lg) of 80nm and the
electrical oxide thickness (Toxe) is 1.45nm measured at
inversion. Figure 8 compares the leakage characteristics of
the high-K/metal-gate stacks with the conventional
SiO2 /polySi. Figures 9-10 show the device characteristics of
the PMOS transistor with high-K/metal-gate, while Figures
11-12 show the device characteristics of the NMOS transistor
with high-K/metal-gate. Both the high-K/metal-gate PMOS
and NMOS transistors show very high drive performance
(Idsat) with the right Vth for both p- and n-channel
devices on bulk Si, with very low gate leakage.
4. From SiO2 to High-K
We have implemented 1.2nm physical SiO2 in our 90nm
logic technology node [1], and have scaled physical SiO2
further down to 0.8nm and integrated it in research transistors
with 15nm physical gate length which show well-controlled
short-channel characteristics. We have also successfully
demonstrated very high-performance PMOS and NMOS
transistors with high-K/metal-gate gate stacks with the right
Vth for both p- and n-channels on bulk Si, with very low gate
leakage. We believe high-K/metal-gate is an option for the
45nm logic technology node for high-performance CMOS.
5. References
[1] S. Thompson et al., IEDM Technical Digest, p.61, 2002.
[2] R. Chau et al., IEDM Technical Digest, p.45, 2000.
[3] R. Chau et al., Physica E, Low-dimensional Systems and Nanostructures,
Vol. 19, Issues 1-2, p.1, 2003.
[4] R. Choi et al., IEDM Technical Digest, p.613, 2002.
[5] G. Lucovsky et al., IEDM Technical Digest, p.617, 2002.
[6] S. Inumiya et al., Symp. of VLSI Technology, p.17, 2003.
[7] Y. Kim et al., Symp. of VLSI Technology, p.167, 2003.
[8] J.H. Lee et al., IEDM Technical Digest, p.359, 2002.
[9] S.B. Samavedam et al., IEDM Technical Digest, p.433, 2002.
[10] R.M. Wallace, G. Wilk, MRS Bulletin, Vol. 27, No. 3, p.192, 2002.
[11] V. Mistra et al., MRS Bulletin, Vol. 27, No. 3, p.212, 2002.
[12] C. Hobbs et al., Symp. of VLSI Technology, p.9, 2003.
[13] M. Fischetti et al., J. Appl. Phys., Vol. 90, p.4587, 2001.
[14] S. Datta et al., to be presented at 2003 IEDM.
[15] I. De at al., Solid State Electron., Vol. 44, p.1077, 2000.
100
Thickness (Å)
Gate
1.2nm SiO2
Silicon substrate
90 nm
130 nm
180 nm
350nm
250 nm
10
Fig. 2 High resolution TEM cross section of 1.2nm
physical SiO 2 gate oxide at the 90nm logic technology
node.
Capacitance
Capacitance ( µF/cm²)
(µF/cm²)
Fig. 1 Scaling of physical thickness of SiO 2 gate oxide
across technology generations.
PolySi
2.0
1.5
NMOS
NMOS
PMOS
PMOS
1.0
0.5
0.8nm
0.0
Silicon
-1
-0.5
0
Vg
Vg (V)
0.5
1
Inversion Capacitance
Fig. 3 High resolution TEM cross section of
physical SiO 2 gate oxide.
0.8nm
Fig. 4 Inversion split C-V measurements of 0.8nm
physical SiO 2 gate oxide for NMOS and PMOS.
1E+3
500
1E+2
µA/ µm)
1E-1
NMOS
Inversion
NMOS
1E-2
1E-4
PMOS
Inversion
Drain Current (
J g (A/cm²)
1E+0
1E-3
Vg = 0.8V
15nm NMOS
1E+1
1E-5
400
0.7V
300
0.6V
200
0.5V
0.4V
100
0.3V
1E-6
-1
-0.5
0
0.5
1
V g (Volts)
0
0
0.2
0.4
0.6
0.8
Drain Voltage (V)
Fig. 5 Inversion gate leakage measurements of 0.8nm
physical SiO 2 gate oxide for NMOS and PMOS.
Fig. 6 Id-Vds characteristics of 15nm Lg experimental
NMOS transistor with 0.8nm physical SiO 2 gate oxide.
1.E+02
15nm NMOS
Vd = 0.8V
SiO2/polySi
1.E+01
1.E-04
Vd = 0.05V
1.E-05
S.S. = 95mV/decade
DIBL = 100mV/V
Ioff = 180nA/um
1.E-06
1.E-07
Jox [A/cm 2 ]
Drain Current (A/µm)
1.E-03
1.E+00
1.E-01
1.E-02
High-K/metal-gate
1.E-03
1.E-04
1.E-08
0
0
0.2
0.4
0.6
0.8
Gate Voltage (V)
Fig. 7 Id-Vg characteristics of 15nm Lg experimental
NMOS transistor with 0.8nm physical SiO 2 gate oxide.
15
20
25
-7.E-04
Vd =1.3V
1E -04
Vd =0.05V
1E -05
1E -06
Ion = 693 µA/µ m
Ioff = 25 n A /µ m
1E -07
1E -08
0.E+00
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vg (V)
Fig. 10 Id-Vds characteristics of the 80 nm Lg PMOS
transistors with high-K/metal-gate gate stack.
0.0016
0.0014
Ion = 1.5 mA/µm
Ioff = 43 nA/µm
Lg = 80nm
Toxe = 14.5A
0.0012
Id (A/µm)
1.E-05
1.E-07
Vds (V)
Vd=0.05V
1.E-04
1.E-06
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vd=1.3V
1.E-03
-3.E-04
-1.E-04
1E -10
1.E-02
-4.E-04
-2.E-04
Tox
T
o x ien v = 14A
14.5A
Fig. 9 Id-Vg characteristics of the 80 nm Lg PMOS
transistors with high-K/metal-gate gate stack at Vcc=1.3V.
Toxe = 14.5A
-5.E-04
Lg = 80nm
1E -09
Lg = 80nm
-6.E-04
Id (A/µm)
Id (A/µm)
10
tox,acc [A]
Fig. 8 Accumulation gate leakage as a function of electrical
thickness for high-K/metal-gate gate stacks. Also shown for
comparison is leakage for SiO 2/polySi gate stack.
1E -03
Id (A/µm)
5
0.001
0.0008
0.0006
1.E-08
Lg = 80nm
0.0004
1.E-09
Toxe = 14.5A
0.0002
0
1.E-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Vg (V)
Fig. 11 Id-Vg characteristics of the 80 nm Lg NMOS
transistors with high-K/metal-gate gate stack at Vcc=1.3V.
0
0.2 0.4 0.6 0.8
1
1.2 1.4
Vd (V)
Fig. 12 Id-Vds characteristics of the 80 nm Lg NMOS
transistors with high-K/metal-gate gate stack.