Chau high k metal gate conf foils 110603
Gate Dielectric Scaling for
High-Performance CMOS:
from SiO2 to High-K
Robert Chau
Intel Fellow
Technology and Manufacturing Group
Intel Corporation
Nov 06 2003
Robert Chau
Intel Corporation
1
Content
• Introduction
• SiO2 Scaling
• Review on High-K Problems
• Significant Breakthroughs in High-K/Metal-Gate
• High-K/Metal-gate NMOS & PMOS Transistors
with Record-Setting Drive Performance
• Summary
Robert Chau
Intel Corporation
2
Introduction
• 1.2nm physical SiO2 in
production in our 90nm
logic technology node
100
Physical SiO2 Thickness
Thickness (Å)
• 0.8nm physical SiO2 in our
research transistors with
15nm physical Lg
• Gate leakage is increasing
with reducing physical
SiO2 thickness
90 nm
130 nm
180 nm
250 nm
350nm
10
• SiO2 running out of atoms
for further scaling
• Will eventually need high-K
Robert Chau
Intel Corporation
3
SiO2 Scaling
Gate
PolySi
1.2nm
1.2nm SiO
SiO2
PolySi
2
SiO2
Silicon
Silicon substrate
• 1.2nm physical SiO2 in production (90nm logic node)
• 0.8nm physical SiO2 in research transistors
Robert Chau
Intel Corporation
4
1E+3
2.0
1E+2
1.5
1E+1
NMOS
NMOS
PMOS
PMOS
1E+0
Jg (A/cm²)
Capacitance
Capacitance (µF/cm²)
(µF/cm²)
Electrical Characteristics of
0.8nm Physical SiO2
1.0
0.5
0.8nm
1E-1
NMOS
Inversion
NMOS
1E-2
1E-3
1E-4
PMOS
Inversion
1E-5
0.0
-1
-0.5
0
Vg
Vg (V)
0.5
1
1E-6
-1
-0.5
0
0.5
1
Vg (Volts)
Inversion Capacitance
Robert Chau
Intel Corporation
5
Research Transistor with 15nm
Physical Lg and 0.8nm Physical SiO2
Vd = 0.8V
0.8nm physical SiO2
Vd = 0.05V
1.E-05
S.S. = 95mV/decade
DIBL = 100mV/V
Ioff = 180nA/um
1.E-06
1.E-07
Vg = 0.8V
15nm NMOS
µ A/ µ m)
1.E-04
15nm NMOS
500
Drain Current (
Drain Current (A/µm)
1.E-03
0.8nm physical SiO2
400
0.7V
300
0.6V
200
0.5V
100
0.4V
0.3V
1.E-08
0
0
0.2
0.4
0.6
0.8
0
0.2
Gate Voltage (V)
0.4
0.6
0.8
Drain Voltage (V)
• Well-controlled short-channel characteristics
Robert Chau
Intel Corporation
6
Formation of High-K: Atomic Layer Deposition
MCl4 + 2H2O(g) -> M02 + 4HCl(g)
MCl4(g)
Step 1
Step 3
M02
Step 2
M = Zr, Hf
Step 4
• Sequential introduction of precursor molecules
MCl4(g), H2O(g)
Robert Chau
Intel Corporation
7
Review on High-K Problems
(High-K/PolySi-Gate)
• High-K and polySi gate are incompatible due
to Fermi level pinning at the high-K and
polySi interface which causes high threshold
voltages in transistors
• High-K/polySi transistors exhibit severely
degraded channel mobility due to the
coupling of SO phonon modes in high-K to
the inversion channel charge carriers
Robert Chau
Intel Corporation
8
High-K and PolySi are Incompatible
Poly Si
Interface
Si Si Si Si Si Si Si Si Si Si
Si Si
Si Si Si Si Si Si Si Si Si Si
Si Si
Si Si Si Si Si Si Si Si Si Si
Si Si
Si
Si
O
O
M
M
M
M
O
O
O
M
O
M
O
M
O
O
M
O
Si
M
O
O
O
O
O
O
O
M
M
M
M
O
O
O
M
O
M
O
Si Si
O
M
M
M
Si
O
O
M
M
M
Si Si
Si
O
M
O
Si
O
O
High-K
Si
M
O
M
O
O
O
M
O
M
O
M = Zr, Hf
O
M
O
O
• Defect formation at the polySi-high-K interface
Robert Chau
Intel Corporation
9
Experimental Evidence of
Phonon Scattering in High-K
4.5E-05
Coulombic Phonon
High-K/PolySi
3.5E-05
∂
1
µ Coul
∂T
3.0E-05
Phonon scattering
0
µCoul ↑ T ↑
SiO2/PolySi
∂
1
µ SR
∂T
1.5E-05
1.0E-05
0.1
µSR~
const
1
µ PH
∂T
2.0E-05
Surface
Roughness
µph ↓ T ↑
µ
d(1/ueff)/dT
4.0E-05
=0
E-Field
0.3
0.5
0.7
0.9
1.1
1.3
1.5
E-Field (MV/cm)
Robert Chau
Intel Corporation
1
µ eff
=
1
µ Coul
+
1
µ ph
+
1
µ SR
10
Review on High-K Problems
(High-K/Metal-Gate)
• Metal gate electrodes may be able to screen
the high-K SO phonons from coupling to the
inversion channel charge carriers and reduce
the mobility degradation problem
• However the use of high-K/metal-gate
requires metal gate electrodes with the
“correct” work functions on high-K for both
PMOS and NMOS transistors for high
performance
Robert Chau
Intel Corporation
11
Significant Breakthroughs in
High-K/Metal-Gate made by Intel
• N-type metal and P-type metal with the
correct work functions on high-K have been
engineered and demonstrated for highperformance CMOS
• High-K/metal-gate stack achieves NMOS and
PMOS channel mobility close to SiO2’s
• High-K/metal-gate stack shows significantly
lower gate leakage than SiO2
Robert Chau
Intel Corporation
12
P+ PolySi/SiO2
SDK
P-type Metal on High-K
Mid-gap Metal on High-K
NDK
N-type Metal on High-K
Metal J
Metal I
Metal H
Metal G
Metal F
Metal E
Metal D
Metal C
Metal B
Metal A
N-metal
P-metal
N+ PolySi/SiO2
P+poly
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
N+poly
Transistor Flatband Voltage (V)
We have Engineered N-type and P-type Metal
Electrodes on High-K with the “Correct” Work
Functions for NMOS and PMOS on Bulk Si
Gate Electrode Materials
Robert Chau
Intel Corporation
13
NMOS Mobility (cm 2/V.s)
High-K/Metal-Gate Stack Achieves
NMOS Channel Mobility Close to SiO2
Nitridation
SiO2/polyS
i
Optimizatio
n
SiO2/PolySi
High-K/Metal-Gate
TiN fill + improved
contact
W fill + improved contact
W fill + poor
contacts
Eeff
= 1.0MV/cm
20Å High-K/polySi
10 12 14 16 18 20 22 24 26
Inversion Electrical Thickness, Toxe (A)
Robert Chau
Intel Corporation
14
PMOS Mobility (cm2 /V.s)
High-K/Metal-Gate Stack Achieves
PMOS Channel Mobility Close to SiO2
SiO2/PolySi
High-K/Metal-Gate
Eeff = 1.0MV/cm
10
15
20
25
30
Inversion Electrical Thickness, Toxe (Å)
Robert Chau
Intel Corporation
15
High-K Reduces Gate Leakage
1.E+02
SiO2/polySi
Jox [A/cm 2 ]
1.E+01
1.E+00
1.E-01
1.E-02
High-K/metal-gate
1.E-03
1.E-04
0
5
10
15
20
25
Accumulation Electrical Tox [A]
Robert Chau
Intel Corporation
16
High-K/Metal-gate NMOS and PMOS
Transistors with Record-Setting
Drive Current (Idsat) Performance
• NMOS and PMOS high-K/metal-gate transistors
were made on bulk Si
– Physical gate length (Lg) = 80nm
– Electrical Oxide Thickness @ inversion (Toxe) = 1.45nm
• Very high NMOS Idsat
– Idsat = 1.66mA/um, Ioff = 37nA/um at Vcc = 1.3V
• Very high PMOS Idsat
– Idsat = 0.69mA/um, Ioff = 25nA/um at Vcc = 1.3V
Robert Chau
Intel Corporation
17
High-K/Metal-Gate NMOS Ion- Ioff
1.8
Ion (mA/µm)
1.6
1.4
Physical Gate Length
(Lg) ~80nm
1.2
1
• Electrical Tox at inversion
(Toxe) = 1.45nm
• Vcc = 1.3V
0.8
1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06
Ioff (A/µm)
Robert Chau
Intel Corporation
18
High-K/Metal-Gate NMOS with Record-Setting
Drive Current Performance
1.E-03
Vd=1.3V
1.E-04
Vd= 0.05V
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
Ion = 1.66mA/um
Ioff = 37nA/um
Id (A/µm)
Id (A/µm)
1.E-02
Lg = 80nm
Toxe = 14.5A
1.E-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Vg (V)
0.0018
0.0016
0.0014
0.0012
0.001
0.0008
0.0006
0.0004
0.0002
0
Lg = 80nm
Toxe = 14.5A
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Vd (V)
• Electrical Tox at Inversion (Toxe) = 1.45nm
• Transistor physical gate length (Lg) = 80nm
Robert Chau
Intel Corporation
19
High-K/Metal-Gate PMOS with Record-Setting
Drive Current Performance
1E-03
1E-05
1E-06
1E-07
Vd=1.3V
-6.E-04
Vd=0.05V
Ion = 693 µA/µm
Ioff = 25 nA/µm
Id (A /µm )
Id (A/µm)
1E-04
-7.E-04
-5.E-04
Toxe = 14.5A
-4.E-04
-3.E-04
1E-08
Lg = 80nm
-2.E-04
1E-09
Toxe = 14.5A
-1.E-04
1E-10
Lg = 80nm
0.E+00
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vg (V)
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vds (V)
• Electrical Tox at Inversion (Toxe) = 1.45nm
• Transistor physical gate length (Lg) = 80nm
Robert Chau
Intel Corporation
20
Summary
• We have implemented 1.2nm physical SiO2 in our
90nm logic technology node and products, and
have demonstrated 0.8nm physical SiO2
• We have engineered and demonstrated NMOS and
PMOS high-K/metal-gate stacks on bulk Si with i)
the correct work functions, ii) channel mobility
close to SiO2’s and iii) very low gate leakage
• We have fabricated high-K/metal-gate NMOS and
PMOS transistors on bulk Si with record-setting
drive current performance
• We believe high-K/metal-gate is an option for the
45nm logic technology node, to be in production
in 2007
Robert Chau
Intel Corporation
21
High-Performance CMOS:
from SiO2 to High-K
Robert Chau
Intel Fellow
Technology and Manufacturing Group
Intel Corporation
Nov 06 2003
Robert Chau
Intel Corporation
1
Content
• Introduction
• SiO2 Scaling
• Review on High-K Problems
• Significant Breakthroughs in High-K/Metal-Gate
• High-K/Metal-gate NMOS & PMOS Transistors
with Record-Setting Drive Performance
• Summary
Robert Chau
Intel Corporation
2
Introduction
• 1.2nm physical SiO2 in
production in our 90nm
logic technology node
100
Physical SiO2 Thickness
Thickness (Å)
• 0.8nm physical SiO2 in our
research transistors with
15nm physical Lg
• Gate leakage is increasing
with reducing physical
SiO2 thickness
90 nm
130 nm
180 nm
250 nm
350nm
10
• SiO2 running out of atoms
for further scaling
• Will eventually need high-K
Robert Chau
Intel Corporation
3
SiO2 Scaling
Gate
PolySi
1.2nm
1.2nm SiO
SiO2
PolySi
2
SiO2
Silicon
Silicon substrate
• 1.2nm physical SiO2 in production (90nm logic node)
• 0.8nm physical SiO2 in research transistors
Robert Chau
Intel Corporation
4
1E+3
2.0
1E+2
1.5
1E+1
NMOS
NMOS
PMOS
PMOS
1E+0
Jg (A/cm²)
Capacitance
Capacitance (µF/cm²)
(µF/cm²)
Electrical Characteristics of
0.8nm Physical SiO2
1.0
0.5
0.8nm
1E-1
NMOS
Inversion
NMOS
1E-2
1E-3
1E-4
PMOS
Inversion
1E-5
0.0
-1
-0.5
0
Vg
Vg (V)
0.5
1
1E-6
-1
-0.5
0
0.5
1
Vg (Volts)
Inversion Capacitance
Robert Chau
Intel Corporation
5
Research Transistor with 15nm
Physical Lg and 0.8nm Physical SiO2
Vd = 0.8V
0.8nm physical SiO2
Vd = 0.05V
1.E-05
S.S. = 95mV/decade
DIBL = 100mV/V
Ioff = 180nA/um
1.E-06
1.E-07
Vg = 0.8V
15nm NMOS
µ A/ µ m)
1.E-04
15nm NMOS
500
Drain Current (
Drain Current (A/µm)
1.E-03
0.8nm physical SiO2
400
0.7V
300
0.6V
200
0.5V
100
0.4V
0.3V
1.E-08
0
0
0.2
0.4
0.6
0.8
0
0.2
Gate Voltage (V)
0.4
0.6
0.8
Drain Voltage (V)
• Well-controlled short-channel characteristics
Robert Chau
Intel Corporation
6
Formation of High-K: Atomic Layer Deposition
MCl4 + 2H2O(g) -> M02 + 4HCl(g)
MCl4(g)
Step 1
Step 3
M02
Step 2
M = Zr, Hf
Step 4
• Sequential introduction of precursor molecules
MCl4(g), H2O(g)
Robert Chau
Intel Corporation
7
Review on High-K Problems
(High-K/PolySi-Gate)
• High-K and polySi gate are incompatible due
to Fermi level pinning at the high-K and
polySi interface which causes high threshold
voltages in transistors
• High-K/polySi transistors exhibit severely
degraded channel mobility due to the
coupling of SO phonon modes in high-K to
the inversion channel charge carriers
Robert Chau
Intel Corporation
8
High-K and PolySi are Incompatible
Poly Si
Interface
Si Si Si Si Si Si Si Si Si Si
Si Si
Si Si Si Si Si Si Si Si Si Si
Si Si
Si Si Si Si Si Si Si Si Si Si
Si Si
Si
Si
O
O
M
M
M
M
O
O
O
M
O
M
O
M
O
O
M
O
Si
M
O
O
O
O
O
O
O
M
M
M
M
O
O
O
M
O
M
O
Si Si
O
M
M
M
Si
O
O
M
M
M
Si Si
Si
O
M
O
Si
O
O
High-K
Si
M
O
M
O
O
O
M
O
M
O
M = Zr, Hf
O
M
O
O
• Defect formation at the polySi-high-K interface
Robert Chau
Intel Corporation
9
Experimental Evidence of
Phonon Scattering in High-K
4.5E-05
Coulombic Phonon
High-K/PolySi
3.5E-05
∂
1
µ Coul
∂T
3.0E-05
Phonon scattering
0
µCoul ↑ T ↑
SiO2/PolySi
∂
1
µ SR
∂T
1.5E-05
1.0E-05
0.1
µSR~
const
1
µ PH
∂T
2.0E-05
Surface
Roughness
µph ↓ T ↑
µ
d(1/ueff)/dT
4.0E-05
=0
E-Field
0.3
0.5
0.7
0.9
1.1
1.3
1.5
E-Field (MV/cm)
Robert Chau
Intel Corporation
1
µ eff
=
1
µ Coul
+
1
µ ph
+
1
µ SR
10
Review on High-K Problems
(High-K/Metal-Gate)
• Metal gate electrodes may be able to screen
the high-K SO phonons from coupling to the
inversion channel charge carriers and reduce
the mobility degradation problem
• However the use of high-K/metal-gate
requires metal gate electrodes with the
“correct” work functions on high-K for both
PMOS and NMOS transistors for high
performance
Robert Chau
Intel Corporation
11
Significant Breakthroughs in
High-K/Metal-Gate made by Intel
• N-type metal and P-type metal with the
correct work functions on high-K have been
engineered and demonstrated for highperformance CMOS
• High-K/metal-gate stack achieves NMOS and
PMOS channel mobility close to SiO2’s
• High-K/metal-gate stack shows significantly
lower gate leakage than SiO2
Robert Chau
Intel Corporation
12
P+ PolySi/SiO2
SDK
P-type Metal on High-K
Mid-gap Metal on High-K
NDK
N-type Metal on High-K
Metal J
Metal I
Metal H
Metal G
Metal F
Metal E
Metal D
Metal C
Metal B
Metal A
N-metal
P-metal
N+ PolySi/SiO2
P+poly
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
N+poly
Transistor Flatband Voltage (V)
We have Engineered N-type and P-type Metal
Electrodes on High-K with the “Correct” Work
Functions for NMOS and PMOS on Bulk Si
Gate Electrode Materials
Robert Chau
Intel Corporation
13
NMOS Mobility (cm 2/V.s)
High-K/Metal-Gate Stack Achieves
NMOS Channel Mobility Close to SiO2
Nitridation
SiO2/polyS
i
Optimizatio
n
SiO2/PolySi
High-K/Metal-Gate
TiN fill + improved
contact
W fill + improved contact
W fill + poor
contacts
Eeff
= 1.0MV/cm
20Å High-K/polySi
10 12 14 16 18 20 22 24 26
Inversion Electrical Thickness, Toxe (A)
Robert Chau
Intel Corporation
14
PMOS Mobility (cm2 /V.s)
High-K/Metal-Gate Stack Achieves
PMOS Channel Mobility Close to SiO2
SiO2/PolySi
High-K/Metal-Gate
Eeff = 1.0MV/cm
10
15
20
25
30
Inversion Electrical Thickness, Toxe (Å)
Robert Chau
Intel Corporation
15
High-K Reduces Gate Leakage
1.E+02
SiO2/polySi
Jox [A/cm 2 ]
1.E+01
1.E+00
1.E-01
1.E-02
High-K/metal-gate
1.E-03
1.E-04
0
5
10
15
20
25
Accumulation Electrical Tox [A]
Robert Chau
Intel Corporation
16
High-K/Metal-gate NMOS and PMOS
Transistors with Record-Setting
Drive Current (Idsat) Performance
• NMOS and PMOS high-K/metal-gate transistors
were made on bulk Si
– Physical gate length (Lg) = 80nm
– Electrical Oxide Thickness @ inversion (Toxe) = 1.45nm
• Very high NMOS Idsat
– Idsat = 1.66mA/um, Ioff = 37nA/um at Vcc = 1.3V
• Very high PMOS Idsat
– Idsat = 0.69mA/um, Ioff = 25nA/um at Vcc = 1.3V
Robert Chau
Intel Corporation
17
High-K/Metal-Gate NMOS Ion- Ioff
1.8
Ion (mA/µm)
1.6
1.4
Physical Gate Length
(Lg) ~80nm
1.2
1
• Electrical Tox at inversion
(Toxe) = 1.45nm
• Vcc = 1.3V
0.8
1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06
Ioff (A/µm)
Robert Chau
Intel Corporation
18
High-K/Metal-Gate NMOS with Record-Setting
Drive Current Performance
1.E-03
Vd=1.3V
1.E-04
Vd= 0.05V
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
Ion = 1.66mA/um
Ioff = 37nA/um
Id (A/µm)
Id (A/µm)
1.E-02
Lg = 80nm
Toxe = 14.5A
1.E-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Vg (V)
0.0018
0.0016
0.0014
0.0012
0.001
0.0008
0.0006
0.0004
0.0002
0
Lg = 80nm
Toxe = 14.5A
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Vd (V)
• Electrical Tox at Inversion (Toxe) = 1.45nm
• Transistor physical gate length (Lg) = 80nm
Robert Chau
Intel Corporation
19
High-K/Metal-Gate PMOS with Record-Setting
Drive Current Performance
1E-03
1E-05
1E-06
1E-07
Vd=1.3V
-6.E-04
Vd=0.05V
Ion = 693 µA/µm
Ioff = 25 nA/µm
Id (A /µm )
Id (A/µm)
1E-04
-7.E-04
-5.E-04
Toxe = 14.5A
-4.E-04
-3.E-04
1E-08
Lg = 80nm
-2.E-04
1E-09
Toxe = 14.5A
-1.E-04
1E-10
Lg = 80nm
0.E+00
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vg (V)
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
Vds (V)
• Electrical Tox at Inversion (Toxe) = 1.45nm
• Transistor physical gate length (Lg) = 80nm
Robert Chau
Intel Corporation
20
Summary
• We have implemented 1.2nm physical SiO2 in our
90nm logic technology node and products, and
have demonstrated 0.8nm physical SiO2
• We have engineered and demonstrated NMOS and
PMOS high-K/metal-gate stacks on bulk Si with i)
the correct work functions, ii) channel mobility
close to SiO2’s and iii) very low gate leakage
• We have fabricated high-K/metal-gate NMOS and
PMOS transistors on bulk Si with record-setting
drive current performance
• We believe high-K/metal-gate is an option for the
45nm logic technology node, to be in production
in 2007
Robert Chau
Intel Corporation
21