Revision 1.0 MultiMediaCardRS-MultiMediaCard Product Manual
© 2004 SanDisk Corporation 4-22
051304
4 R3 OCR register: response length 48 bits.
The contents of the OCR Register are sent as a response to CMD1.
Table 4-10 Response R3
Bit Position
47 46 [45:40]
[39:8] [7:1]
Width bits
1 1 6 32 7 1
Value
0 0 111111
x 111111
1
Description
start bit transmission bit
reserved OCR Register reserved
end bit
R4 and R5: responses are not supported.
4.8 Timing Diagrams
All timing diagrams use schematics and abbreviations listed in Table 4-11.
Table 4-11 Timing Diagram Symbols
Symbol Definition
S Start Bit = 0
T Transmitter Bit Host = 1, Card = 0
P One-cycle pull-up = 1
E End Bit = 1
Z High Impedance State - = 1
D Data bits
X Repeater CRC
Cyclic Redundancy Check Bits 7 bits Card
active Host
active
4.8.1 Command and Response
Card Identification and Card Operation Conditions Timing
The card identification CMD2 and card operation conditions CMD1 timing are processed in the open-drain mode. The card response to the host command starts after
exactly NID clock cycles.
Identification Timing Card ID Mode
S T Content
E Z Z S T
Z Z Z Host Command
N
ID
CMD CRC
Content CID or OCR
Cycles
Revision 1.0 MultiMediaCardRS-MultiMediaCard Product Manual
© 2004 SanDisk Corporation 4-23
051304
The minimum delay between the host command and card response is N
CR
clock cycles. This timing diagram is relevant for host command CMD3.
Command Response Timing ID Mode
Data Transfer Mode
There is just one Z bit period followed by P bits pushed up by the responding card. This timing diagram is relevant for all responded host commands except CMD1, 2, 3.
Command Response Timing Data Transfer Mode
Last Card Response—Next Host Command Timing
After receiving the last card response, the host can start the next command transmission after at least N
RC
clock cycles. This timing is relevant for any host command. Timing Response End to Next CMD Start Data Transfer Mode
Last Host Command—Next Host Command Timing
After the last command has been sent, the host can continue sending the next command after at least N
CC
clock periods. This timing is relevant for any host command that does not have a response.
Timing CMD
n
End to CMD
n+1
Start all modes
In the case where the CMD
n
command was a last acquisition command with no further response by any card, then the next CMD
n+1
command is allowed to follow after at least N
CC
+136 the length of the R2 response clock periods.
CMD S T Content
E Z Z S T
Z Z Z
Host Command N
CR
CRC Response
Cycles Content
CRC Z
E
CMD S T Content
E Z P S T
Z Z Z
Host Command N
CR
CRC Response
Cycles Content
CRC Z
E Z P
CMD S T Content
E Z Z S T
Z Response
N
RC
CRC Host Command
Cycles Content
CRC E
CMD S T Content
E Z Z S T
Z Host Command
N
CC
CRC Host Command
Cycles Content
CRC E
Revision 1.0 MultiMediaCardRS-MultiMediaCard Product Manual
© 2004 SanDisk Corporation 4-24
051304
4.9 Data Read
