Command and Response Data Read

Revision 1.0 MultiMediaCardRS-MultiMediaCard Product Manual © 2004 SanDisk Corporation 5-18 051304

5.22 Card Registers

In SPI Mode, only the OCR, CSD and CID registers are accessible. Although the registers’ format is identical to those in MultiMediaCard Mode, a few fields are irrelevant in SPI Mode.

5.23 SPI Bus Timing Diagrams

All timing diagrams use the schematics and abbreviations listed in Table 5-10. Table 5-10 SPI Bus Timing Abbreviations Symbol Definition H Signal is high logical 1 L Signal is low logical 0 X Don’t care undefined value Z High impedance state - = 1 Repeater Busy Busy token Command Command token Response Response token Data block Data token The host must keep the clock running for at least N CR clock cycles after the card response is received. This restriction applies to command and data response tokens.

5.23.1 Command and Response

This section provides valuable information on commands and responses. Host Command to Card Response—Card is Ready Figure 5-20 describes the basic command response no data in an SPI transaction. Figure 5-20 Host Command to Card Response—Card is Ready Host Command to Card Response--Card is Busy The timing diagram in Figure 5-21 illustrates the command response transaction for commands when the card response is of type R1b—for example, SET_WRITE_PROT and ERASE. When the card is signaling busy, the host may de-select it by raising the CS at any time. The card will release the DataOut line one clock after CS goes high. To check if the card is still busy, it needs to be re-selected by asserting the CS signal set to low. The card will resume the busy signal, pulling DataOut low, one clock after the falling edge of CS. H H H H H L X H X Z Z H H Z H H H H H X X X X L H H H H L L H Z 1 or 2 Bytes Response H DataIn CS DataOut H H H H H H H L H 6 Bytes Command Z H L L H H H H H H N CR N CS N EC Revision 1.0 MultiMediaCardRS-MultiMediaCard Product Manual © 2004 SanDisk Corporation 5-19 051304 Figure 5-21 Command Response Transaction Timing, Card is Busy Card Response to Host Command Figure 5-22 Card Response to Next Host Command Timing

5.23.2 Data Read

This section provides valuable information on the Data Read function. Card Response to Host Command Figure 5-23 Single Block Read Transaction Timing Multiple Block Read— Stop transmission is sent between blocks Figure 5-24 Multiple Block Transaction Timing no data overlap The timing for de-asserting the CS signal after the last card response is identical to a standard commandresponse transaction. Multiple Block Read—Stop transmission is sent within a block Figure 5-25 Multiple Block Transaction data overlap H H H H H L X H H H Z Z H H H H H N CR N CS L H H H H X X X X N AC L H N EC H H Data Block H H H H H L L L H H Z Z Z H H H Read Command H H H Card Response DataIn CS DataOut H L L L L L X H H H Z Z H H H H H H H H N CR N C S L H H H H H H H H N AC L H H H H H N AC N C R StopCommand H H Data Block Data Block H H H H Card Resp Card Resp H H Read Command DataIn CS DataOut H L L L L L X H H H H H H H H Z Z H H H H H H H H H Data Read Command Card Resp N CR N C S L H H Card Resp H H H H H H H H N AC L X X H Data Block H H H H H H N AC N C R StopCommand DataIn CS DataOut H H H L L L X H H Z Z H H H N CR N CS L H H H H X X H H L N EC H H Busy H H L L L H Z H 6 Bytes Command H Card Response DataIn CS DataOut L H H H L L L L H H H H L H H H H H H H H H X X X H H H H Z Z Z Busy N EC N DS L H H H H L H H H H H H H H N CR L H H H H X X X H L H H H H L L H Z 1 or 2 Bytes Response H DataIn CS DataOut H H H H H H H L H 6 Bytes Command Z H Revision 1.0 MultiMediaCardRS-MultiMediaCard Product Manual © 2004 SanDisk Corporation 5-20 051304 The Stop Transmission command may be sent asynchronously to the data transmitted out of the card and may overlap the data block. In this case the card will stop sending the data and transmit the response token as well. The delay between command and response is standard N CR clocks. The first byte, however, is not guaranteed to be all set to ‘1.’ The card is allowed up to two clocks to stop data transmission. The timing for de-asserting the CS signal after the last card response is identical to a standard commandresponse transaction. Reading the CSD Register The following timing diagram describes the SEND_CSD command bus transaction. The timeout values between the response and the data block are N CX because the N AC remains unknown. Figure 5-26 Read CSD Register Timing

5.23.3 Data Write