Sample-and-Hold Sampling

7.4.1 Sample-and-Hold Sampling

In an actual ADC the time required to do the sampling, quantization, and coding needs to be con- sidered. Therefore, the width 1 of the sampling pulses cannot be zero as assumed. A sample-and-hold sampling system takes the sample and holds it long enough for quantization and coding to be done before the next sample is acquired. The question is then how does this affect the sampling process and how does it differ from the ideal results obtained before? We hinted at the effects when we considered the PAM before, except that now the resulting pulses are flat.

C H A P T E R 7: Sampling Theory

t Sampling using a sample-and-hold system (δ

0 =T T

s ).

The system shown in Figure 7.10 generates the desired signal. Basically, we are modulating the ideal sampling signal δ T s ( t) with the analog input x(t), giving an ideally sampled signal x s ( t). This signal is then passed through a zero-order hold filter, an LTI system having as impulse response h(t) a pulse of the desired width 1 ≤T s . The output of the sample-and-hold system is a weighted sequence of shifted versions of the impulse response. In fact, the output of the ideal sampler is x s ( t) = x(t)δ T s ( t), and using the linearity and time invariance of the zero-order hold system its output is

(7.20) with a Fourier transform of

y s ( t) = (x s ∗ h)(t)

where the term in the brackets is the spectrum of the ideally sampled signal and

e −1s/2

H( j)

1 = s/2 ( e −e −1s/2 ) | s

=j

sin(1/2)

e −j1/2

is the frequency response of the LTI system.

Remarks

Equation (7.20) can be written as

s ( t) =

x(nT s ) h(t − nT s )

That is, y s ( t) is a train of pulses h(t) = u(t) − u(t − 1) shifted and weighted by the sample values x(nT s ) ,

a more realistic representation of the sampled signal.

7.4 Practical Aspects of Sampling 441

x (t)

x sh (t )

FIGURE 7.11 Sample-and-hold circuit.

Two significant changes due to considering the pulses of width 1 > 0 in the sampling are:

The spectrum of the ideal sampled signal x s ( t) is now weighted by the sinc function of the frequency response H( j) of the zero-order hold filter. Thus, the spectrum of the sampled signal using the sample- and-hold system will not be periodic and will decay as  increases.

The reconstruction of the original signal x(t) requires a more complex filter than the one used in the ideal sampling. Indeed, the concatenation of the zero-order hold filter with the reconstruction filter should be such that H(s)H r ( s) = 1, or that H r ( s) = 1/H(s).

A circuit used for implementing the sample-and-hold system is shown in Figure 7.11. In this circuit the switch closes every T s seconds and remains closed for a short time 1. If the time constant rC << 1, the capacitor charges very fast to the value of the sample attained when the switch closes at some nT s , and by setting the time constant RC >> T s when the switch opens 1 seconds later, the capacitor slowly discharges. The cycle repeats providing a signal that approximates the output of the sample-and-hold system explained before.

The DAC also uses a holder to generate an analog signal from the discrete signal coming out of the decoder into the DAC. There are different possible types of holders, providing an interpolation that will make the final smoothing of the signal a lot easier. The so-called zero-order hold basically expands the sample value in between samples, providing a rough approximation of the discrete signal, which is then smoothed out by a low-pass filter to provide the analog signal.