Power MOSFET IRF530, SiHF530

   Power MOSFET FEATURES PRODUCT SUMMARY

  • Dynamic dV/dt Rating

  V (V) 100

  DS Available

  • Repetitive Avalanche Rated

  R (Ω) V = 10 V

  0.16 DS(on) GS

  RoHS*

  • 175 °C Operating Temperature

  Q (Max.) (nC)

  26 COMPLIANT

  g

  • Fast Switching

  Q (nC)

  5.5

  gs

  • Ease of Paralleling

  Q (nC)

  11

  gd

  • Simple Drive Requirements

  Configuration Single

  • Lead (Pb)-free Available

  D DESCRIPTION TO-220

  Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, G ruggedized device design, low on-resistance and cost-effectiveness.

  The TO-220 package is universally preferred for all

  S D commercial-industrial applications at power dissipation

  S

  G

  levels to approximately 50 W. The low thermal resistance N

  • Channel MOSFET

  and low package cost of the TO-220 contribute to its wide acceptance throughout the industry.

ORDERING INFORMATION

  Package TO-220

  IRF530PbF Lead (Pb)-free

  SiHF530-E3

  IRF530 SnPb

  SiHF530

  ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted

  C

PARAMETER SYMBOL LIMIT UNIT

  Drain-Source Voltage V 100

  DS

  V Gate-Source Voltage V ±

  20 GS T = 25 °C

  14 C Continuous Drain Current V at 10 V

  I GS D T = 100 °C

  10 A

  C a

  Pulsed Drain Current

  I

  56 DM Linear Derating Factor

  0.59 W/°C

  b

  Single Pulse Avalanche Energy E 69 mJ

  AS a

  Repetitive Avalanche Current

  I

  14 A

  AR a

  Repetitive Avalanche Energy E 8.8 mJ

  AR

  Maximum Power Dissipation T = 25 °C P

  88 W

  C D c

  Peak Diode Recovery dV/dt dV/dt 5.5 V/ns

  Operating Junction and Storage Temperature Range T , T - 55 to + 175

  J stg

  °C

  d

  Soldering Recommendations (Peak Temperature) for 10 s 300 10 lbf · in Mounting Torque 6-32 or M3 screw

  1.1 N · m

  Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

  b. V DD = 25 V, starting T J = 25 °C, L = 528 µH, R G = 25 Ω, I AS = 14 A (see fig. 12).

  c. I SD ≤ 14 A, dI/dt ≤ 140 A/µs, V DD ≤ V DS , T J ≤ 175 °C.

  d. 1.6 mm from case.

  • Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91019

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  • 62
  • 1.7

  • 670 -
  • 250 - Reverse Transfer Capacitance C
  • 60 -
  • 10 - ns
  • 34 -
  • 23 -
  • 24 -
  • 4.5 - nH
  • 7.5 -
  • 150 280 ns
  • 0.85

  S

  Internal Source Inductance L

  Between lead, 6 mm (0.25") from package and center of die contact

  D

  Internal Drain Inductance L

  f

  Fall Time t

  d(off)

  Turn-Off Delay Time t

  r

  Rise Time t

  b

  V DD = 50 V, I D = 14 A R G = 12 Ω, R D = 3.6 Ω, see fig. 10

  d(on)

  11 Turn-On Delay Time t

  gd

  5.5 Gate-Drain Charge Q

  gs

  26 Gate-Source Charge nC Q

  b

  = 80 V, see fig. 6 and 13

  DS

  I D = 14 A, V

  V GS = 10 V

  g

  Total Gate Charge Q

  rss

  Drain-Source Body Diode Characteristics

  Continuous Source-Drain Diode Current

  I S MOSFET symbol showing the integral reverse p - n junction diode

  T

  D

  and L

  S

  Intrinsic turn-on time is negligible (turn-on is dominated by L

  1.7 µC Forward Turn-On Time t on

  rr

  Body Diode Reverse Recovery Charge Q

  b

  = 14 A, dI/dt = 100 A/µs

  F

  = 25 °C, I

  J

  rr

  14 A Pulsed Diode Forward Current

  2.5 V Body Diode Reverse Recovery Time t

  b

  = 0 V

  GS

  = 14 A, V

  S

  = 25 °C, I

  J

  V SD T

  56 Body Diode Voltage

  I SM

  a

  oss

  V DS = 25 V, f = 1.0 MHz, see fig. 5

  Output Capacitance pF C

  V GS = 0 V, I

  Gate-Source Threshold Voltage

  = 1 mA - 0.12 - V/°C

  D

  Reference to 25 °C, I

  J

  /T

  DS

  Temperature Coefficient ΔV

  DS

  V V

  = 250 µA 100 - -

  D

  V DS

  V DS = V GS , I D = 250 µA 2.0 -

  Drain-Source Breakdown Voltage

  SPECIFICATIONS T J = 25 °C, unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

  thJC

  0.50 - Maximum Junction-to-Case (Drain) R

  thCS

  °C/W Case-to-Sink, Flat, Greased Surface R

  thJA

  Maximum Junction-to-Ambient R

  THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT

  b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.

  Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

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  V GS(th)

  4.0 V Gate-Source Leakage

  V GS = 0 V,

  V GS = 10 V

  iss

  Input Capacitance C

  Dynamic

  5.1 - - S

  b

  = 8.4 A

  D

  V DS = 50 V, I

  fs

  0.16 Ω Forward Transconductance g

  b

  I D = 8.4 A

  DS(on)

  I GSS

  Drain-Source On-State Resistance R

  = 150 °C - - 250

  J

  = 0 V, T

  GS

  V DS = 80 V, V

  25 µA

  = 0 V - -

  GS

  V DS = 100 V, V

  I DSS

  ± 100 nA Zero Gate Voltage Drain Current

  V GS = ± 20 V - -

  ) D S G S D G TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Fig. 1 - Typical Output Characteristics, T = 25 °C Fig. 3 - Typical Transfer Characteristics

  C Fig. 2 - Typical Output Characteristics, T C = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature

  Document Number: 91019 www.vishay.com

  Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area

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  R D

  V DS

  V GS D.U.T. R G

  • V - DD

  10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 %

  Fig. 10a - Switching Time Test Circuit

  V DS 90 % 10 %

  V GS t t t t d(on) r d(off) f

  Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L

  V DS

  V DS V ary t to obtain p t p required I

  AS

  V DD R D.U.T

  • G

  V

  • DD

  V DS

  I AS

  10 V t p 0.01 Ω

  I AS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

  Document Number: 91019 www.vishay.com

  

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator Same type as D.U.T.

  50 kΩ Q G

10 V

  12 V 0.2 µF 0.3 µF Q Q

  • GS GD

  V DS D.U.T. -

  V G

  V GS 3 mA

  Charge

  I I G D Current sampling resistors Fig. 13b - Gate Charge Test Circuit Fig. 13a - Basic Gate Charge Waveform

  www.vishay.com Document Number: 91019

  Peak Diode Recovery dV/dt Test Circuit Circuit layout considerations + D.U.T.

  • Low stray inductance
  • Ground plane
  • Low leakage inductance current transformer
    • R

  G

  • • dV/dt controlled by R

    + G

  V • Driver same type as D.U.T.

  DD

  • I controlled by duty factor "D"

  SD

  • D.U.T. - device under test

  Driver gate drive P.W.

  Period D = Period

P.W.

  V = 10 V* GS w D.U.T. I aveform

  SD Reverse recovery Body diode forward current current dI/dt w D.U.T. V aveform

  DS Diode recovery dV/dt

  V DD Re-applied v oltage

  Body diode forward drop Inductor current

  I SD Ripple ≤ 5 %

  • V = 5 V for logic level devices

  GS

Fig. 14 - For N-Channel

  

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see http://www.vishay.com/ppg?91019.

  Document Number: 91019 www.vishay.com

  

Disclaimer

All product specifications and data are subject to change without notice.

  

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf

(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein

or in any other disclosure relating to any product.

Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any

information provided herein to the maximum extent permitted by law. The product specifications do not expand or

otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed

therein, which apply to these products.

  

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this

document or by any conduct of Vishay.

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless

otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such

applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting

from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding

products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.

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