Processing Transformation of data Implemented using processors Storage Retention of data Implemented using memory Communication Transfer of data between processors and memories Implemented using buses Called interfacing

  Interfacing Interfacing

  Introduction Introduction Addressing Addressing Interrupt Interrupt

  DMA DMA Arbitration Arbitration Advanced communication architectures Advanced communication architectures

  Vahid, Givargis Vahid, Givargis Introduction

  Introduction Embedded system functionality aspects

  Processing Transformation of data Implemented using processors Storage Retention of data Implemented using memory

  Communication Transfer of data between processors and memories Implemented using buses Called interfacing

  Vahid, Givargis Vahid, Givargis

• 2 - -

  2 A simple bus A simple bus

  Wires: Uni-directional or bi-directional One line may represent multiple wires

  Bus Sets of wires with a single function Address bus, data bus, control bus Single set of wires collecting all functions

  rd'/wr cpu memory enable addr[0:15] data[0:7]

  Vahid, Givargis

  3 3 - - Vahid, Givargis Timing Diagrams Timing Diagrams

  Common method for describing a protocol Time proceeds to the right on the x axis

  Control signal: Active high: wr Asserted when 1 Active low: wr Asserted when 0

  Data signal: Valid: Data on the bus can be read/written Not valid Data on the bus is meaningless

  Vahid, Givargis

  4 4 - - Timing Diagrams Timing Diagrams

• Vahid, Givargis

  Protocol: Defines how communication takes place May have subprotocols

  Bus cycles Each bus cycle may be several clock cycles Vahid, Givargis

  5 - - Timing Diagrams: Read example

• 5 - Vahid, Givargis

  Timing Diagrams: Read example

  1

  rd'/wr

  3

  enable

  2

  addr

  4

  data T T

  setup read 1 rd' asserted

  starts read bus cycle

  2

  address placed on addr address must be stable at least T before enable asserted

  setup 3 enable asserted

  Triggers memory to place data on data wires Not later than after the time delay T

  read

  4

  data ready on data wires

  Vahid, Givargis Vahid, Givargis

  6 6 - -

  1

4 Vahid, Givargis Vahid, Givargis

  Share a single set of wires for multiple pieces of data Subsequent bytes of a word Data/Address Saves wires at expense of time

  Sender: Data source Receiver: Data destination Time multiplexing

  Master: initiates the communication Slave: responds to master Direction

  Basic protocol concepts Actor

  8 8 - - Basic protocol concepts

  3

  2

  4

  3

  2

  1

  write

  before enable asserted enable asserted triggers memory save data found on data wires must remain asserted for at least T

  setup

  before enable asserted data placed on data wires data must be stable at least T

  setup

  wr asserted starts write bus cycle address placed on addr address must be stable at least T

  write

  T

  setup

  rd'/wr enable addr data T

  Timing Diagrams: Write example

  7 7 - - Timing Diagrams: Write example

  Vahid, Givargis Vahid, Givargis

Time multiplexing Time multiplexing

  req req master slave master slave

  data[0:15] data[0:15] data addr data addr mux demux mux demux

  d[0:7] d[0:15] req req

  data[8:15] data[0:7] addr[0:15] data[0:15]

  d d

• Vahid, Givargis

  9 Vahid, Givargis 9 - - Strobe protocol

  Strobe protocol

  req

  1 Master asserts req to receive data

  master slave

  2 Slave puts data on bus

  Within T

  

a

  d[0:7]

  

2 3 Master receives data

  3 Master deasserts req

  4 Slave ready for next request

  req data T

  a

  1

  2

  3

4 Vahid, Givargis Vahid, Givargis

  10 10 - - Handshake protocol Handshake protocol

  req

  1 Master asserts req to receive data

  master slave ack

  2 Slave puts data on bus

  3 Slave asserts ack

  d[0:7]

  3

  4 Master receives data

  4 Master deasserts req

  req

  5 Slave deasserts ack

  Slave ready for next request ack data

  1

  2

  3

  4

  5 Vahid, Givargis Vahid, Givargis

  11 11 - Strobe/handshake protocol: Fast Strobe/handshake protocol: Fast

  req

  1 Master asserts req to receive data

  master slave wait

  2 Slave puts data on bus

  Within T

  

a

  The wait line is unused d[0:7]

  

2 3 Master receives data

  3 Master deasserts req

  req

  4 Slave ready for next request

  wait data T

  a

  1

  2

  3

  4 Vahid, Givargis Vahid, Givargis

  12 12 - -

  1

  4

  data

  4

  2

  3

  req wait

  5

  5

  2

  5

  1

  Slave asserts wait Slave puts data on bus Slave deasserts wait Master receives data Master deasserts req Slave ready for next request

  a

  master slave req d[0:7] wait Master asserts req to receive data Slave can't put data on bus within T

  Strobe/handshake protocol: Slow

  4

  6 Vahid, Givargis Vahid, Givargis

  3

6 T a

  13 13 - - Strobe/handshake protocol: Slow

  Vahid, Givargis Vahid, Givargis

  14 14 - - I/O Addressing I/O Addressing

  CPU communicates using some of its pins Port-based I/O or parallel I/O CPU has one or more n-bit ports Software reads and writes a port just like a register

  Bus-based I/O CPU has address, data and control ports

  cpu port 0 port 1 port k bus memory

  I/O Addressing I/O Addressing

  Parallel I/O peripheral (PIO) Processor only supports bus-based I/O … But parallel I/O needed Ports are managed by a dedicated peripheral

  port 0 cpu PIO port 1 port k memory bus

  Vahid, Givargis

• 15 15 -
• Vahid, Givargis

  I/O Addressing I/O Addressing

  Extended parallel I/O Processor supports port-based I/O … But more ports needed One or more PIO extending total number of ports

  port 0 port k+1 cpu PIO port 1 port k+2 port k port k+m memory bus

  Vahid, Givargis

• Vahid, Givargis

  16

  16 Memory mapped and Standard I/O Memory mapped and Standard I/O

  Processor uses the same bus to talk to Memory Peripherals

  There are two main ways to communicate Memory-mapped I/O Standard I/O

  Vahid, Givargis

• Vahid, Givargis

  17 - -

  17 Memory mapped I/O Memory mapped I/O

  Peripheral registers occupy addresses in same address space as memory E.g. Bus has 16-bit address Lower 32K map to memory

  Upper 32k map to peripherals Requires no special instructions

  Assembly instructions involving memory work with peripherals as well E.g. MOV, LOAD, STORE, ADD, … Standard I/O requires special instructions to move data between peripheral registers and memory E.g. IN, OUT

  Vahid, Givargis Vahid, Givargis

• 18 - -

  18 Standard I/O Standard I/O

  No loss of memory addresses to peripherals E.g. Bus has 16-bit address All 64K map to memory when M/IO set to 0 all 64K map to peripherals when M/IO set to 1

  Simpler address decoding logic in peripherals When the number of peripherals much smaller than address space, high-order address bits are ignored

  Smaller and/or faster comparators Additional pin on bus indicates whether a memory or peripheral access

M/IO

  Vahid, Givargis 19 - Vahid, Givargis 19 - - -

  Interrupts Interrupts

  Suppose a peripheral intermittently receives data, which must be serviced by the processor Processor can poll the peripheral regularly To see if data has arrived

  Wastes a lot of time Peripheral can interrupt the processor when ready Requires one or more extra pin or pins

  Interrupt pins: INT0, INT1, … If INT is 1

  Processor suspends current program Jumps to an Interrupt Service Routine, or ISR Accomplishes the requested I/O operation

  Vahid, Givargis

• Vahid, Givargis

  20

  20 Interrupts Interrupts

  Different interrupt signals (INT0, INT1, …) have different service routines (ISR0, ISR1, …) What is the address of the correct ISR?

  Fixed interrupt Address built into microprocessor, cannot be changed Either ISR or jump to actual ISR stored at address Vectored interrupt Peripheral must provide the address Common when microprocessor has multiple peripherals connected by a system bus Compromise: interrupt address table

  Vahid, Givargis 21 - Vahid, Givargis 21 - - -

  Fixed ISR location Fixed ISR location

  [1A] CPU is executing its main program [1B] P1 receives input data in a register with address 0x8000

  

[2] P1 asserts INT to request servicing by

the microprocessor

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and sets PC to the ISR fixed location of 16

  [4A] The ISR reads data from 0x8000, [4B] After being read, P1 de-asserts INT modifies the data, and writes the resulting data to 0x8001

  [5] The ISR returns, thus restoring PC to 100+1=101, where CPU resumes executing

• Vahid, Givargis Vahid, Givargis

  22 - 22 - - Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction 101: # instruction 102: # instruction LR=--- 1612

  [1A] CPU is executing its main program [1B] P1 receives input data in a register with address 0x8000

  Vahid, Givargis

• Vahid, Givargis

  23 23 - - Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction PC=100

  101: # instruction 102: # instruction LR=--- 1612

  [2] P1 asserts INT to request servicing by the microprocessor

  Vahid, Givargis Vahid, Givargis

  24 24 - Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and sets PC to the ISR fixed location of 16

  Vahid, Givargis

• Vahid, Givargis

  25 25 - - Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction PC=16

  101: # instruction 102: # instruction LR=100 1612

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and sets PC to the ISR fixed location of 16

• Vahid, Givargis Vahid, Givargis

  26 - 26 - - Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1612

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612

  [4A] The ISR reads data from 0x8000, modifies the data, and writes the

  [4B] After being read, P1 de-asserts INT resulting data to 0x800

  27

  27 - - - - Vahid, Givargis Vahid, Givargis Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction PC=17

  101: # instruction 102: # instruction LR=100 1612

  [4A] The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

  Vahid, Givargis Vahid, Givargis

  28 28 - Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612 1613

  [4A] The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

• 29 29 -
• Vahid, Givargis
• Vahid, Givargis

  Fixed ISR location Fixed ISR location

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction PC=101

  101: # instruction 102: # instruction LR=100 1612 1613

  [5] The ISR returns, thus restoring PC to 100+1=101, where CPU resumes executing

• Vahid, Givargis

  30 - - - Vahid, Givargis

  30

  [5B] After being read, P1 de-asserts INT

  Vahid, Givargis Vahid, Givargis

  [4] P1 detects INTA and puts interrupt

address vector 16 on the data bus

  [6] The ISR returns, thus restoring PC to 100+1=101, deassrts INTA and CPU resumes executing

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and asserts INTA

  

[2] P1 asserts INT to request servicing by

the microprocessor

  [1A] CPU is executing its main program [1B] P1 receives input data in a register with address 0x8000

  32 32 - - Vectored interrupt Vectored interrupt

  [5] The ISR returns, thus restoring PC to 100+1=101, where CPU resumes executing

  R0=1613

  INT Data Memory

  LR=100 P1: 0x8000 P2: 0x8001 1612 1613

  ISR: 16: MOV R0, 0x8000 17: INCR R0 18: MOV 0x8001, R0 19: RETI … MAIN: … 100: # instruction 101: # instruction 102: # instruction CPU

  Program memory

  31 31 - - Fixed ISR location Fixed ISR location

  Vahid, Givargis Vahid, Givargis

  Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

• 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction 101: # instruction 102: # instruction LR=--- 1612

  [1A] CPU is executing its main program [1B] P1 receives input data in a register with address 0x8000

  Vahid, Givargis

• Vahid, Givargis

  33 33 - Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

• 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction PC=100

  16 101: # instruction 102: # instruction

  LR=--- 1612

  [2] P1 asserts INT to request servicing by the microprocessor

  Vahid, Givargis Vahid, Givargis 34 - 34 - - -

  Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

• 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and asserts INTA

  Vahid, Givargis 35 - 35 - - - Vahid, Givargis

  Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction PC=100

  16 101: # instruction 102: # instruction

  LR=100 1612

  [4] P1 detects INTA and puts interrupt address vector 16 on the data bus

  Vahid, Givargis

• Vahid, Givargis

  36 36 - - Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

  Vahid, Givargis 37 - Vahid, Givargis 37 - - -

  Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1612

  … 100: # instruction PC=16

  16 101: # instruction 102: # instruction

  LR=100 1612

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

  Vahid, Givargis

• Vahid, Givargis

  38 38 - - Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

  Vahid, Givargis

  39 - - - - Vahid, Givargis Vectored interrupt Vectored interrupt

  39

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction PC=18

  16 101: # instruction 102: # instruction

  LR=100 1612 1613

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001

  40 - - - - Vahid, Givargis Vahid, Givargis

  40 Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612 1613

  [5B] After being read, P1 de-asserts INT

• Vahid, Givargis Vahid, Givargis

  41

  41 Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction PC=101

  16 101: # instruction 102: # instruction

  LR=100 1612 1613

  [6] The ISR returns, thus restoring PC to 100+1=101, deassrts INTA and CPU resumes executing

  42 - - - - Vahid, Givargis Vahid, Givargis

  42 Vectored interrupt Vectored interrupt

  Program memory CPU Data Memory

  ISR: 16: MOV R0, 0x8000 17: INCR R0

  16 18: MOV 0x8001, R0

  INTA 19: RETI

  INT … MAIN:

  P1: 0x8000 P2: 0x8001 R0=1613

  … 100: # instruction 101: # instruction 102: # instruction LR=100 1612 1613

  [6] The ISR returns, thus restoring PC to 100+1=101, deassrts INTA and CPU resumes executing

• Vahid, Givargis

  43 - Vahid, Givargis Interrupt address table

  43

  Interrupt address table Compromise between fixed and vectored interrupts

  One interrupt pin Table in memory holding ISR addresses

  Maybe 256 words Peripheral doesn’t provide ISR address

  … But rather index into table Fewer bits are sent by the peripheral Can move ISR location without changing peripheral

  Vahid, Givargis

  44 44 - - Additional interrupt issues Additional interrupt issues

• Vahid, Givargis

  Maskable (MI) vs. Non-Maskable (NMI) interrupts Maskable Programmer can set bit that causes processor to ignore interrupt Important when in the middle of time-critical code

  Non-maskable A separate interrupt pin that can’t be masked Typically reserved for drastic situations, like power failure requiring immediate backup of data to non- volatile memory

• Vahid, Givargis

  45 45 - - Vahid, Givargis Additional interrupt issues Additional interrupt issues

  Jump to ISR Some microprocessors treat jump same as call of any subroutine

  Complete state saved (PC, registers) May take hundreds of cycles Others only save partial state

  PC only

  ISR must not modify registers Or else must save them first Assembly-language programmer must be aware of which registers stored

  Vahid, Givargis

• Vahid, Givargis

  46

  46 Direct memory access Direct memory access

  Buffering Temporarily storing data in memory before processing Data accumulated in peripherals commonly buffered

  Microprocessor could handle this with ISR Storing and restoring microprocessor state inefficient Regular program must wait

  DMA (Direct Memory Access) controller is more efficient Vahid, Givargis Vahid, Givargis

  47 47 - - Direct memory access Direct memory access

  Separate single-purpose processor CPU leaves control of system bus to DMA controller CPU can meanwhile execute its regular program No inefficient storing and restoring state due to interrupt service routine call Regular program need not wait unless it requires the system bus For Harvard archictectures Processor can fetch and execute instructions as long as they don’t access data memory If they do, processor stalls

  Vahid, Givargis

• Vahid, Givargis

  48

  48

• 0x0001
• 0x7FFF

  Program memory

  16

  INTA

  R0=---

  [1A] CPU is executing its main program [1B] P1 receives input data in a register with address 0x8000

  INT Data Memory

  P1: 0x8000 P2: 0x8001 1612

  PC=100 LR=---

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0 19: RETI … MAIN: … 100: # instruction 101: # instruction 102: # instruction CPU

  50 50 - - Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Vahid, Givargis Vahid, Givargis

  [5B] After being read, P1 de-asserts INT Vahid, Givargis Vahid, Givargis

  [4] P1 detects INTA and puts interrupt

address vector 16 on the data bus

  [6] The ISR returns, thus restoring PC to 100+1=101, deassrts INTA and CPU resumes executing

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000 and writes it to 0x0001

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and asserts INTA

  

[2] P1 asserts INT to request servicing by

the microprocessor

  [1A] CPU is executing its main program [1B] P1 receives input data in a register with address 0x8000

  Peripheral to memory transfer with vectored interrupt with vectored interrupt

  49 49 - - Peripheral to memory transfer

  0x0000

  Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0

• 19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 … 100: # instruction

  PC=100

  16 101: # instruction 102: # instruction

  LR=--- 1612

  [2] P1 asserts INT to request servicing by the microprocessor

  51 - 51 - - Vahid, Givargis Vahid, Givargis

• Peripheral to memory transfer Peripheral to memory transfer

  with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0

• 19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction PC=100

  16 101: # instruction 102: # instruction

  LR=100 1612

  [3] After completing instruction at 100, CPU sees INT asserted, saves the PC’s value of 100, and asserts INTA

  52

  52 - - - Vahid, Givargis

• Vahid, Givargis

  Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0

  16 19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 … 100: # instruction

  PC=100

  16 101: # instruction 102: # instruction

  LR=100 1612

  [4] P1 detects INTA and puts interrupt address vector 16 on the data bus

• Vahid, Givargis Vahid, Givargis

  53

  53 Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0

  16 19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 R0=---

  … 100: # instruction PC=16

  16 101: # instruction 102: # instruction

  LR=100 1612

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000 and writes it to 0x0001

  Vahid, Givargis 54 - 54 - - - Vahid, Givargis

  Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0

  16 19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 … 100: # instruction

  PC=16

  16 101: # instruction 102: # instruction

  LR=100 1612

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000 and writes it to 0x0001

• Vahid, Givargis Vahid, Givargis

  55

  55 Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU 1612

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0 1612

  19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 R0=1612

  … 100: # instruction PC=17

  16 101: # instruction 102: # instruction

  LR=100 1612

  [5A] CPU jumps to the address on the bus (16). The ISR reads data from 0x8000 and writes it to 0x0001

  Vahid, Givargis

• Vahid, Givargis

  56 56 - Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU 1612 --- ---

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0 1612

  19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 … 100: # instruction

  PC=18

  16 101: # instruction 102: # instruction

  LR=100 1612

  [5B] After being read, P1 de-asserts INT Vahid, Givargis 57 - 57 -

• Vahid, Givargis

  Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  Data Memory 0x0000 0x0000 0x7FFF

  Program memory CPU

• 1612 ---

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0 1612

  19: RETI

  INTA …

  INT MAIN:

  P1: 0x8000 P2: 0x8001 R0=1612

  … 100: # instruction PC=101

  16 101: # instruction 102: # instruction

  LR=100 1612

  [6] The ISR returns, thus restoring PC to 100+1=101, deassrts INTA and CPU resumes executing

  58 - - - Vahid, Givargis

  58

• Vahid, Givargis
• 0x0000

• 0x7FFF

  [7A] CPU deasserts DACK and resumes control of the bus

  0x8000 and writes it to 0x0001 [6] DMA deasserts DREQ and ACK completing handshake with P1

  CPU stalls only if it needs the system bus to continue executing [5] DMA ctrl asserts ACK, reads data from

  [7B] P1 deasserts REQ [3] DMA ctrl asserts DREQ to request [4] control of system bus After executing instruction 100, the CPU sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution.

  [2] P1 asserts REQ to request servicing by DMA ctrl

  [1B] P1 receives input data in a register with address 0x8000.

  [1A] CPU is executing its main program. It has already configured the DMA ctrl registers

  60 60 - - Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Vahid, Givargis Vahid, Givargis

  1612 0x0000

  Data Memory

  16 1612

  [6] The ISR returns, thus restoring PC to 100+1=101, deassrts INTA and CPU resumes executing

  INTA

  INT

  P1: 0x8000 P2: 0x8001 1612

  CPU PC=101 LR=100

  Peripheral to memory transfer Peripheral to memory transfer with vectored interrupt with vectored interrupt

  ISR: 16: MOV R0, 0x8000 18: MOV 0x0001, R0 19: RETI … MAIN: … 100: # instruction 101: # instruction 102: # instruction

  Program memory

  59 59 - -

  Vahid, Givargis Vahid, Givargis

  Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  # # No ISR needed!!

• #

  DACK …

  DREQ MAIN:

  DMA ctrl P1: 0x8000 …

  ACK 100: # instruction

  PC=100 0x8000 101: # instruction REQ 102: # instruction

  LR=--- 0x0001 1612

  [1A] CPU is executing its main program. It [1B] P1 receives input data in a register has already configured the DMA ctrl

with address 0x8000.

registers

• Vahid, Givargis 61 -
• Vahid, Givargis

  61

  Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

  # # No ISR needed!!

• #

  DACK …

  DREQ MAIN:

  DMA ctrl P1: 0x8000 R0=---

  … 100: # instruction ACK

  PC=100 0x8000 101: # instruction REQ 102: # instruction

  LR=--- 0x0001 1612

  [3] DMA ctrl asserts DREQ to request control of system bus [2] P1 asserts REQ to request servicing by DMA ctrl

  Vahid, Givargis

• Vahid, Givargis

  62

  62

• 0x0001
• 0x7FFF

  [4] After executing instruction 100, the CPU sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. CPU stalls only if it needs the system bus to continue executing

  REQ ACK

  0x0000

  DACK 0x8000

  Data Memory R0=---

  0x0001 1612 DREQ

  LR=--- DMA ctrl P1: 0x8000

  CPU PC=101

  Program memory # # No ISR needed!! # … MAIN: … 100: # instruction 101: # instruction 102: # instruction

  64 64 - - Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Vahid, Givargis Vahid, Givargis

  REQ ACK

  [4] After executing instruction 100, the CPU sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. CPU stalls only if it needs the system bus to continue executing

  0x0000

  0x8000

  Data Memory DACK

  0x0001 1612 DREQ

  LR=--- DMA ctrl P1: 0x8000

  CPU PC=100

  Program memory # # No ISR needed!! # … MAIN: … 100: # instruction 101: # instruction 102: # instruction

  Peripheral to memory transfer with DMA with DMA

  63 63 - - Peripheral to memory transfer

  Vahid, Givargis Vahid, Givargis

• 0x0001
• 0x7FFF

  Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

• 1612 ---

  # # No ISR needed!!

• #

  DACK …

  DREQ MAIN:

  DMA ctrl P1: 0x8000 …

  ACK 100: # instruction

  PC=102 0x8000 101: # instruction REQ 102: # instruction

  LR=--- 0x0001 1612

  [4] After executing instruction 100, the CPU sees DREQ asserted, releases the system bus, asserts DACK, and resumes execution. CPU stalls only if [5] DMA ctrl asserts ACK, reads data from it needs the system bus to continue 0x8000 and writes it to 0x0001 executing

  Vahid, Givargis

• Vahid, Givargis

  65 65 - - Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

• 1612 ---

  # # No ISR needed!!

• #

  DACK …

  DREQ MAIN:

  DMA ctrl P1: 0x8000 R0=---

  … 100: # instruction ACK

  PC=102 0x8000 101: # instruction REQ 102: # instruction

  LR=--- 0x0001 1612

  [6] DMA deasserts DREQ and ACK completing handshake with P1 Vahid, Givargis

• Vahid, Givargis

  66 66 - -

  Peripheral to memory transfer Peripheral to memory transfer with DMA with DMA

  Data Memory 0x0000 0x0001 0x7FFF

  Program memory CPU

• 1612 ---

  # # No ISR needed!!

• #

  DACK …

  DREQ MAIN:

  DMA ctrl P1: 0x8000 …

  ACK 100: # instruction

  PC=102 0x8000 101: # instruction REQ 102: # instruction

  LR=--- 0x0001 1612

  [7A] CPU deasserts DACK and resumes control of the bus [7B] P1 deasserts REQ

  Vahid, Givargis Vahid, Givargis 67 - -

• 67 -

  Arbitration Arbitration

  Multiple peripherals may request services from single resource simultaneously Microprocessor, DMA controller, …

  Who is served first? Need an arbiter mechanism

  Different approaches Priority arbiter Daisy-chain arbiter

  Vahid, Givargis

• Vahid, Givargis

  68 68 - -

Arbitration using a priority arbiter Arbitration using a priority arbiter

  Single-purpose processor Peripherals make requests to arbiter Arbiter makes requests to resource

  Arbiter is connected to system bus For configuration purposes only

  CPU Priority Arbiter P1 Pn

  INTA

  INT

  IREQ1

  IACK1

  IREQn

  IACKn

  Vahid, Givargis

• Vahid, Givargis

  69 69 - - Arbitration using a priority arbiter

  Arbitration using a priority arbiter

  CPU

  7

  5 Priority Arbiter P1 Pn

  INTA

  4

  3 INT

  2 IREQ1

  6 IACK1

  2

  1

  9

  program

8 ISR

  IREQn

  IACKn

  1. Microprocessor is executing its program

  2. Peripheral P1 needs servicing so asserts IREQ1; peripheral Pn also needs servicing so asserts IREQn

  3. Priority arbiter sees at least one IREQ input asserted, so asserts INT

  4. Microprocessor stops executing its program and stores its state

  5. Microprocessor asserts INTA

  6. Priority arbiter asserts IACK1 to acknowledge peripheral P1

  7. Peripheral P1 puts its interrupt address vector on the system bus

  8. Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns and completes handshake with arbiter

  9. Microprocessor resumes executing its program Vahid, Givargis Vahid, Givargis

  70 70 - - Arbitration using a priority arbiter Arbitration using a priority arbiter