Materi Kuliah ke-9 FLIP- FLOPS Continue

  

TEKNI K DI GI TAL (A)

TEKNI K DI GI TAL (A)

  

(TI 2104)

(TI 2104)

• - M a teri M a teri Kuliah Kuliah ke ke

  9 9 - - - FLIP FLIP FLOPS Continue FLOPS Continue

Flip- Flops

• Last t ime, we saw how lat ches can be used as memor y in a cir cuit .

• Lat ches int r oduce new pr oblems: – We need t o know when t o enable a lat ch.
• – We also need t o quickly disable a lat ch.
• – I n ot her wor ds, it ’s dif f icult t o cont r ol t he t iming of lat ches in a lar ge cir cuit .
• We solve t hese pr oblems wit h t wo new element s: clocks and f lip-f lops
• – Clocks t ell us when t o wr it e t o our memor y.
• – Flip-f lops allow us t o quickly wr it e t he memor y at clear ly def ined t imes.
• – Used t oget her , we can cr eat e cir cuit s wit hout wor r ying about t he memor y t iming.

An SR lat ch wit h a cont rol input • Her e is an SR lat ch wit h a cont r ol input C

  C S R S’ R’ Q x x

  1

  1 No change

  1

  1

  1 No change

  1

  1 1 0 (r eset )

  1

  1 1 1 (set )

  1

  1

  1 Avoid!

• Not ice t he hier ar chical design! – The dot t ed blue box is t he S’R’ lat ch.
• – The addit ional NAND gat es ar e simply used t o gener at e t he cor r ect input s f or t he S’R’ lat ch.
• The cont r ol input act s j ust like an enable.

  

Flip- f l ops

  3 D lat ch

• Finally, a D lat ch is based on an S’R’ lat ch. The addit ional gat es gener at e t he S’ and R’ signals, based on input s D (“dat a”) and C (“cont r ol”).
• – When C = 0, S’ and R’ ar e bot h 1, so t he st at e Q does not change.
• – When C = 1, t he lat ch out put Q will equal t he input D.
• No mor e messing wit h one input f or set and anot her input f or r eset !

  C D Q x No change

  1

  1

  1

  1

• Also, t his lat ch has no “bad” input combinat ions t o avoid. Any of t he f our possible assignment s t o C and D ar e valid.
• 1

• Let ’s say t hese lat ches cont ain some value t hat we want t o incr ement .
• – The incr ement ed value is st or ed back int o t he lat ches.
• At t his point , we have t o st op t he cycle, so t he lat ch value doesn’t get incr ement ed again by accident .
• One convenient way t o br eak t he loop is t o disable t he lat ches.

• – The ALU should r ead t he cur r ent lat ch value.
• – I t applies t he “G = X + 1” oper at ion.

  

Flip- f l ops

  5 Using lat ches in real lif e • We can connect some lat ches, act ing as memor y, t o an ALU.

  ALU S

  X G Lat ches

  D Q C

  

The problem wit h lat ches

• 1

• The pr oblem is exact ly when t o disable t he lat ches. You have t o wait long enough f or t he ALU t o pr oduce it s out put , but no longer .
• – But dif f er ent ALU oper at ions have dif f er ent delays. For inst ance,
• – Changing t he ALU implement at ion, such as using a car r y-lookahead adder inst ead of a r ipple-car r y adder , also af f ect s t he delay.
• I n gener al, it ’s ver y dif f icult t o know how long oper at ions t ake, and how long lat ches should be enabled f or .
• – Let ’s say t her e ar e f our lat ches init ially st or ing 0000.
• – We want t o use an ALU t o incr ement t hat value t o 0001.

  ar it hmet ic oper at ions might go t hr ough an adder , wher eas logical oper at ions don’t .

  ALU S

  X G Lat ches

  D Q C

• Nor mally t he lat ches should be disabled, t o pr event unwant ed dat a f r om being accident ally st or ed.
• – I n our example, t he ALU can r ead t he cur r ent lat ch cont ent s, 0000, and comput e t heir incr ement , 0001.
• – But t he new value cannot be st or ed back while t he lat ch is disabled.
• 1

• Af t er t he ALU has f inished it s incr ement oper at ion, t he lat ch can be enabled, and t he updat ed value is st or ed.
• The lat ch must be quickly disabled again, bef or e t he ALU has a chance t o r ead t he new value 0001 and pr oduce a new r esult 0010.
• 1
• 1

  D Q C 0001

  X G Lat ches

  ALU S

  0001

  1 0001

  D Q C

  X G Lat ches

  ALU S

  

W rit ing t o t he lat ches

  0001

  D Q C 0000

  X G Lat ches

  ALU S

  7 Making lat ches work right • Our example used lat ches as memor y f or an ALU.

  

Flip- f l ops

  0010

  

Two main issues

• So t o use lat ches cor r ect ly wit hin a cir cuit , we have t o:
• – Keep t he lat ches disabled unt il new values ar e r eady t o be st or ed.
• – Enable t he lat ches j ust long enough f or t he updat e t o occur .
• Ther e ar e t wo main issues we need t o addr ess:

  4 How do we know exact ly when t he new values ar e r eady? We’ll add anot her signal t o our cir cuit . When t his new signal becomes 1, t he lat ches will know t hat t he ALU comput at ion has complet ed and dat a is r eady t o be st or ed.

  4 How can we enable and t hen quickly disable t he lat ches? This can be done by combining lat ches t oget her in a special way, t o f or m what ar e called f lip-f lops.

  

Flip- f l ops

  9 Clocks and synchronizat ion

• A clock is a special device t hat whose out put cont inuously alt er nat es bet ween 0 and 1.

  clock per iod

• The t ime it t akes t he clock t o change f r om 1 t o 0 and back t o 1 is called t he clock per iod, or clock cycle t ime.
• The clock f r equency is t he inver se of t he clock per iod. The unit of measur ement f or f r equency is t he her t z.
• Clocks ar e of t en used t o synchr onize cir cuit s.
• – They gener at e a r epeat ing, pr edict able pat t er n of 0s and 1s t hat can t r igger cer t ain event s in a cir cuit , such as wr it ing t o a lat ch.
• – I f sever al cir cuit s shar e a common clock signal, t hey can coor di nat e t heir act ions wit h r espect t o one anot her .
• This is similar t o how humans use r eal clocks f or synchr onizat ion.

  

More about clocks

• Clocks ar e used ext ensively in comput er ar chit ect ur e.

• All pr ocessor s r un wit h an int er nal clock.
• – Moder n chips r un at f r equencies up t o 3.2 GHz.
• – This wor ks out t o a cycle t ime as lit t le as 0.31 ns!
• Memor y modules ar e of t en r at ed by t heir clock speeds t oo—examples include “PC133” and “DDR400” memor y.
• Be car ef ul...higher f r equencies do not always mean f ast er machines!
• – You also have t o consider how much wor k is act ually being done dur ing each clock cycle.
• – How much st uf f can r eally get done in j ust 0.31 ns? – Take CS232.

  

Flip- f l ops

  11 Synchronizing our example • We can use a clock t o synchr onize our lat ches wit h t he ALU.

• – The clock signal is connect ed t o t he lat ch cont r ol input C.
• – The clock cont r ols t he lat ches. When it becomes 1, t he lat ches will be enabled f or wr it ing.
• 1 S ALU G

  X D Q Lat ches

  C

• The clock per iod must be set appr opr iat ely f or t he ALU.
• – I t should not be t oo shor t . Ot her wise, t he lat ches will st ar t writ ing bef or e t he ALU oper at ion has f inished.
• – I t should not be t oo long eit her . Ot her wise, t he ALU might pr oduce a new r esult t hat will accident ally get st or ed, as we saw bef or e.
• The f ast er t he ALU r uns, t he shor t er t he clock per iod can be.

  

Flip- f lops

• The second issue was how t o enable a lat ch f or j ust an inst ant .

• Her e is t he int er nal st r uct ur e of a D f lip-f lop.
• – The f lip-f lop input s ar e C and D, and t he out put s ar e Q and Q’.
• – The D lat ch on t he lef t is t he mast er , while t he SR lat ch on t he r ight is called t he slave.
• Not e t he layout her e.
• – The f lip-f lop input D is connect ed dir ect ly t o t he mast er lat ch.
• – The mast er lat ch out put goes t o t he slave.
• – The f lip-f lop out put s come dir ect ly f r om t he slave lat ch.

  

Flip- f l ops

  13 D f lip- f lops when C=0

• The D f lip-f lop’s cont r ol input C enables eit her t he D lat ch or t he SR lat ch, but not bot h.
• When C = 0: – The mast er lat ch is enabled, and it monit or s t he f lip-f lop input D.

  Whenever D changes, t he mast er ’s out put changes t oo.

• – The slave is disabled, so t he D lat ch out put has no ef f ect on it .

  Thus, t he slave j ust maint ains t he f lip-f lop’s cur r ent st at e.

  

D f lip- f lops when C=1

• As soon as C becomes 1,
• – The mast er is disabled. I t s out put will be t he last D input value seen j ust bef or e C became 1.
• – Any subsequent changes t o t he D input while C = 1 have no ef f ect on t he mast er lat ch, which is now disabled.
• – The slave lat ch is enabled. I t s st at e changes t o r ef lect t he mast er ’s out put , which again is t he D input value f r om r ight when C became 1.

  

Flip- f l ops

  15 Posit ive edge t riggering • This is called a posit ive edge-t r igger ed f li p-f lop.

• – The f lip-f lop out put Q changes only af t er t he posit ive edge of C.
• – The change is based on t he f lip-f lop input values t hat wer e pr esent r ight at t he posit ive edge of t he clock signal.
• The D f lip-f lop’s behavior is similar t o t hat of a D lat ch except f or t he posit ive edge-t r igger ed nat ur e, which is not explicit in t his t able.

  C D Q x No change 1 0 (r eset )

  1 1 1 (set )

• One last t hing t o wor r y about … what is t he st ar t ing value of Q?
• We could set t he init ial value synchr onously, at t he next posit ive clock edge, but t his act ually makes cir cuit design mor e dif f icult .
• I nst ead, most f lip-f lops pr ovide dir ect , or asynchr onous, input s t hat let you immediat ely set or clear t he st at e.
• – You would “r eset ” t he cir cuit once, t o init ialize t he f lip-f lops.
• – The cir cuit would t hen begin it s r egular , synchr onous oper at ion.
• Her e is a LogicWor ks D f lip-f lop wit h act ive-low dir ect input s.

  Dir ect input s t o set or r eset t he f lip-f lop S’R’ = 11 f or “nor mal” oper at ion of t he D f lip-f lop • We can use t he f lip-f lops’ dir ect input s t o init ialize t hem t o 0000.

  0001 C Q G C Q G

  D Q C 0000

  X G Flip-f lops

  ALU S

  D Q C 0000

  X G Flip-f lops

  ALU S

  1 1 1 (set )

  1

  1

  1

1 0 (r eset )

  1

  1 1 x No change

  S ’ R’ C D Q

x x Avoid!

1 x x 1 (set ) 1 x x 0 (r eset )

  17 Direct input s

  

Flip- f l ops

Our example wit h f lip- f lops

• 1
• Dur ing t he clock cycle, t he ALU out put s 0001, but t his does not af f ect t he f lip-f lops yet .
• 1

  

Example cont inued

• The ALU out put is copied int o t he f lip-f lops at t he next posit ive edge of t he clock signal.
• 1 S

  C ALU G

  X 0001 0001 Q

  D Q Flip-f lops

  G C

• The f lip-f lops aut omat ically “shut of f ,” and no new dat a can be wr it t en

  unt il t he next posit ive clock edge... even t hough t he ALU pr oduces a new out put .

• 1 S

  C ALU G

  X 0010 0001 Q

  D Q Flip-f lops

  G C

  

Flip- f l ops

  19 Flip- f lop variat ions

• We can make dif f er ent ver sions of f lip-f lops based on t he D f lip-f lop, j ust like we made dif f er ent lat ches based on t he S’R’ lat ch.
• A J K f lip-f lop has input s t hat act like S and R, but t he input s J K=11 ar e used t o complement t he f lip-f lop’s cur r ent st at e.

  next

  C J K Q x x No change

  1 No change

  1 1 0 (r eset )

  1 1 1 (set )

  cur r ent

  1

  1

  1 Q’ • A T f lip-f lop can only maint ain or complement it s cur r ent st at e.

  next C T Q x No change

  

1

  1 Q ’ cur r ent

  

Charact erist ic t ables

• The t ables t hat we’ve made so f ar ar e

  D Q(t +1) Oper at ion called char act er ist ic t ables.

  Reset

• – They show t he next st at e Q (t +1)

  1

  1 Set in t er ms of t he cur r ent st at e Q (t ) and t he input s.

• – For simplicit y, t he cont r ol input C is not usually list ed.

  J K Q (t +1) Oper at ion

• – Again, t hese t ables don’t indicat e

  Q(t ) No change t he posit ive edge-t r igger ed

  1 Reset behavior of t he f lip-f lops t hat

  1

  1 Set we’ll be using.

  1

  1 Q’(t ) Complement

  T Q (t +1) Oper at ion Q(t ) No change

  1 Q ’(t ) Complement Flip- f l ops 2 1

  

Charact erist ic equat ions

• We can also wr it e char act er ist ic equat ions, wher e t he next st at e Q(t +1) is def ined in t er ms of t he cur r ent st at e Q(t ) and input s.

  D Q(t +1) Oper at ion Reset Q (t +1) = D

  1

  1 Set J K Q (t +1) Oper at ion

  Q(t ) No change

  1 Reset Q (t +1) = K’Q (t ) + J Q ’(t )

  1

  1 Set

  1

  1 Q’(t ) Complement

  T Q (t +1) Oper at ion

  Q (t +1) = T’Q (t ) + TQ ’(t )

  Q(t ) No change

  = T Q (t )

  ⊕

  

Flip f lop t iming diagrams

• “Pr esent st at e” and “next st at e” ar e r elat ive t er ms.

• I n t he example J K f lip-f lop t iming diagr am on t he lef t , you can see t hat at t he f ir st posit ive clock edge, J =1, K=1 and Q(1) = 1.
• We can use t his inf or mat ion t o f ind t he “next ” st at e, Q(2) = Q(1)’.
• Q(2) appear s r ight af t er t he f ir st posit ive clock edge, as shown on t he r ight . I t will not change again unt il af t er t he second clock edge.

  1

  2

  3

  4

  1

  2

  3

  4 C C J J K K Q Q …det er mine t he “next ” Q These values at clock cycle 1...

  Flip- f l ops 2 3

“Present ” and “next ” are relat ive

• Similar ly, t he values of J , K and Q at t he second posit ive clock edge can be used t o f ind t he value of Q dur ing t he t hir d clock cycle.
• When we do t his, Q(2) is now r ef er r ed t o as t he “pr esent ” st at e, and Q(3) is now t he “next ” st at e.

  1

  2

  3

  4

  1

  2

  3

  4 C C J J K K Q Q

  

Posit ive edge t riggered

• One f inal point t o r epeat : t he f lip-f lop out put s ar e af f ect ed only by t he input values at t he posit ive edge.
• – I n t he diagr am below, K changes r apidly bet ween t he second and t hir d posit ive edges.
• – But it ’s only t he input values at t he t hir d clock edge (K=1, and J =0 and Q=1) t hat af f ect t he next st at e, so her e Q changes t o 0.
• This is a f air ly simple t iming model. I n r eal lif e t her e ar e “set up t imes”

  and “hold t imes” t o wor r y about as well, t o account f or int er nal and ext er nal delays.

  1

  2

  3

  4 C J K Q

  Flip- f l ops 2 5

Summary

• To use memor y in a lar ger cir cuit , we need t o: – Keep t he lat ches disabled unt il new values ar e r eady t o be st or ed.
• – Enable t he lat ches j ust long enough f or t he updat e t o occur .
• A clock signal is used t o synchr onize cir cuit s. The cycle t ime r ef lect s how long combinat ional oper at ions t ake.
• Flip-f lops f ur t her r est r ict t he memor y wr it ing int er val, t o j ust t he posit ive edge of t he clock signal.
• – This ensur es t hat memor y is updat ed only once per clock cycle.
• – Ther e ar e sever al dif f er ent kinds of f lip-f lops, but t hey all ser ve t he same basic pur pose of st or ing bit s.
• Next week we’ll t alk about how t o analyze and design sequent ial cir cuit s t hat use f lip-f lops as memor y.