Hypothetical machine support for the display model
16.2.6 Hypothetical machine support for the display model
Besides the mark stack register MP , our machine is assumed to have a set of display registers, which we can model in an interpreter as a small array, display . Conceptually this is indexed from 1, which calls for care in a C ++ implementation where arrays are indexed from 0. The MST instruction provides support for procedure activation as before, but the ADR , CAL and RET instructions are subtly different: ADR L A Push a run-time address onto the stack for a variable that was declared at static level L and predicted to be stored at an offset A from the base of a stack frame. CAL L A Call and enter a procedure whose ProcIdentifier was declared at static level L , and whose code commences at address A . RET L Return from a procedure whose Block was compiled at level L . The extensions to the interpreter of section 4.4 show the detailed operational semantics of these instructions: case STKMC_adr: push run time address cpu.sp--; decrement stack pointer if inboundscpu.sp { mem[cpu.sp] = display[mem[cpu.pc] - 1] extract display element + mem[cpu.pc + 1]; and then add offset cpu.pc += 2; } bump program count break; case STKMC_cal: procedure entry mem[cpu.mp - 1] = display[mem[cpu.pc]]; save display element mem[cpu.mp - 2] = cpu.bp; save dynamic link mem[cpu.mp - 3] = cpu.pc + 2; save return address display[mem[cpu.pc]] = cpu.mp; update display cpu.bp = cpu.mp; reset base pointer cpu.pc = mem[cpu.pc + 1]; enter procedure break; case STKMC_ret: procedure exit display[mem[cpu.pc] - 1] = mem[cpu.bp - 1]; restore display cpu.sp = cpu.bp; discard stack frame cpu.pc = mem[cpu.bp - 3]; get return address cpu.bp = mem[cpu.bp - 2]; reset base pointer break;16.2.7 Code generation for the display model
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» Code generation for the display model
» Relative merits of the static link and display models
» Syntax and semantics compilers and compiler generators 1996
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