10.0 = 0.7 1 Nano open house Paolo Gargini

I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 13 60X Transistor Cost Drop from 350nm to 90nm Node Source: Intel ‘03 60X Transistor Cost Drop from 350nm to 60X Transistor Cost Drop from 350nm to 90nm Node 90nm Node Source: Intel Source: Intel ‘ ‘ 03 03 CostTransistor Normalized to 130nm Node CostTransistor Normalized to 130nm Node CostTransistor Normalized to 130nm Node 2003 2001 1999 1997 1995 0.1

1.0 10.0

100.0 350nm 250nm 180nm 130nm 90nm Technology NodeIntroduction Year N o rmalized Cos tTransistor Cost per Total Trans 25 SavingsYear 35 SavingsYear 40 SavingsYear Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 14 The Era of Geometrical Scaling I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 15 With respect to the factor contributed by Device and Circuit Cleverness, however, the situation is different. We are approaching a limit that must slow the rate of progress I see no reason to expect the rate of progress In the use of smaller dimensions in complex Circuits to decrease in the near future. Gordon Moore, IEDM 1975 The new slope might approximate a doubling Every two years……. I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 16 Moore Moore ’ ’ s Law and Scaling Laws s Law and Scaling Laws Convergence Convergence 50 AREA READUCION GENERATION TO GENERATION 50 = 30 LINEAR FEATURE REDUCTION

0.5 = 0.7

Year 0=1X Year 1 Year 2=2X I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 17 Worldwide Transistor Production 1000000 10000000 1E+08 1E+09 1E+10 1E+11 1E+12 1E+13 1E+14 1E+15 1E+16 1E+17 1E+18 1955 1957 1959 1961 1963 1965 1967 1969 1971 1973 1975 1977 1979 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 Units RESTRICTED DATA: for access and use only within your company, as per your companys agreement with VLSI Research Inc. Copyright © 2003 by VLSI Research Inc. Theres no slowing of Moores Law here [ Transistors ] Source: VLSI Research ~55 CAGR I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 18 Average Transistor Price by Year Average Transistor Price by Year Nearly 7 Orders Of Magnitude Reduction in PriceTransistor Nearly 7 Orders Of Magnitude Reduction in PriceTransistor 0.0000001 0.000001 0.00001 0.0001 0.001 0.01

0.1 1

10 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 100 Nanodollars per transistor Source: WSTSDataquestIntel, 304 Source: WSTSDataquestIntel, 304 I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 19 Transistor Trade-offs F Max = I DSat V DD C ox I DSat ~1 µ C ox WV DD –V T 2 2 Lg Power= V DD 2 C ox F Max S D G Lg W Increase Cox =Reduce t ox Reduce Lg Reduce V DD ε o ε s t ox t ox I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 20 Gate Oxide Scaling Gate Oxide Scaling 1 10 1990 1995 2000 2005 Gate Oxide Thickness nm 1 10 1.2 nm 90nm .13um .18um .25um .35um Generation I DSat 1 µ V DD –V T 2 2 Lg W ε o ε s 1 t ox ~ Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 21 Transistor Performance Transistor Performance 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1990 1995 2000 2005 Drive Current mAum 1 10 Supply Voltage V NMOS PMOS 1.2V 90nm .13um .18um .25um .35um Generation I DSat 1 µ V DD –V T 2 2 Lg W ε o ε s 1 t ox ~ Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 22 Gate Delay Trend 100nm F Max = I DSat V DD C ox Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 23 0.35 0.35 Μ Μ Gate Gate Salicide Salicide Spacer Spacer Salicide Salicide The Incredible Shrinking The Incredible Shrinking Silicon Technology in the 90s Silicon Technology in the 90s µ µ 0.25 0.25 Salicide Gate Gate Spacer Spacer Salicide 0.18 0.18 µ µ Gate Gate Spacer Spacer Salicide Salicide 1995 1997 1999 Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 24 Process Name Px60 P1262 P1264 P1266 P1268 Lithography 130nm 90nm 65nm 45nm 32nm Gate Length 70nm 50nm 35nm 25nm 18nm Wafer mm 200300 300 300 300 300 1 st Production 2001 2003 2005 2007 2009 Intels Logic Technology Intels Logic Technology Evolution Continues Evolution Continues Moores Law continues Intel continues to introduce a new technology generation every 2 years M.Bohr I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 25 50nm 50nm 100nm 100nm Transistor for Transistor for 90nm 90nm - - node node Gate oxide=1.2nm Gate oxide=1.2nm Source: Intel Source: Intel Influenza virus Influenza virus Source: CDC Source: CDC Nanotechnology Today Example of today’s technology: 50 nm transistor dimension Intel Intel 2003 Silicon Nanotech Product Revenue 20B Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 26 50nm 50nm But is this really Nanotechnology or more of the same ? I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 27 CMOS Future Directions CMOS Future Directions ??2-3year New Devices 2010-20XX 2X Performance2-3year Integrated Solutions 2000-2014 702-3year 70 2-3year Equivalent Scaling 2005-2014 1970-2004 Traditional Scaling Features Source: ITRS 7111998 From My Files I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 28 The Era of Equivalent Scaling And Much More I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 29 The Ideal MOS Transistor The Ideal MOS Transistor Fully Surrounding Metal Electrode High-K Gate Insulator Fully Enclosed, Depleted Semiconductor Band Engineered Semiconductor Low Resistance SourceDrain Drain Source Metal Gate Insulator I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 30 New Transistor Trade-off I DSat ~1 µ C ox WV DD –V T 2 2 Lg S D G Lg W Increase Cox Reduce Lg µ Increase µ ε o κ s t ox New Material I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 31 R R ® ® Gate Dielectric Scaling Gate Dielectric Scaling 1 2 3 Tox equivalent nm 4 8 12 Monolayers 4 1999 2001 2003 2005 1997 NTRS P.Gargini From My Files I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 32 Gate Oxide Scaling Gate Oxide Scaling 1 10 1990 1995 2000 2005 Gate Oxide Thickness nm 1 10 1.2 nm Thinner gate oxide increases transistor performance Thinner gate oxide increases transistor performance 90nm .13um .18um .25um .35um Generation Silicon substrate 1.2nm SiO 2 Gate Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 33 The Next Step Towards Equivalent The Next Step Towards Equivalent Scaling: High Scaling: High - - k Dielectric k Dielectric Silicon substrate Gate 3.0nm High-k Silicon substrate 1.2nm SiO 2 Gate November 4 th , 2003 High-k 1.6x 0.01x 90nm process 1.0x 1.0x Capacitance: Leakage: Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 34 Gate Dielectric Scaling High Gate Dielectric Scaling High - - K K 1 10 1990 1995 2000 2005 Gate Dielectric Thickness nm 1 10 1.2 nm Thinner equivalent gate oxide increases transistor performance Thinner equivalent gate oxide increases transistor performance 90nm .13um .18um .25um .35um Generation 2010 K= 3X K D K= 5X K D Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 35 Equivalent Scaling plus Innovation I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 36 Transistor Strain Transistor Strain Techniques Techniques D G S S D G Tensile Si 3 N 4 Cap S D G Selective SiGe S-D Graded SiGe Layer Biaxial Tensile Strain Uniaxial Compressive Strain for PMOS Uniaxial Tensile Strain for NMOS Traditional Approach Intels 90nm Technology Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 37 Strained Silicon Transistors Strained Silicon Transistors Normal Silicon Lattice Strained Silicon Lattice Current Flow Normal electron flow Faster electron flow Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 38 Mobility Innovation Mobility Innovation SiGe SiGe Strained Strained P P - - Channel Channel Transistor Transistor High Stress Film Strained Strained N N - - Channel Channel Transistor Transistor Source: Intel I n t e l N a n ot e ch nology Vir t u a l Ope n H ou se 39 40 60 80 100 120 140

0.2 0.4