Index of /intel-research/silicon
2/5/2003 Intel Corp. George Bourianoff 1
The future of nano-computing
George Bourianoff
Intel Corporation
Presented to
International Engineering Consortium and
Electrical and Computer Engineering Department
Heads
(2)
Future of Nanocomputing
Silicon highway
Scalable new
technology
Scalable new
technology
origins
characteristics
limits
criteria
criteria
taxonomy
elements
(3)
2/5/2003 Intel Corp. George Bourianoff 3
Key messages
• CMOS scaling will continue for next 12 –15
years
• Alternative new technologies will emerge
and begin to be integrated on CMOS by
2015
• Nanoscience research is needed to facilitate
radical new scalable technologies beyond
2020
(4)
The future of nanocomputing
• Introduction
• Scaled CMOS
• Nano-computing, nano-technology and
nano-science
• Radical new technologies
• Challenges
(5)
2/5/2003 Intel Corp. George Bourianoff 5
The foundations of microelectronics
Central Breakthroughs:
•Band structure concept
•Minute amounts of impurities
control properties
•Advances in purification and
high quality crystal growth of Si
and Ge
Most basic semiconductor
devices were demonstrated
within 12 years
Beginning about 1946, we
began to utilize this
knowledge base
Government funded
research in solid state
physics in 1930’s and 40’s
laid the foundation
Bipolar transistor
1948
Field effect transistor
1953
LED
1955
Tunnel diode
1957
IC
1959
(6)
The beauty of silicon
1 GB
64 MB
4 MB
DRAMs
Cost per
Megabit
12”
8”
6”
Wafer diameter
0.15 µm
0.35 µm
0.8 µm
Feature size
2000
1995
1990
1. Scaling device
dimensions
downward
For four decades, the semiconductor
industry has steadily reduced the
unit cost of IC components by
$6.50
$3.14
$0.10
2. Scaling wafer
diameter
(7)
2/5/2003 Intel Corp. George Bourianoff 7 2008 70 nm 2011 50 nm 2014 35 nm
6.00 10.00 13.50 9 9-10 10 3 4 4 2.1 E6 3.7 E6 4.6 E6
140 100 70 165 120 85
1.9 2.1 2.2 - 2.3 9 7 5 210 145 110 2.5/2.3 2.7/2.4 2.9/2.5
30 22 17 0 0 0 330 240 170 2.8/2.9 2.9/3.0 3.0/3.1
55 38 20 14.1 16.1 23.1
1.8 < 1.8 < 1.8 0 0 0 1.4 <1.5 <1.5
Brick Walls on the ITRS
YEAR TECHNOLOGY NODE 1999 180 nm 2002 130 nm 2005 100 nmOn-chip local frequency (MHz) 1.25 2.10 3.50
Number of metal levels - Logic 6-7 7-8 8-9
Number of optional levels 0 2 2
Jmax (A/cm2) - wire (at 105oC) 5.8 E5 9.6 E5 1.4 E6
Local wiring pitch - DRAM non-contacted (nm) 360 260 200
Local wiring pitch - Logic (nm) 500 325 230
Local wiring AR-Logic (Cu) 1.4 1.5 1.7
Cu local dishing (nm) 18 14 11
Intermediate wiring pitch - Logic (nm) 560 405 285
Intermediate wiring h/w AR - Logic (Cu DD via/lin) 2.0/2.1 2.2/2.1 2.4/2.2
Cu intermediate wiring dishing -
15 um wide wire (nm) 64 51 41
Dielectric erosion, intermediate wiring
50% density (nm) 64 51 41
Global wiring pitch - Logic (nm) 900 650 460
Global wiring h/w AR - Logic - Cu DD via/line (nm) 2.2/2.4 2.5/2.7 2.7/2.8
Cu global wiring dishing, 15 um wide wire (nm) 116 95 76
Contact aspect ratio - DRAM, stacked cap 9.3 11.4 13
Conductor effective resistivity (uohm -cm) 2.2 2.2 2.2
Barrier/cladding thickness (nm) 17 13 10
Interlevel metal insulator effective
dielectric constant (k) - Logic 4.0 - 3.5 3.5 - 2.7 2.2 - 1.6
Solutions Exist
Solutions being pursued No known solutions
2008 70 nm 2011 50 nm 2014 35 nm
6.00 10.00 13.50 9 9-10 10 3 4 4 2.1 E6 3.7 E6 4.6 E6
140 100 70 165 120 85
1.9 2.1 2.2 - 2.3 9 7 5 210 145 110 2.5/2.3 2.7/2.4 2.9/2.5
30 22 17 0 0 0 330 240 170 2.8/2.9 2.9/3.0 3.0/3.1
55 38 20 14.1 16.1 23.1
1.8 < 1.8 < 1.8 0 0 0 1.4 <1.5 <1.5
(8)
Silicon Nanotechnology is Here!
10000
10000
1000
1000
100
100
10
10
10
10
1
1
0.1
0.1
0.01
0.01
Micron
Micron
Nano
Nano
meter
meter
-
-1970
1980
1990
2000
2010
2020
1970
1980
1990
2000
2010
2020
Nominal feature size
Nominal feature size
Nanotechnology
Nanotechnology
130nm
130nm
90nm
90nm
70nm
70nm
50nm
50nm
Gate Width
Gate Width
(9)
2/5/2003 Intel Corp. George Bourianoff 9
The ingredients of scaling
Material Evolution in MOS
Material Evolution in MOS
2000’s 60’s 70’s 80’s 90’s Al SiO2 Al-Si SiO2 Poly Al-Cu SiO2 WSi2/Poly Ti/TiN Al-Cu SiO2 TiSi2/Poly Ti/TiN W Al-Cu SiO2 TiSi2/Poly Ti/TiN W Low K Al-Cu SiO2/SiN
CSi2/Poly
Ti/TiN W
ELK
Cu
Silicon Silicon Silicon Silicon Silicon Silicon
New materials
Improved processing
New geometries
Scaling Will continue as long as
(10)
Transistor Scaling
70nm transistor
for 0.13µm process
2001 production
70nm
30nm transistor
Prototype
30nm
Demo: 2000
15nm
15nm transistor
prototype
Source:
Intel (IEDM, Dec 2001)
0
100
200
300
400
500
0
0.2 0.4 0.6 0.8
Drain Voltage (V)
Drain Current (µA/µm)
Vg = 0.8V 0.7V 0.6V 0.5V 0.4V 0.3V
15nm NMOS
100nm
100nm
Influenza virus
Source: CDC
(11)
2/5/2003 Intel Corp. George Bourianoff 11
New Materials
Gate
Gate
Silicide
Silicide
added
added
Channel
Channel
Strained
Strained
silicon
silicon
Changes
Changes
Made
Made
Future
Future
Options
Options
High
High
-
-
k
k
gate
gate
dielectric
dielectric
New
New
transistor
transistor
structure
structure
Transistor
Transistor
Source: Intel
The problem: High Ioff current
The problem: High
(12)
New Geometries
Source
Source
Drain
Drain
Gate
Gate
Gate
Gate
Silicon
Silicon
Drain
Drain
Source
Source
Id
(
Id (
mAmA
/µm)/µm)
0.2
0.2
0.4
0.4
0.6
0.6
0.8
0.8
1.0
1.0
1.2
1.2
Source: Intel
Source: Intel
(ISSDM, Sep 2002)
(13)
2/5/2003 Intel Corp. George Bourianoff 13
Improved processing
EUV
EUV
Lithography
Lithography
Prototype Exposure Tool
Prototype Exposure Tool
50nm Lines Printed
50nm Lines Printed
with EUV Lithography
with EUV Lithography
EUV lithography in commercialization phase
Cost effectiveness is key challenge
EUV lithography in commercialization phase
Cost effectiveness is key challenge
Source:
(14)
The limits of logic scaling
• For an
arbitrary
switching device made of
of a single electron in a dual quantum well
– Operating at room temperature
• It can be shown a power dissipation limit of
100 W/cm**2
• Will limit the operational frequency to ~100
GHz at length scales ~ 4 nm
(15)
2/5/2003 Intel Corp. George Bourianoff 15
CMOS device circa 2016
•
Cost
10
-11
$/gate
•
Size
8 nm / device
•
Speed
0.2 ps /operation
(16)
The future of nanocomputing
– Introduction
– Scaled CMOS
–
Nano-computing, nano-technology and nano-science
•
A taxonomy
• New devices
• New architectures
• Alternative state variables
– Radical new technologies
– Challenges
(17)
2/5/2003 Intel Corp. George Bourianoff 17
Architecture
Devices
State
variables
Data
represent
ations
A taxonomy for nano-computing
CNT FETs Molecular Spintronics Quantum CNN Crossbar Quantum Boolean Molecular state Spin orientation
Flux quanta Quantum state Electric charge associative patterns analogue Digital Scaled CMOS probabilities
Heir-archy
bi
ot
ec
h
Mem
ory d
evice
s
sensors
(18)
The future of nanocomputing
– Introduction
– Scaled CMOS
–
Nano-computing, nano-technology and nano-science
• A taxonomy
•
New devices
• New architectures
• Alternative state variables
– Radical new technologies
– Challenges
(19)
(20)
CNT-FET Device Structure
E-beam Ti/Au gate
Mo S/D
8 nm
ZrO2
1.4 nm diameter single wall CNT
(21)
2/5/2003 Intel Corp. George Bourianoff 21
Nanowire Gating Geometries
S D
G
SiO2 Si
Back gate
S D
G
Top gate
S D
G
Coaxial gate
(22)
Top-gated p-Si Nanowire
Transistors
S D G 1500 1000 500 0 -I DS (n A )-2 -1 0 1 20.01 0.1 1 10 100 1000 -I DS (n A ) 700 nA/V 250 mV/dec
VDS= -1 V
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 I DS ( µ A)
-4 -3 -2 -1 0 VDS (V)
-2.0 VGS
-1.5 VGS
-1.0 VGS
-0.5 VGS
0.0 VGS
+0.5 VGS
Si
SiO
xD
S
G
1 µm
1 µm C. Leiber et. al. , Harvard U
(23)
2/5/2003 Intel Corp. George Bourianoff 23
Crossed Nanowire Structures: A
Powerful Strategy for Creation &
Integration of Nanodevices
Nanowires serve dual purpose: both active devices and
interconnects.
All key nanoscale metrics are defined during synthesis and
subsequent assembly.
Crossed nanowire architecture provides natural scaling and
potential for integration at highest densities.
No additional complexity (with added material).
(24)
Crossed Nanowire FETs
400
200
0
-200
-400
C
u
rrent (nA
)
-1.0
-0.5
0.0
0.5
1.0
Bias (V)
S D
G
Vg(V):
0 1 2 3 10-2 100 102 Curre nt (nA ) 5 4 3 2 1 0 Gate (V)
In crossed nanowire FETs (cNW-FET), all critical nanoscale metrics
are defined by synthesis and assembly:
•
channel width by the active nanowire diameter (to 2 nm)
•
channel length by the gate nanowire diameter (to 1-2 nm)
•
gate dielectric oxide coating on the nanowires (to 1 atomic layer)
The conductance of cNW-FETs can be changed by more than 10
5
-times
with less than 0.1 V variation in the nano-gate.
(25)
2/5/2003 Intel Corp. George Bourianoff 25
Device Demonstrated
P-N Junction
(26)
Room temperature Single
Electron Transistor (SET)
•
•
Single electron
Single electron
in “island”
in “island”
controls current
controls current
flow from
flow from
source to drain
source to drain
•
•
Typical sizes
Typical sizes
of the
of the
TiOx
TiOx
lines are 15
lines are 15
-
-
25
25
nm widths and
nm widths and
30
30
-
-
50 nm
50 nm
lengths.
lengths.
•
•
Typical island
Typical island
sizes are 30
sizes are 30
-
-
50
50
nm by 35
nm by 35
-
-
50
50
nm
nm
(27)
2/5/2003 Intel Corp. George Bourianoff 27
Spin resonance transistor (SRT)
• Transistors that control
spins rather than charge
• More energy efficient than
conventional transistors
• Combines magnetic and
electrostatic fields
• May enable quantum
computing
Courtesy Eli
(28)
A Molecular Electronic Switch
(2-amino-4-ethyinylphenyl-4-ethylphenyl-5-nitro-1-benzenethiolate)
Au
Silicon Nitride
1000 Self Assembled
Molecules (SEM)
Au
IV
Characteristics
1
1
0.00 0.50 1.00 1.50 2.00 2.50 3.00
Voltage (V)
Current
(
pA
)
(29)
2/5/2003 Intel Corp. George Bourianoff 29
The future of nanocomputing
– Introduction
– Scaled CMOS
–
Nano-computing, nano-technology and nano-science
•
A taxonomy
•
New devices
•
New architectures
• Alternative state variables
– Radical new technologies
– Challenges
(30)
Emerging Research Architectures
ARCHITECTURE 3-D INTEGRATION
QUANTUM CELLULAR AUTOMATA DEFECT TOLERANT ARCHITECTURE MOLECULAR ARCHITECTURE CELLULAR NONLINEAR NETWORKS QUANTUM COMPUTING DEVICE IMPLEMENTATION CMOS with dissimilar material systems Arrays of quantum dots Intelligently assembles nanodevices Molecular switches and memories Single electron array architectures Spin resonance transistors, NMR devices, Single flux quantum devices ADVANTAGES Less interconnect delay, Enables mixed technology solutions High functional density. No interconnects in signal path
Supports hardware with defect densities >50% Supports memory based computing Enables utilization of single electron devices at room temperature Exponential performance scaling, Enables unbreakable cryptography CHALLENGES Heat removal, No design tools, Difficult test and measurement
Limited fan out, Dimensional control (low temperature operation), Sensitive to background charge Requires pre-computing test Limited functionality Subject to background noise, Tight tolerances Extreme application limitation, Extreme technology
MATURITY Demonstration Demonstration Demonstration Concept Demonstration Concept
N O2 H 2N
(31)
2/5/2003 Intel Corp. George Bourianoff 31
Quantum Cellular Automata
Adder circuit with carry
executed in QCA logic
Example of asynchronous,
CNN, nearest neighbor
architecture
(32)
Fault tolerant architecture
• All-memory architecture
• Defect tolerant
• Potentially self-repairing and
reconfigurable
J. Heath, R. S. Williams
et al, UCLA and HP
(33)
2/5/2003 Intel Corp. George Bourianoff 33
Phase logic
• Store information in the
relative phase of 2 signals
• Multi-valued logic
possible depending on
frequencies of 2 signals
• Tunneling Phase logic
devices use RTDs to
create one of the signals
Courtesy: R
Courtesy: R
Keihle
Keihle
, University of
, University of
Minnesota
(34)
Quantum Computer
Selected technological
implementations
•Liquid-state NMR
•Linear ion trap
•Coupled quantum dots
•
Deterministically doped
semicondustor structures
31
P
31P
e
-28
Si
Barrier layer
- - -
+ + +
(35)
2/5/2003 Intel Corp. George Bourianoff 35
The future of nanocomputing
– Introduction
– Scaled CMOS
–
Nano-computing, nano-technology and nano-science
• A taxonomy
• New devices
• New architectures
•
Alternative state variables
– Radical new technologies
– Challenges
(36)
Alternative state variables
• Electric charge
• Molecular state
• Spin orientation
• Electric dipole
orientation
• Photon intensity
• Photon polarization
• Quantum state
• Phase state
(37)
2/5/2003 Intel Corp. George Bourianoff 37
The future of nanocomputing
– Introduction
– Scaled CMOS
–
Nano-computing, nano-technology and nano-science
• A taxonomy
• New devices
• New architectures
•
Alternative state variables
–
Radical new technologies
– Challenges
– Conclusions
(38)
Economic criteria
•
Economic relevance criteria
–
The risk adjusted ROI for any new technology must
exceed that of silicon
•
Caution
–
Sufficiently advanced technologies will create their
own applications. New technologies cannot
(39)
2/5/2003 Intel Corp. George Bourianoff 39
Technical criteria
•
CMOS compatibility
•
Energy efficiency
•
Scalability
•
Performance
•
Architectural compatibility
•
Sensitivity to parametric variation
•
Room temperature operation
(40)
Existence proof for alternate models
The brain is the
ultimate model for its
ability to deal with
complexity
• Little understanding on its architecture & organization
• It is however
– Orders of magnitude more powerful than the best microprocessor
– Self assembled
– Parallel operation
– Self repairing to a significant degree
– Fault tolerant
(41)
2/5/2003 Intel Corp. George Bourianoff 41
Breakthrough scientific
investigation is needed
1952 Achievements
•
Bulk
band structure
of solids
•
Doping
•
Crystal growth
2002 Needs
•
geometry dependent
energetic structure of
nanostructures
•
precise location of atoms
•
self organization of matter in
complex structures
(42)
The integration challenge
Scalability Scalability Port Switch Port Switch MemoryMemory MemoryMemory
Scalability Scalability Node Node Controller Controller I/O Hub I/O Hub PCI
PCI--(X)(X)
Bridge Bridge InfiniBand* InfiniBand* Bridge Bridge I/O I/O Bridge Bridge PCI
PCI--(X)(X) Bridge Bridge InfiniBand* InfiniBand* Bridge Bridge I/O I/O Bridge Bridge Scalability Scalability Port Switch Port Switch Scalability Scalability Node Node Controller Controller I/O Hub I/O Hub Intel
(43)
2/5/2003 Intel Corp. George Bourianoff 43
Conclusions
• CMOS scaling will continue for next 12 –15
years
• Alternative new technologies will emerge
and begin to be integrated on CMOS by
2015
• Nanoscience research is needed to facilitate
radical new scalable technologies beyond
2020
(44)
For further information on Intel's silicon technology,
please visit the Silicon Showcase at
(45)
2/5/2003 Intel Corp. George Bourianoff 45
(46)
For about four decades now we have exploited
(mined) our investment in basic science and we
have continuously evolved the devices based
(47)
2/5/2003 Intel Corp. George Bourianoff 47
Leakage is the limiter to SiO2 scaling
Integration is the key challenge to High K
Leakage is the limiter to SiO2 scaling
Leakage is the limiter to SiO2 scaling
Integration is the key challenge to High K
Integration is the key challenge to High K
Silicon substrate
Silicon substrate
Gate
Gate
3.0nm High
3.0nm High
-
-
k
k
90nm process
90nm process
1X
1X
1X
1X
Experimental high
Experimental high
-
-
k
k
1.6X
1.6X
< 0.01X
< 0.01X
Capacitance
Capacitance
Leakage
Leakage
Silicon substrate
Silicon substrate
1.2nm SiO
1.2nm SiO
22Gate
Gate
Source: Intel
Transistor gate oxide thickness trend
1
10
100
1970 1980 1990 2000 2010 2020
First year in production
Dimension (nm)
SiO2High K
Si-O bond:
0.16nm
Nanotechnology for
Gate Dielectrics
(48)
What new basic science is
needed?
•
Spin manipulation
, e.g.
transport, storage, detection,
creation, …
•
Geometry related quantum
effects
, e.g. quantum wedge,
parabolic wells, …
•
Precise location of atoms
e.g.
coherent manipulation of
entangled wavefunctions
R
s
r
→
P+ P+
Si
(49)
2/5/2003 Intel Corp. George Bourianoff 49
Transport in Si-Ge Core-Shell
Structures
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 I DS ( µ A)-4 -3 -2 -1 0
VDS (V)
VGS= -1.1 V
-0.7 -0.9 -0.5 -0.3 0.0 S D G
Si
Ge
SiO
x 1000 800 600 400 200 0 -I DS (n A)-1.0 0.0 1.0
VGS (V)
0.01 0.1 1 10 100 1000 -I DS (n A )
VDS= -1 V
1300 nA/V
330 mV/dec
G
S
D
(50)
Coaxially-Gated Si-Ge
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 I DS ( µ A)-1.5 -1.0 -0.5 0.0
VSD (V)
O VGS -1 VGS
-2 VGS
3.0 2.5 2.0 1.5 1.0 0.5 0.0 I DS ( µ A)
-2 -1 0 1 2
0.1 1 10 100 1000 I DS (n A)
1.5 µA/V
450 mV/dec.
+1 VDS
Si
Ge
SiO
x(51)
2/5/2003 Intel Corp. George Bourianoff 51
Devices Demonstrated
Nanowire FET
(52)
Photonic devices
Man-made crystals
produced by etching
precisely placed holes
in silicon or III-V
material
Can produce, detect and
manipulate light more
efficiently than
naturally occurring
materials
(53)
2/5/2003 Intel Corp. George Bourianoff 53
System software design needs to
facilitate emerging technologies
Challenge
• CMOS is based on Boolean logic and binary data
representation
• Alternative technologies will require “native”
logic systems and data representations to optimize
their performance
Solution?
• Design science must provide functional
abstractions and interfaces to couple multiple,
dissimilar technologies into a single functional
system
(54)
Nano-computing,
(55)
2/5/2003 Intel Corp. George Bourianoff 55
Changing architectural paradigms
Current
•
Boolean logic
•
Binary data
representation
•
2D
•
Homogeneous
•
Globally interconnected
•
Synchronous
•
Von Neuman
•
3 terminal
Future
• Neural networks, CNN,
QCA,…
• Associative, patterned,
memory based, … data
representations
• 3D
• Non homogeneous
• Nearest neighbor
• Asynchronous
• Integrated memory/logic
• 2 terminal
(1)
2/5/2003 Intel Corp. George Bourianoff 50
Coaxially-Gated Si-Ge
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 I DS ( µ A)-1.5 -1.0 -0.5 0.0 VSD (V)
O VGS
-1 VGS
-2 VGS
3.0 2.5 2.0 1.5 1.0 0.5 0.0 I DS ( µ A)
-2 -1 0 1 2
VGS (V)
0.1 1 10 100 1000 I DS (n A)
1.5 µA/V
450 mV/dec.
+1 VDS
Si
Ge
SiOx
(2)
Devices Demonstrated
Nanowire FET
(3)
2/5/2003 Intel Corp. George Bourianoff 52
Photonic devices
Man-made crystals
produced by etching precisely placed holes in silicon or III-V
material
Can produce, detect and manipulate light more efficiently than
naturally occurring materials
(4)
System software design needs to
facilitate emerging technologies
Challenge
• CMOS is based on Boolean logic and binary data representation
• Alternative technologies will require “native”
logic systems and data representations to optimize their performance
Solution?
• Design science must provide functional
abstractions and interfaces to couple multiple, dissimilar technologies into a single functional
(5)
2/5/2003 Intel Corp. George Bourianoff 54
Nano-computing,
(6)
Changing architectural paradigms
Current
• Boolean logic
• Binary data
representation
• 2D
• Homogeneous
• Globally interconnected
• Synchronous
• Von Neuman
Future
• Neural networks, CNN, QCA,…
• Associative, patterned, memory based, … data representations
• 3D
• Non homogeneous • Nearest neighbor • Asynchronous