Index of /intel-research/silicon

(1)

Si

and Non

-

Si

Nanotechnologies

and their Benchmarking

Robert Chau

I ntel Fellow

Director of Transistor Research and Nanotechnology

Technology & Manufacturing Group

I ntel Corporation

April 25, 2005

(2)

Content

I ntroduction

Benchmarking metrics

Benchmarking methodology

Benchmarking results

(3)

Transistor Scaling

Technology

Node

0.5µm

0.35µm

0.25µm

0.18µm

0.13µm 90nm 65nm 45nm 30nm

Transistor

Physical Gate

Length

130nm 70nm 50nm 30nm 20nm 15nm

1995

2005

1990

2000

2010

0.01

0.10

1.00 M

icromete

r

Nanotechnology

10

100 1000

Na

nome

te

r

Technology

Node

0.5µm

0.35µm

0.25µm

0.18µm

0.13µm 90nm 65nm 45nm 30nm

Transistor

Physical Gate

Length

130nm 70nm 50nm 30nm 20nm 15nm

1995

2005

1990

1995

2000

2005

2010

1990

2000

2010

0.01

0.10

1.00 M

icromete

r

0.01

0.10

1.00 M

icromete

r

Nanotechnology

10

100 1000

Na

nome

te

r

10

100 1000

Na

nome

te

r

Transistor physical gate length will reach ~ 15 nm before

end of this decade, and ~ 10 nm early next decade

(4)

Emerging Nanoelectronic Devices

5 n m 5 n m

2.0 nm High-K Gate

5.0 nm Si Nanowire

5 n m 5 n m

2.0 nm High-K Gate

5.0 nm Si Nanowire (e)

10nm

( a) 10nm L_G Si MOSFET ( b) Non- planar Si Tri- gate ( c) I I I - V QWFET

( d) CNT FET

(5)

Benchmarking Metrics

Benchmark emerging nanoelectronic devices

against state-of-the-art Si devices

Separate reality from hype

I dentify device strengths and shortcomings

Gauge research progress

4 key device metrics

CV/ I vs L

-- I ntrinsic speed

Energy-Delay product vs L

-- Switching energy

Subthreshold slope vs L

-- Scalability

CV/ I vs I

_ON

/ I

_OFF

-- I

_OFF

vs speed tradeoff

(6)

Benchmarking Methodology

I

_ON

= I

_DS

at | V

_DS

| = V

_CC

and | V

–V

| = 2 V

_CC

/ 3

I

_OFF

= I

_DS

at | V

_DS

| = V

_CC

and | V

–V

| = V

_CC

/ 3

Measure or estimate capacitance C

(7)

I ntrinsic Gate Delay CV/ I for PMOS

D = 1 to 2.5 nm D = 4 to 35 nm

CNT shows significant p-channel CV/ I improvement over Si

CNT has > 20x higher effective p-channel mobility than Si

(8)

Energy

-

Delay Product for PMOS

CNT shows significant p-channel energy-delay product

improvement over Si due to higher effective p-channel

mobility than Si

(9)

Subthreshold Slope vs L

_G

for PMOS

Si Planar (V_CC = 1.0-1.5V)

Si Tri-gate (V_CC = 1.1V) CNTFETs

(V_CC = 0.3-0.5V)

(10)

PMOS CV/ I versus I

_ON

/ I

_OFF

Ratio

(Metal-CNT

source/drain contacts)

For I_ON/ I_OFF < 100, CNT shows improvement over Si due to higher

(11)

Ambipolar Conduction: Parasitic Leakage in CNTs

CNTs use metal-CNT Schottky contacts to form source and drain,

which leads to ambipolar conduction

(12)

I ntrinsic Gate Delay CV/ I for NMOS

n-channel CNT not as well established as p-channel CNT

I I I -V (e.g. I nSb) devices show significant CV/ I improvement over Si

(13)

Energy

-

Delay Product for NMOS

I I I -V (e.g. I nSb) devices show significant energy-delay product

improvement over Si due to > 50X higher effective mobility and

(14)

Subthreshold Slope vs L

_G

for NMOS

Si Planar (V_CC = 1.0-1.5V)

Si Tri-gate (V_CC = 1.1V) CNTFETs

(V_CC = 0.3-0.5V)

Tri-gate

(15)

NMOS CV/ I versus I

_ON

/ I

_OFF

Ratio

Chemically-doped junction delays ambipolar conduction Due to Schottky

gate leakage

Use of chemically-doped junctions delays the ambipolar conduction in

the CNTFET despite poor gate delay performance at present

(16)

Summary

Need to diligently benchmark emerging

nanoelectronic devices against state-of-the-art

Si data to

identify potential device strengths and shortcomings,

and

to gauge research progress

Emerging non-Si nanoelectronic devices show

both challenges and opportunities for future

logic transistor applications

(17)

References

R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A.

Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications”, I EEE Transactions on Nanotechnology, vol. 4, pp. 153-158, 2005.

R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J.

Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Emerging Silicon and Non-Silicon Nanoelectronic Devices:

Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications”, Proceedings of Technical Papers, 2005 I EEE VLSI -TSA I nternational Symposium on VLSI Technology, Hsinchu, Taiwan, pp. 13-16, April 25-27, 2005.

(1)

I ntrinsic Gate Delay CV/ I for NMOS

n-channel CNT not as well established as p-channel CNT

I I I -V (e.g. I nSb) devices show significant CV/ I improvement over Si

I I I -V devices have > 50X higher effective n-ch mobility than Si I I I -V devices operated at low VCC = 0.5V

(2)

Energy

(3)

Subthreshold Slope vs L

_G

for NMOS

Si Planar (V_CC = 1.0-1.5V) Si Tri-gate (V_CC = 1.1V) CNTFETs

(V_CC = 0.3-0.5V)

Tri-gate

(4)

NMOS CV/ I versus I

_ON

/ I

_OFF

Ratio

Chemically-doped junction delays ambipolar conduction Due to Schottky

(5)

Summary

Need to diligently benchmark emerging

nanoelectronic devices against state-of-the-art

Si data to

identify potential device strengths and shortcomings,

and

to gauge research progress

Emerging non-Si nanoelectronic devices show

both challenges and opportunities for future

logic transistor applications

(6)

References

R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A.

R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J.

Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Emerging Silicon and Non-Silicon Nanoelectronic Devices: