Index of /intel-research/silicon
2003 IRPS
High Performance Logic
Technology and Reliability Challenges
Mark Bohr
Intel Senior Fellow
Director of Process Architecture & Integration
®
April 1, 2003
Outline
y Logic Technology Evolution
y 90 nm Logic Technology
y Future Scaling Challenges
®
2
CPU Transistor Count Trend
1 billion transistor CPU by 2007
1,000,000,000
Itanium® 2 CPU
100,000,000
Pentium® 4 CPU
Pentium® III CPU
10,000,000
Pentium® II CPU
Pentium® CPU
486TM CPU
1,000,000
386TM CPU
100,000
286
8086
10,000
8080
8008
4004
1,000
1970
®
1980
1990
2000
2010
3
CPU MHz Trend
10 GHz CPU by 2007
10,000
Pentium® 4 CPU
1,000
Pentium® III CPU
Pentium® II CPU
Pentium® CPU
MHz
100
486TM CPU
386TM CPU
286
8086
10
8080
1
1970
®
1980
1990
2000
2010
4
Feature Size Trend
10
10000
3.0um
1
Micron
0.1
0.01
1970
2.0um
1.5um
1.0um
Feature
.8um
.5um
Size
.35um
.25um
.18um
.13um
90nm
1980
1990
2000
2010
1000
Nanometer
100
10
2020
New technology generation introduced every 2 years
®
5
Feature Size Trend
10
10000
3.0um
1
Micron
0.1
2.0um
1.5um
1.0um
Feature
.8um
.5um
Size
.35um
.25um
.18um
.13um
90nm
Gate
Length
1000
Nanometer
100
50nm
0.01
1970
1980
1990
2000
2010
10
2020
Transistor gate length scaling faster for improved performance
®
6
CPU Power Trend
100
Pentium® 4
CPU
Pentium Pro®
CPU
Power
10
(W)
Pentium® II/II
CPU
Pentium®
CPU
486
386
1
1.5
1.0
0.8
0.5
0.35 0.25 0.18 0.13 0.09
Generation (um)
CPU power growing due to increased operating
frequency and increased transistor count
®
7
Logic Technology Evolution
Each new technology generation provides:
~ 0.7x minimum feature size scaling
~ 2.0x increase in transistor density
~ 1.5x faster transistor switching speed
Reduced chip power
Reduced chip cost
®
8
Outline
y Logic Technology Evolution
y 90 nm Logic Technology
y Future Scaling Challenges
®
9
Key 90 nm Process Features
High Speed, Low Power Transistors
– 1.2 nm gate oxide
– 50 nm gate length
– Strained silicon technology
Faster, Denser Interconnects
– 7 copper layers
– New low-k dielectric
Lower Chip Cost
– 1.0 µm2 SRAM memory cell size
– 300 mm wafers
®
10
90 nm Generation Transistor
W Contact
NiSi Layer
Silicon Gate
Electrode
50nm
1.2 nm SiO2
Gate Oxide
Strained
Silicon
®
11
90 nm Generation Gate Oxide
Polysilicon
Gate Electrode
1.2 nm SiO2
Silicon Substrate
Gate oxide is less than 5 atomic layers thick
®
12
1.2 nm Gate Oxide Reliability
1.E+09
10 Years
1.E+08
1.E+07
TDDB 1.E+06
(sec)
1.E+05
VMAX=1.2V
1.E+04
1.E+03
T=110C
1.E+02
5
6
7
EOX
8
9
(MV/cm)
10
11
12
1.2 nm gate oxide exceeds 1.2 V reliability criteria
®
13
Strained Silicon Transistors
Current Flow
Normal
electron
flow
Normal Silicon Lattice
®
Faster
electron
flow
Strained Silicon Lattice
10-20% drive
current increase
14
Transistor Performance Trend
1.4
10
90 nm
1.2
1.0
Drive
Current
(mA/um)
0.8
0.6
0.4
Supply
Voltage
(V)
NMOS
PMOS
0.2
0.0
1990
1
1995
2000
2005
• Increased drive current for performance
• Reduced voltage for power and reliability
®
15
90 nm Generation Interconnects
7 layers of copper interconnect
– 1 more layer than 0.13 µm generation
– Extra layer provides cost effective improvement in logic
density
New low-k dielectric introduced to reduce wire-wire
capacitance
– Carbon-doped oxide (CDO) dielectric reduces capacitance
by 18% compared to SiOF dielectric used on 0.13 µm
– Reduced capacitance speeds up intra-chip communication
and reduces chip power
®
16
90 nm Generation Interconnects
pitch
M7 1080 nm
Low-k CDO
Dielectric
Copper
Interconnects
M6
720 nm
M5
480 nm
M4
400 nm
M3
320 nm
M2
320 nm
M1
220 nm
Coarse pitch at upper layers for low resistance
Fine pitch at lower layers for high density
®
17
Cu + CDO Interconnects
Thin SiN layer
Cu
CDO K = 2.9
No trench
etch stop layer
®
18
Void-Free Required for Electromigration
V1
Old Process
New Process
M1
®
19
Electromigration Enabling
Old process
New process
CDO
Cu
CDO
Cu
Interface controls EM performance
®
20
Electromigration Improvement
First EM
Process 3
Process 1 Process 2 Process 4
99
95
90
Percent
80
70
60
50
40
30
20
10
5
1
1
10
100
1000
Time
to Fail
Ti
®
21
6-T SRAM Cell
y SRAM cell has area of 1.0 µm2
y Same process as high performance
logic
y Small memory cell enables cost
effective increase in CPU
performance by adding more on-die
cache memory
1 µm
®
22
Intel SRAM Cell Size Trend
100
10
Cell Area
(um2)
.71x
per year
1
90 nm
0.1
1990
1995
2000
2005
90 nm cell is ~half the area of 130 nm generation cell
®
23
52 Mbit SRAM on 90 nm Process
10.1 mm
10.8 mm
330 million transistors on single chip
Initial 90 nm process certification vehicle
Same process and design rules as CPU products
®
24
Same Process for Logic and SRAM
• Microprocessors use same
transistors and interconnects
for Logic and SRAM
• On-die SRAM cache transistor
count increasing for improved
performance
Logic
SRAM
0.18 µm Itanium® 2 Processor
144M SRAM, 220M Total
®
25
52 Mbit SRAM Chips on 300 mm Wafer
120 billion transistors on one wafer
®
26
Outline
y Logic Technology Evolution
y 90 nm Logic Technology
y Future Scaling Challenges
®
27
Planar CMOS Transistor Scaling
Today
Future
25 nm
15nm
50 nm
30 nm
20 nm
Gate Length
15 nm
R&D groups exploring aggressive scaling
of conventional planar CMOS transistors
Source: Intel Components Research
®
28
Transistor IOFF Leakage Trend
1.E-04
Research data
(
in literature
)
1.E-06
IOFF
(A/um)
1.E-08
1.E-10
Production data
Intel 15 nm
transistor
Intel 30 nm
(2001)
transistor
(2000)
( )
1.E-12
1.E-14
10
100
1000
Transistor Physical LG (nm)
• Transistor leakage current increasing as VT scales
• Leakage power is becoming a larger % of total chip power
®
29
Fully Depleted Transistors
1E-03
VD = 1.3V
1E-04
LG
SiO2
ID (A/µm)
TSi
VD = 0.05V
1E-05
1E-06
Matched IOFF
1E-07
FD SOI
DST
Bulk Silicon
1E-08
1E-09
0
Fully-Depleted SOI (planar)
0.25
0.5
0.75
1
1.25
VG (Volts)
Source: Intel Components Research
• FD SOI provides steeper sub-threshold slope, which
can be used to reduce IOFF or increase IDSAT
• Cost and controllability of thin SOI layer are key
manufacturing problems
®
30
Fully Depleted Transistors
TSi
Lg
Lg
WSi
Double-Gate (non-planar)
WSi
TSi
Tri-Gate (non-planar)
Double-gate or triple-gate devices offer steep sub-threshold
slope, but with more complex process than planar transistors
®
31
Transistor IGATE Leakage Trend
1000
10
100
10
IGATE
(A/cm2)
Tox
(nm)
1
0.1
0.01
0.001
1
90 130 180 250 350 500
Technology Generation (nm)
Gate oxide leakage increasing exponentially due to tunneling current
®
32
High-k Gate Dielectric
1E+1
1E+0
TiO2
HfO2
2
JOX @1V (A/cm )
1E-1
1E-2
1E-3
ZrO2
SiO2
1E-4
Ta2O5
Better
1E-5
Al2O3
1E-6
1E-7
1E-8
0.50
1.00
1.50
2.00
2.50
3.00
3.50
2
Cox (µ F/cm )
Source: Intel Components Research
High-k dielectrics provide higher capacitance and reduced leakage
®
33
Early Problems with High-K Dielectrics
Gate Capacitance
Electron Mobility (cm2/V.s)
500
-0.5
0
0.5
1
1.5
Gate Bias
VT instability due to charge traps
450
Universal Mobility
Curve
400
350
300
250
SiO2
200
150
100
50
High-K
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Eeff (MV/cm)
Degraded inversion layer mobility
SiO2 will be difficult to replace as the gate dielectric
®
34
Interconnect Delay
10
< 100 MHz
Interconnect
Delay
(nsec)
Al + SiO2
1
10 mm Line
< 1 GHz
1 mm Line
0.1
< 10 GHz
0.01
0.1
•
•
•
•
®
1
Interconnect Pitch (um)
10
Interconnect delay getting worse as pitch scales
Scaling line length helps keep delay constant
Material changes such as Cu and low-k needed for lower RC
Adding more metal layers is an expensive alternative
35
Narrow Line Width Resistivity Increase
2.5
2.0
Cu
Resistivity 1.5
(normalized)
1.0
0.5
0
100
200
300
Line Width (nm)
400
500
Cu resistivity increases for narrow lines due to:
• Finite barrier layer thickness
• Electron mean free path comparable to line width
®
36
Electromigration Requirements
10
Current
Density
Requirement
(normalized)
Cu
Al
1
65
90 130 180 250 350 500
Technology Generation (nm)
• Current density increases ~1.5x per generation as feature size
decreases and operating frequency increases
• EM improved on Al by adding alloy ingredients and shunt layers
• Change to Cu provided big EM boost, but future generations will
need Cu EM improvements
®
37
Fragile Low-k Dielectric Materials
Si Chip
Organic
Package
Solder
Bumps
• Low-k dielectric materials are mechanically weaker than SiO2
• CTE mismatch between chip and package causes stress
during chip bonding step
• Stress can cause interconnect deformation or ILD cracking
®
38
Summary
• High performance logic technology has scaled
at a rapid pace down to the 90 nm generation,
providing significant gains in density and
performance
• Going forward, transistor and interconnect
scaling challenges look formidable
• New materials and new device structures are
needed and options are emerging that show
promise for continued scaling
®
39
For further information on Intel's silicon technology,
please visit:
www.intel.com/research/silicon
®
40
High Performance Logic
Technology and Reliability Challenges
Mark Bohr
Intel Senior Fellow
Director of Process Architecture & Integration
®
April 1, 2003
Outline
y Logic Technology Evolution
y 90 nm Logic Technology
y Future Scaling Challenges
®
2
CPU Transistor Count Trend
1 billion transistor CPU by 2007
1,000,000,000
Itanium® 2 CPU
100,000,000
Pentium® 4 CPU
Pentium® III CPU
10,000,000
Pentium® II CPU
Pentium® CPU
486TM CPU
1,000,000
386TM CPU
100,000
286
8086
10,000
8080
8008
4004
1,000
1970
®
1980
1990
2000
2010
3
CPU MHz Trend
10 GHz CPU by 2007
10,000
Pentium® 4 CPU
1,000
Pentium® III CPU
Pentium® II CPU
Pentium® CPU
MHz
100
486TM CPU
386TM CPU
286
8086
10
8080
1
1970
®
1980
1990
2000
2010
4
Feature Size Trend
10
10000
3.0um
1
Micron
0.1
0.01
1970
2.0um
1.5um
1.0um
Feature
.8um
.5um
Size
.35um
.25um
.18um
.13um
90nm
1980
1990
2000
2010
1000
Nanometer
100
10
2020
New technology generation introduced every 2 years
®
5
Feature Size Trend
10
10000
3.0um
1
Micron
0.1
2.0um
1.5um
1.0um
Feature
.8um
.5um
Size
.35um
.25um
.18um
.13um
90nm
Gate
Length
1000
Nanometer
100
50nm
0.01
1970
1980
1990
2000
2010
10
2020
Transistor gate length scaling faster for improved performance
®
6
CPU Power Trend
100
Pentium® 4
CPU
Pentium Pro®
CPU
Power
10
(W)
Pentium® II/II
CPU
Pentium®
CPU
486
386
1
1.5
1.0
0.8
0.5
0.35 0.25 0.18 0.13 0.09
Generation (um)
CPU power growing due to increased operating
frequency and increased transistor count
®
7
Logic Technology Evolution
Each new technology generation provides:
~ 0.7x minimum feature size scaling
~ 2.0x increase in transistor density
~ 1.5x faster transistor switching speed
Reduced chip power
Reduced chip cost
®
8
Outline
y Logic Technology Evolution
y 90 nm Logic Technology
y Future Scaling Challenges
®
9
Key 90 nm Process Features
High Speed, Low Power Transistors
– 1.2 nm gate oxide
– 50 nm gate length
– Strained silicon technology
Faster, Denser Interconnects
– 7 copper layers
– New low-k dielectric
Lower Chip Cost
– 1.0 µm2 SRAM memory cell size
– 300 mm wafers
®
10
90 nm Generation Transistor
W Contact
NiSi Layer
Silicon Gate
Electrode
50nm
1.2 nm SiO2
Gate Oxide
Strained
Silicon
®
11
90 nm Generation Gate Oxide
Polysilicon
Gate Electrode
1.2 nm SiO2
Silicon Substrate
Gate oxide is less than 5 atomic layers thick
®
12
1.2 nm Gate Oxide Reliability
1.E+09
10 Years
1.E+08
1.E+07
TDDB 1.E+06
(sec)
1.E+05
VMAX=1.2V
1.E+04
1.E+03
T=110C
1.E+02
5
6
7
EOX
8
9
(MV/cm)
10
11
12
1.2 nm gate oxide exceeds 1.2 V reliability criteria
®
13
Strained Silicon Transistors
Current Flow
Normal
electron
flow
Normal Silicon Lattice
®
Faster
electron
flow
Strained Silicon Lattice
10-20% drive
current increase
14
Transistor Performance Trend
1.4
10
90 nm
1.2
1.0
Drive
Current
(mA/um)
0.8
0.6
0.4
Supply
Voltage
(V)
NMOS
PMOS
0.2
0.0
1990
1
1995
2000
2005
• Increased drive current for performance
• Reduced voltage for power and reliability
®
15
90 nm Generation Interconnects
7 layers of copper interconnect
– 1 more layer than 0.13 µm generation
– Extra layer provides cost effective improvement in logic
density
New low-k dielectric introduced to reduce wire-wire
capacitance
– Carbon-doped oxide (CDO) dielectric reduces capacitance
by 18% compared to SiOF dielectric used on 0.13 µm
– Reduced capacitance speeds up intra-chip communication
and reduces chip power
®
16
90 nm Generation Interconnects
pitch
M7 1080 nm
Low-k CDO
Dielectric
Copper
Interconnects
M6
720 nm
M5
480 nm
M4
400 nm
M3
320 nm
M2
320 nm
M1
220 nm
Coarse pitch at upper layers for low resistance
Fine pitch at lower layers for high density
®
17
Cu + CDO Interconnects
Thin SiN layer
Cu
CDO K = 2.9
No trench
etch stop layer
®
18
Void-Free Required for Electromigration
V1
Old Process
New Process
M1
®
19
Electromigration Enabling
Old process
New process
CDO
Cu
CDO
Cu
Interface controls EM performance
®
20
Electromigration Improvement
First EM
Process 3
Process 1 Process 2 Process 4
99
95
90
Percent
80
70
60
50
40
30
20
10
5
1
1
10
100
1000
Time
to Fail
Ti
®
21
6-T SRAM Cell
y SRAM cell has area of 1.0 µm2
y Same process as high performance
logic
y Small memory cell enables cost
effective increase in CPU
performance by adding more on-die
cache memory
1 µm
®
22
Intel SRAM Cell Size Trend
100
10
Cell Area
(um2)
.71x
per year
1
90 nm
0.1
1990
1995
2000
2005
90 nm cell is ~half the area of 130 nm generation cell
®
23
52 Mbit SRAM on 90 nm Process
10.1 mm
10.8 mm
330 million transistors on single chip
Initial 90 nm process certification vehicle
Same process and design rules as CPU products
®
24
Same Process for Logic and SRAM
• Microprocessors use same
transistors and interconnects
for Logic and SRAM
• On-die SRAM cache transistor
count increasing for improved
performance
Logic
SRAM
0.18 µm Itanium® 2 Processor
144M SRAM, 220M Total
®
25
52 Mbit SRAM Chips on 300 mm Wafer
120 billion transistors on one wafer
®
26
Outline
y Logic Technology Evolution
y 90 nm Logic Technology
y Future Scaling Challenges
®
27
Planar CMOS Transistor Scaling
Today
Future
25 nm
15nm
50 nm
30 nm
20 nm
Gate Length
15 nm
R&D groups exploring aggressive scaling
of conventional planar CMOS transistors
Source: Intel Components Research
®
28
Transistor IOFF Leakage Trend
1.E-04
Research data
(
in literature
)
1.E-06
IOFF
(A/um)
1.E-08
1.E-10
Production data
Intel 15 nm
transistor
Intel 30 nm
(2001)
transistor
(2000)
( )
1.E-12
1.E-14
10
100
1000
Transistor Physical LG (nm)
• Transistor leakage current increasing as VT scales
• Leakage power is becoming a larger % of total chip power
®
29
Fully Depleted Transistors
1E-03
VD = 1.3V
1E-04
LG
SiO2
ID (A/µm)
TSi
VD = 0.05V
1E-05
1E-06
Matched IOFF
1E-07
FD SOI
DST
Bulk Silicon
1E-08
1E-09
0
Fully-Depleted SOI (planar)
0.25
0.5
0.75
1
1.25
VG (Volts)
Source: Intel Components Research
• FD SOI provides steeper sub-threshold slope, which
can be used to reduce IOFF or increase IDSAT
• Cost and controllability of thin SOI layer are key
manufacturing problems
®
30
Fully Depleted Transistors
TSi
Lg
Lg
WSi
Double-Gate (non-planar)
WSi
TSi
Tri-Gate (non-planar)
Double-gate or triple-gate devices offer steep sub-threshold
slope, but with more complex process than planar transistors
®
31
Transistor IGATE Leakage Trend
1000
10
100
10
IGATE
(A/cm2)
Tox
(nm)
1
0.1
0.01
0.001
1
90 130 180 250 350 500
Technology Generation (nm)
Gate oxide leakage increasing exponentially due to tunneling current
®
32
High-k Gate Dielectric
1E+1
1E+0
TiO2
HfO2
2
JOX @1V (A/cm )
1E-1
1E-2
1E-3
ZrO2
SiO2
1E-4
Ta2O5
Better
1E-5
Al2O3
1E-6
1E-7
1E-8
0.50
1.00
1.50
2.00
2.50
3.00
3.50
2
Cox (µ F/cm )
Source: Intel Components Research
High-k dielectrics provide higher capacitance and reduced leakage
®
33
Early Problems with High-K Dielectrics
Gate Capacitance
Electron Mobility (cm2/V.s)
500
-0.5
0
0.5
1
1.5
Gate Bias
VT instability due to charge traps
450
Universal Mobility
Curve
400
350
300
250
SiO2
200
150
100
50
High-K
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Eeff (MV/cm)
Degraded inversion layer mobility
SiO2 will be difficult to replace as the gate dielectric
®
34
Interconnect Delay
10
< 100 MHz
Interconnect
Delay
(nsec)
Al + SiO2
1
10 mm Line
< 1 GHz
1 mm Line
0.1
< 10 GHz
0.01
0.1
•
•
•
•
®
1
Interconnect Pitch (um)
10
Interconnect delay getting worse as pitch scales
Scaling line length helps keep delay constant
Material changes such as Cu and low-k needed for lower RC
Adding more metal layers is an expensive alternative
35
Narrow Line Width Resistivity Increase
2.5
2.0
Cu
Resistivity 1.5
(normalized)
1.0
0.5
0
100
200
300
Line Width (nm)
400
500
Cu resistivity increases for narrow lines due to:
• Finite barrier layer thickness
• Electron mean free path comparable to line width
®
36
Electromigration Requirements
10
Current
Density
Requirement
(normalized)
Cu
Al
1
65
90 130 180 250 350 500
Technology Generation (nm)
• Current density increases ~1.5x per generation as feature size
decreases and operating frequency increases
• EM improved on Al by adding alloy ingredients and shunt layers
• Change to Cu provided big EM boost, but future generations will
need Cu EM improvements
®
37
Fragile Low-k Dielectric Materials
Si Chip
Organic
Package
Solder
Bumps
• Low-k dielectric materials are mechanically weaker than SiO2
• CTE mismatch between chip and package causes stress
during chip bonding step
• Stress can cause interconnect deformation or ILD cracking
®
38
Summary
• High performance logic technology has scaled
at a rapid pace down to the 90 nm generation,
providing significant gains in density and
performance
• Going forward, transistor and interconnect
scaling challenges look formidable
• New materials and new device structures are
needed and options are emerging that show
promise for continued scaling
®
39
For further information on Intel's silicon technology,
please visit:
www.intel.com/research/silicon
®
40