Index of /intel-research/silicon 65nm IEDM 04 foils

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A 65 nm Logic Technology Featuring

35 nm Gate Length, Enhanced Channel

Strain, 8 Cu Interconnect Layers, Low

-

-k ILD and 0.57um

k ILD and 0.57um

_{SRAM Cell}

P.Bai, C.Auth, S.Balakrishnan, M.Bost, R.Brain, V.Chikarmane, R.Heussner, M.Hussein, J.Hwang, D.Ingerly, R.James, J.Jeong,

C.Kenyon, E.Lee, S.H.Lee, N.Lindert, M.Liu, Z.Ma*, T.Marieb*, A.Murthy, R.Nagisetty, S.Natarajan, J.Neirynck, A.Ott, C.Parker,

J.Sebastian, R.Shaheed**, S.Sivakumar, J.Steigerwald, S.Tyagi, C.Weber**, B.Woolery*, A.Yeoh, K.Zhang, and M.Bohr

Portland Technology Development, *QRE, **TCAD, Intel Corporation, Hillsboro, OR, USA

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Outline

•

65 nm technology dimensional scaling

•

Transistor features and performance

•

Interconnect features and performance

•

SRAM test vehicle

•

(3)

0.01 0.1 1 10

1980 1990 2000 2010 2020

Micron 10 100 1000 10000 nm 193nm 13nm EUV 248nm 365nm Lithography Wavelength 65nm 90nm 130nm Feature Size Gap

Lithography Challenge at 65 nm

Minimum feature size at significant gap to lithography waveleng

Minimum feature size at significant gap to lithography wavelengthth Advanced

(4)

Leading

-

Edge OPC and APSM Masks

Sub-resolution Optical Proximity Correction

Drawn structure Add OPC features Mask structure Printed on wafer

Phase shift masks enable patterning 35 nm lines

0° 180° 0° 0° 180°

(5)

Aggressive Design Rule and Metal AR

Layer Pitch (nm) Thickness (nm) Aspect Ratio

Isolation 220 320 NA

Poly silicon 220 90 NA

Contacted gate 220 NA NA

Metal 1 210 170 1.6

Metal 2 210 190 1.8

Metal 3 220 200 1.8

Metal 4 280 250 1.8

Metal 5 330 300 1.8

Metal 6 480 430 1.8

Metal 7 720 650 1.8

Metal 8 1080 975 1.8

65 nm node continues ~70% linear scaling

Metal aspect ratio optimized for RC delay

(6)

Transistor Features

• 35 nm gate length

• 220 nm contacted gate pitch

• 1.2 nm physical gate oxide

•

2 _{generation of strained silicon}

(7)

Logic Transistor Gate Length Trend

65 nm continues aggressive gate length scaling

(8)

0.1 1 10

1992 1994 1996 1998 2000 2002 2004 2006 Contacted

Gate Pitch (micron)

0.7x every 2 years

Contacted Gate Pitch

Pitch

Transistor gate pitch continues to scale 0.7x per

generation, now 220 nm on 65 nm generation

(9)

1.2 nm Gate Oxide

0 1 2 3 4 5 65 90 130 180 250 Tox (nm) Gate Leakage (log scale)

• Gate oxide thickness is held at 1.2 nm to avoid increased gate leakage

• Gate capacitance (C_GATE) reduced ~20% due to smaller gate length (35 nm)

• Lower gate capacitance improves performance and reduces active power

Gate

Substrate

Source Drain

(10)

NMOS with Enhanced Strain

S D

35 nm

Tensile

Tensile SiNSiN capping films for enhanced capping films for enhanced uniaxialuniaxial strain strain Shallow/abrupt junction for SCE control for 35 nm gate

(11)

PMOS with Enhanced Strain

D G

Epitaxial

Epitaxial SiGeSiGe film embedded into S/D film embedded into S/D –– same as 90 nmsame as 90 nm Enhanced strain by higher

(12)

Intel 2

NDND

_{Generation Strained Silicon}

Strain-induced performance gain summary

90 nm 65 nm

NMOS PMOS NMOS PMOS

Mobility 20% 55% 35% 90%

I_DSAT 10% 30% 18% 50%

I_DLIN 10% 55% 18% 80%

65 nm transistors improve strain over 90 nm

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NMOS I

_DSAT_DSAT

vs

I

_OFF_OFF

0.1 1 10 100 1000 10000

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 IDSAT (mA/µm)

IO F F (n A /µ m)

100 nA/µm

90nm at 1.2V [1]

1.2 V_CC 1.0 V_CC

1.46 mA/µm 1.15 mA/µm

90nm at 1.0V [1]

Record 1.46

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PMOS I

_DSAT_DSAT

vs

I

_OFF_OFF

0.1 1 10 100 1000 10000

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 IDSAT (mA/µm)

IO F F (n A /µ m)

100 nA/µm

1.0 V_CC

1.2 V_CC

90nm at 1.2V [1]

0.88 mA/µm 0.67 mA/µm

90nm at 1.0V [1]

Record 0.88

(15)

1 10 100 1000

0.2 0.4 0.6 0.8 1.0 1.2

I_ON(mA/um)

I_OFF

(nA/um)

PMOS NMOS

90 nm 2002

1.0 V

Better Better

Improved Transistor Performance

Improved transistors provide increased drive current at constant leakage current

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1 10 100 1000

0.2 0.4 0.6 0.8 1.0 1.2

I_ON(mA/um)

I_OFF

(nA/um)

PMOS NMOS

90 nm 2002 2004

1.0 V

Improved Transistor Performance

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1 10 100 1000

0.2 0.4 0.6 0.8 1.0 1.2

I_ON(mA/um)

I_OFF

(nA/um)

PMOS NMOS

90 nm 2002 2004

65 nm 2004

1.0 V

Improved Transistor Performance

65 nm transistors increase drive current 10-15% with enhanced strain

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1 10 100 1000

0.2 0.4 0.6 0.8 1.0 1.2

I_ON(mA/um)

I_OFF

(nA/um)

PMOS NMOS

90 nm 2002 2004

65 nm 2004

1.0 V

65 nm transistors can alternatively provide ~4x leakage reduction

Improved Transistor Performance

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Sub

-

threshold Characteristics

Well controlled short channel effects

Sub

Sub--threshold slope ~100 mV/decadethreshold slope ~100 mV/decade 0.01

0.1 1 10 100 1000 10000

-1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2

VGS (V)

(µ A/µ

PMOS NMOS

(20)

Ni

Salicide

Capable for 35 nm Gate

8.0 10.0 12.0 14.0 16.0 18.0 20.0

0.03 0.04 0.05 0.06 0.07

Poly Gate Length (um)

S h eet r e si st an ce ( o h m /s q ) P poly N poly NiSi

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8 Layers Cu Interconnect

• Dual damascene Cu

• 1.8 T/W aspect ratio

• CDO low-k ILD

• SiCN etch-stop layer replaces SiN for 5% total ILD cap reduction

• Graduated pitches for optimizing density vs. performance M8 M8 M7 M7 M6 M6 M5 M5 M4 M4 M3 M3 M2 M2 M1 M1

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Interconnect RC Performance

0 20 40 60 80 100 120 140

200 300 400 500 600 700 800

Min Pitch (nm)

/mm^

2 _90nm

130nm 65nm

1 mm fixed wire length

65 nm continues the intrinsic RC improvement

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0.57 µ

m

₆

_-

_{T SRAM Cell}

0.1 1 10 100

1992 1994 1996 1998 2000 2002 2004 2006

Cell Area

(um2) 0.5x every _{2 years}

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High Performance 70

Mbit

SRAM

• 0.57 µm2 _{cell size}

• >0.5 billion transistors

• 110 mm2 _{chip size}

• Uses all process features

• Capable of supporting Vdd at 0.7V.

• Fully functional 70 Mbit SRAM chips have been fabricated.

(25)

High Performance 70

Mbit

SRAM

0.9 1.0 1.1 1.2 1.3 1.4 1.5

Cycle Time (ns)

(V)

0.2 0.62

FAIL

PASS

3.43 GHz @ 1.2V

Demonstrated 3.43 GHz at 1.2V

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Defect Reduction Trend

130nm 130nm 90nm 65nm

200mm 300mm 300mm 300mm

2000 2001 2002 2003 2004 Defect

Density

(log scale) Two Years

65 nm yield on same improvement rate with 2 years offset

(27)

65 nm Microprocessor Prototypes

Fabricated

Single Core Dual Core 65 nm process ready for

65 nm process ready for

high volume manufacturing in 2005

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Conclusion

•

An industry leading 65 nm logic technology is presented.

•

Continues Moore’s law, with the same density improvement rate as previous generations.

•

Record transistor drive currents achieved by Intel’s unique strained silicon technology.

•

Cu and low-k ILD interconnect with superior RC performance.

•

Excellent yield demonstrated on 70 Mb SRAM, with 0.57 µm2

SRAM cell size and low voltage operation.

•

Microprocessor prototypes have been fabricated. The

process will be ready for high volume manufacturing in 2005, two years after the 90nm technology.

(29)

Acknowledgments

• The authors gratefully acknowledge the many

people in the following organizations at Intel

who contributed to this work:

Portland Technology Development

¾

Sort Test Technology Development

¾

Quality and Reliability Engineering

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For further information on Intel's silicon technology,

please visit the Silicon Showcase at

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High Performance 70

Mbit

SRAM

0.9 1.0 1.1 1.2 1.3 1.4 1.5

Cycle Time (ns)

VD D (V) 0.2 0.62 FAIL PASS

3.43 GHz @ 1.2V

Demonstrated 3.43 GHz at 1.2V

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Defect Reduction Trend

130nm 130nm 90nm 65nm

200mm 300mm 300mm 300mm

2000 2001 2002 2003 2004 Defect

Density

(log scale) Two Years

65 nm yield on same improvement rate with 2 years offset 65 nm yield on same improvement rate with 2 years offset

(3)

65 nm Microprocessor Prototypes

Fabricated

Single Core Dual Core

65 nm process ready for

high volume manufacturing in 2005

(4)

Conclusion

•

An industry leading 65 nm logic technology is presented.

•

Continues Moore’s law, with the same density improvement rate as previous generations.

•

Record transistor drive currents achieved by Intel’s unique strained silicon technology.

•

Cu and low-k ILD interconnect with superior RC performance.

•

Excellent yield demonstrated on 70 Mb SRAM, with 0.57 µm2

SRAM cell size and low voltage operation.

•

Microprocessor prototypes have been fabricated. The

process will be ready for high volume manufacturing in 2005, two years after the 90nm technology.