DATA AND INSTRUCTION FORMATS, ADDRESSING METHODS AND MACHINE PROGRAMMING CONCEPTS (2)

HUMBOLDT-UNIVERSITÄT ZU BERLIN
INSTITUT FÜR INFORMATIK

Lecture 5

DATA AND INSTRUCTION FORMATS,
ADDRESSING METHODS
AND MACHINE PROGRAMMING
CONCEPTS (2)
Sommersemester 2002
Leitung: Prof. Dr. Miroslaw Malek
www.informatik.hu-berlin.de/rok/ca
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COMPUTER PROGRAMMING CONCEPTS
•

Choice of a language:
– machine language (uses 0‘s and 1‘s or hex, inconvenient and error
prone)
– assembly language (machine dependent but efficient)

– high-level language (convenient and universal)

•

Compiler/assembler and operating system in combination with
computer architecture (instruction set plus I/O capabilities)
are decisive factors with respect to computer performance

•

The most important advantages of knowing an assembly
langage:
– understanding how a computer really works
– learning how to debug programs
– being able to optimize the performance
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EXAMPLE OF AN INSTRUCTION EXECUTION
4-bit operation
field

6-bit source 6-bit destination
address field
address field

Op-code
15

src

dstn

12 11

6 5

ADD #R7, R3
0

General format

32

R3
PC = R7

R3

i

49
i+4

PC = R7

Autoincrement mode 010 (210): EA=[PC]=[R7] and increment PC=R7

i

add 2

i+2

R7

0

R3

17

i

add 2

i+2

i+4

R7

0

R3

17

i+4

Before instruction fetch

After instruction execution

CA - V - D&IF(2) - 3

EXAMPLE OF A SHORT PROGRAM EXECUTION
Main memory
16-bit word contents
address
A = 1150
B = 1152

1200 MOV
1202
1204 ADD
1206
1208 MOV
1210
1212

1) R0 = 317

317
- 193

2) R0 = 124

6

R7
- 54

0

R0

EA = X + PC = -54 + 1204 = 1150

6

R7
- 56

0

R0

0

R6
988

6

R7

MOV A, R0
ADD B, R0
MOV R0, C

HALT

HALT

Assembly language version of program
Mode “6“ - Relative index
addressing
EA=X + [PC]=X + [R7 ]

C = 2200

124
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Example of an stw (storeword) instruction execution
(Power PC)
6 bit
Opcode

5 bit
Source register

5 bit
Sourceaddress A

Offset

(a) G en eral format

Autoincrement mode stw
stw rS, d(rA) , where rS (Source) and rA (Destination) are registers and d is an offset

The contents of rS are stored into the word in memory addressed by EA, where
EA=(rA)+d.
Binary representation of mnemonic stw: 100100
Decimal representation of mnemonic stw: 36
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I/O PROGRAMMING (I)
I/O BUS
TERMINAL

CPU

TTYIN

8

10 Op./s

CIN
Keyboard

TTYOUT
COUT
Monitor

Big Problem:
Matching
Speeds

e.g., 10 - 100 Characters/sec.

TTYIN

8 bit buffer register associated with a keyboard

TTYOUT

8 bit buffer register associated with a monitor

CIN, COUT

control flags

CIN = 1

informs CPU that a valid character is in TTYIN

COUT= 1

informs CPU that it can transfer a valid character to TTYOUT

MOVB TTYIN, R1

input operation

MOVB R1, TTYOUT output operation
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I/O PROGRAMMING (II)
MOV

#LOC,R0

READ: TSTB KBSTATUS
BPL
READ
MOVB TTYIN,@R0
ECHOBACK: TSTB
BPL

PRSTATUS
ECHOBACK

Initialize pointer register R0 to contain the address of
the first location of the area in main memory where
the characters are to be loaded.
Wait for a character to be entered into the keyboard
buffer register TTYIN.
Transfer the character from into the main memory
(this clears CIN to 0).
Wait for the monitor to become ready.

MOVB @R0,TTYOUT Move the character just read the monitor buffer
register TTYOUT for printing (this clears COUT to
0).
CMPB (R0)+,#CR
BNE
READ
HALT

Check to see if the character just read is "carriage
return” (CR). If it is not CR, branch back and read
another character, otherwise stop. The pointer
register R0 is incremented , anticipating that another
character will be read.
CA - V - D&IF(2) - 7

TYPE OF ARCHITECTURES
•
•
•
•
•
•

STACK ARCHITECTURES
REGISTER-REGISTER ARCHITECTURES
REGISTER-STORAGE ARCHITECTURES
STORAGE-STORAGE ARCHITECTURES
TAGGED ARCHITECTURES
TRADEOFFS AMONG STACK, REGISTER AND STORAGE
ARCHITECTURES
–
–
–
–
–
–

PERFORMANCE
EFFICIENCY
DESIGN COMPLEXITY
EASE OF PROGRAMMING
EASE OF PARAMETER PASSING AND SUBROUTINE CALLS
RECURSION

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A STACK IN THE MAIN MEMORY
0
Stack
Pointer
Register

.
.
.
Ri

The Stack

-28
17
739

Current
Top
Element

.
.
43
.
.
M–1

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Bottom
Element

EXAMPLES OF STACK OPERATIONS
MOV
MOV

R1

R1

-28

.

-28

(push)
(pop)

17

R1

739

-11
739

.

17

.

Stack
739

.

.

.

.

.

.

.

.

.

.

.

.

.

43
Newitem

R1

19

17
739

NEWITEM,- (R1)
(R1)+,TOPITEM

19

Topitem
(a) Initial contents of stack

43
Newitem

43

19

Topitem

43

Newitem

19

Newitem

Topitem

-28

Topitem

(b) After push from
NEWITEM

c) After pop
into TOPITEM

Notice (a) => (b), (a) => (c), (a) => (d)

CA - V - D&IF(2) - 10

19

d) After executing
ADD (R1)+, @R1

STACK MACHINES (1)
•
•
•
•
•
•
•

Most instructions manipulate the top few data items (mostly top
2) of a pushdown stack
Additional instructions are provided to move data between
memory and top of stack
Top few items of the stack (2 to 8 items or more) are kept in the
CPU
Instructions manipulate the top of the stack implicitly
Ideal for evaluating expressions (stack holds intermediate
results)
Were thought to be a good match for high level languages
Awkward:
– stack becomes very slow if it grows beyond CPU local storage
– no simple way to get data from ‘middle of stack‘

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STACK MACHINES (2)
•

Binary arithmetic and logic operations:
– operands: top 2 items on stack
– operands are removed from stack
– result is placed on top of stack

•

Unary arithmetic and logic operations:
– operand: top item on the stack
– operand is replaced by result of operation

•

Data move operations:
– push: place memory data on top of stack
– pop: move top of stack to memory
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STACK MACHINES - SAMPLE PROGRAM
•

We evaluate our favorite expression(y ← ax2+ bx+c) ; we use a
hypothetical assembly language (as usual)
push
push
dup
mult
mult
push
push
mult
push
add
add
pop

a
x

b
x
c

y

; tos: a
; tos: a x
; tos: a x x
; tos: a x2
; tos: a x2
; tos: a x2 b
; tos: a x2 b x
; tos: a x2 bx
; tos: a x2 bx c
; tos: a x2 bx+c
; tos: a x2+bx+c
; y