56. DRILL QUESTION

B 9-56. DRILL QUESTION

True or false:

(a) A device connected to a data bus should have tristate outputs. (b) Bus contention occurs when more than one device takes data from

the bus.

P ROBLEMS

(c) Larger units of data can be transferred over an eight-line data bus than over a four-line data bus.

(d) A bus driver IC generally has a high output impedance.

(e) Bidirectional registers and buffers have common I/O lines. 9-57.*For the bus arrangement of Figure 9-44, describe the input signal re-

quirements for simultaneously transferring the contents of register C to both of the other registers.

9-58. Assume that the registers in Figure 9-44 are initially [A] = 1011, [B] = 1000, and [C] = 0111 . The signals in Figure 9-80 are applied to the register inputs.

(a) Determine the contents of each register at times t 1 , t 2 , t 3 , and . t 4 (b) Describe what would happen if IE A were LOW when the third

clock pulse occurred.

FIGURE 9-80 Problems 9-58 and 9-59.

9-59. Assume the same initial conditions of Problem 9-58, and sketch the

signal on DB 3 for the waveforms of Figure 9-80.

9-60. Figure 9-81 shows two more devices that are to be added to the data bus of Figure 9-44. One is a set of buffered switches that can be used to enter data manually into any of the bus registers. The other device is an output register that is used to latch any data that are on the bus during a data transfer operation and display them on a set of LEDs.

(a) Assume that all registers contain 0000. Outline the sequence of operations needed to load the registers with the following data from the switches: [A] = 1011, [B] = 0001, [C] = 1110 .

(b) What will the state of the LEDs be at the end of this sequence?

C 9-61. Now that the circuitry of Figure 9-81 has been added to Figure 9-44,

a total of five devices are connected to the data bus. The circuit in Figure 9-82(a) will now be used to generate the enable signals needed to perform the different data transfers over the data bus. It uses a 74HC139 chip that contains two identical independent 1-of-4 decoders with an active-LOW enable. The top decoder is used to se- lect the device that will put data on the data bus (output select), and the bottom decoder is used to select the device that is to take the data from the data bus (input select). Assume that the decoder out- puts are connected to the corresponding enable inputs of the devices tied to the data bus. Also assume that all registers initially

C HAPTER 9/ MSI L OGIC C IRCUITS

FIGURE 9-81 Problems

+5 V

Data bus

9-60, 9-61, and 9-62.

from Fig. 9-44

(from Fig. 9-44)

FIGURE 9-82 Problem

To Figs.

9-61.

74HC139

9-44, 9-81

CLOCK O 0 IE A t

(a)

(b)

contain 0000 at time t 0 , and the switches are in the positions shown

in Figure 9-81.

(a)*Determine the contents of each register at times t 1 , t 2 , and t 3 in re-

sponse to the waveforms in Figure 9-82(b). (b) Can bus contention ever occur with this circuit? Explain. 9-62. Show how a 74HC541 (Figure 9-47) can be used in the circuit of

Figure 9-81.