Index of /intel-research/silicon Paolo M2S2 0902
Attacking the Red Brick Walls of the
International Technology Roadmap
for Semiconductors
(ITRS)
Dr. Paolo Gargini
Chairman ITRS
2001 Edition
M2 S2
P.Gargini
Sept-23--2002
What is the ITRS?
• A consensus reference document with a 15
year outlook on the requirements of the
semiconductor industry
– Provides a reference document for Equipment,
Materials and Software Suppliers on the Needs of the
Semiconductor Industry and on Possible Solutions
– Provides a reference document for the researchers on
the challenges of the semiconductor industry in the out
years
M2 S2
P.Gargini
Technology Hierarchy
Example:
p
• aReduce
Signal Propagation Delay of
m
d
a
Interconnections
o
• Technology Needs
R
y
g
o
l
o
n
h Solutions
c
• ePossible
T
in
a
m
o
D
• Metal Potential Solution: Cu Metal
Dielectric Potential Solution: Low K
Dielectric
ion
t
a
t
en
m
e
l
p
m
I
y
• Detailed g
Solutions
•
o
l
o
n
h
c
e
T• Implementation
in
a
•
m
o
D
Use: Cu CVD Seed Layer + Cu
Plating+ CMP+Low K CVD
Establish Supplier Infrastructure
M2 S2
P.Gargini
Roadmap Editions
2002ITRS
Update
http://public.itrs.net
2001 Edition
1997NTRS
2001ITRS
Europe
Japan
1994NTRS
2000ITRS
Update
Korea
1992NTRS
Taiwan
1999ITRS
USA
1991
Micro Tech 2000
Workshop Report
1998ITRS
Update
M2 S2
P.Gargini
International and Domestic Timing
Time
Region A
Region B
1Q
Domestic
Domestic
Europe
2Q
Domestic
Domestic
USA
3Q
4Q
2001
Korea
USA
Japan 1999, 2002
Taiwan 2000
M2 S2
P. Gargini
P.Gargini
2002 ITRS Update:
December 4th, 2002
M2 S2
P.Gargini
Mission of ITRS
IRC
•Coordination
among
Associations
Technology Needs
Potential Solutions
ESIA
TWG
JEITA
（STRJ)
KSIA
•Policy
•Goals
•Schedule
•Coordination
among ITWGs
in
TWG
near & long term
etc
TWG
TWG
SIA
TSIA
ITWG
ITWG
FEP
Test
Design
TWG
M2 S2
P.Gargini
International Technology Working
Groups
ITWG
•
•
•
•
•
•
•
•
Cross ITWG
Assembly & Packaging
Design
Factory Integration
Front End Process
Interconnect
Lithography
PIDS, Emerging Devices
Test
• Environment, Safety,
Health
• Metrology
• Modeling and Simulation
• Yield Enhancement
* PIDS=Process Integration and Device Structures
M2 S2
P.Gargini
ITRS Framework
Interconnect
Design
Factory Integration
ESH
Yield Enhancement
Metrology Modeling
PIDS
Lithography
FEP Isolation
Source / Drain
- Extension
Channel
Assembly
QFP
Test
BGA
PGA
2001 Edition
Contacts
Printed Wiring Board
Wells
Starting Material
M2 S2
P.Gargini
Chapters of ITRS 2001
Glossary
ORTC
http://public.itrs.net
12 ITWGs : Design to Modeling & Simulation
- Scope
- Difficult Challenges
- Technology Requirement
- Potential Solutions
System Drivers
Difficult Challenges
Grand Challenges
Introduction
M2 S2
P.Gargini
Contact Information for the ITRS
¾For general questions or information regarding ITRS publications and
public forums visit the ITRS web site http://public.itrs.net [note that
there is no “www” in our web site address.].
To order a Roadmap through email, use the ITRS email address
[email protected] or access the ITRS web site.
¾Other questions or comments?
call
Linda Wilson
ITRS Information Manager
512.356.3605
Sarah Mangum
ITRS Webmaster
512.356.3558
2001 ITRS Book and CD sales
•$25 for CDs, $35 for CDs shipped outside the U.S.A
•$50 for Books, $65 for ITRS books shipped outside the U.S.A.
¾Back issues of the ITRS are available while quantities last (1999, 1997, 1994) !!
M2 S2
P.Gargini
Composition of the Technology
Working Group (ITWG) in 2001
TWG Members by Regions TWG Members by Affiliations
Korea
64
8%
Japan
222
26%
USA
324
Research Inst. /
Other
Consortia /
1% 10
University
193 23%
39%
54%
22%
19%
Taiwan
161
8%
Europe
68
Equipment /
Materials
Suppliers 185
M2 S2
Chip Makers
445
P.Gargini
Applied Materials
KLA-Tencor
Tokyo Electron America
SEMI
Novellus Systems
Wacker Siltronic Corp.
Agilent Technologies
Winbond Electronics Corp.
Axcelis Technologies, Inc.
Komatsu Silicon
MEMC
Canon Inc.
Dow Chemical
Micronix
ASM Lithography
Nikon Corporation
Photronics, Inc.
Shipley Company, Inc.
Episil Technologies
Metrology Edge
Therma-Wave
Oki Electric Ind. Co., Ltd.
DuPont Company
Silicon Valley Group, Inc
ION Systems
M+W Zandar
Nanya Technology Co.
Compaq Computer Corp
Asyst Technologies, Inc.
Sumitomo Sitix Corp.
Varian
Air Products & Chemicals
Etec Systems, Inc.
n-Line Corporation
K&S
THANK YOU!!!
Advantest
LogicVision
Teradyne
Air Liquide
Metara, Inc.
Millipore
M2 S2
CamLine
Ebara
Rohm
Sanyo
FSI International
Genus
Ibis Technology
Okmetic Ltd.
SiGen
Soitec
Tokin Corp
BOC Edwards
Nortel Networks
Cadence
Intransa
UBC
ATMI
Cabot Corporation
E4 Technologies
Praxair, Inc.
SONY
URS Corporation
P.Gargini
DETAILED SOLUTIONS
And
IMPLEMENTATION
M2 S2
P.Gargini
From Strategy to Implementation
ITRS
Technology Needs
Possible Solutions
Consortia
Researchers
Detailed Solutions
Suppliers
Suppliers
IC Makers
Implementation
M2 S2
OEM
P.Gargini
Use of ITRS as a Global Planning Tool
Internal
R&D
Consortia
External
R&D
Suppliers
M2 S2
SRC
Natl Lab
ISMT
IMEC
LETI
MEDEA
MIRAI
ASET
Selete
P.Gargini
Consortia Locations
JR
MARCO
i
IRAI
PR
M2 S2
P.Gargini
M2 S2
P.Gargini
ITRS GUIDING
PRINCIPLE
M2 S2
P.Gargini
RR
Transistors Shipped per
Year
1018
1017
1016
Units
1015
1014
1013
1012
1011
1010
109
'68 '70
®
'72 '74 '76 '78 '80 '82
'84 '86
'88 '90 '92 '94 '96 '98 '00 '02
Source: WSTS/Dataquest/Intel, 8/02
M2 S2
P.Gargini
R
R
Worldwide Semiconductor
Revenues
1000
$B
100
10
1
'68
'68 ’70
’70 '72 '74 '76
'76 '78 '80
'80 '82 '84 '86 '88
'88 ’90
’90 '92 '94 '96 '98 '00 '02
®
Source: Intel/WSTS, 8/02
M2 S2
P.Gargini
RR
Average Transistor Price
by Year
10
$
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
®
Source: WSTS/Dataquest/Intel, 8/02
M2 S2
P.Gargini
ITRS GUIDING PRINCIPLE
50% TRANSISTOR AREA READUCION
GENERATION TO GENERATION
=> 30% LINEAR FEATURE REDUCTION
50%
M2 S2
P.Gargini
Intel’s Process Technology
Basic Feature Size in microns
0.8µ
0.6µ
0.35µ
Pentium®
Processor
0.25µ
0.18µ
0.13µ
In 26 years, the number of
transistors on a chip has
increased more than 18,000
times, from 2,300 on the
4004 in 1971 to 42 million on
the Pentium® 4 processor.
Pentium® Pro
Processor
Pentium® II
Processor
Pentium® III
Processor
Pentium® 4
Processor
M2 S2
P.Gargini
DEFINITIONS
And
TIMING
M2 S2
P.Gargini
Technology Node Definition
One half of the smallest pitch in the technology,
Typically represented by the first metal layer
of DRAM
M2 S2
P.Gargini
Half Pitch (=Pitch/2) Definition
Poly
Pitch
Metal
Pitch
(Typical
MPU/ASIC)
(Typical
DRAM)
M2 S2
P.Gargini
MOS Transistor Scaling
(1974 to present)
S=0.7
[0.5x per 2 nodes]
Pitch
M2 S2
Gate
P.Gargini
1994 NTRS Roadmap
Year:
95 96 97 98 99 00 01 02 03 04 05 06 07
NTRS’94
1/2 pitch* 350
250
180
130
100
* Dimensions for minimum half pitch and isolated line in nm
Source: National Technology Roadmap for Semiconductors
M2 S2
ITRS
10
P.Gargini
P.Gargini
M2 S2
P.Gargini
WAS
Technology Nodes (nm)
X
IS
Actual
100
130
0.7
91
90
70
90
0.7
64
65
50
65
0.7
45
45
35
45
0.7
31
32
25
32
0.7
22
22
IRC
M2 S2
P.Gargini
1999 ITRS Timing
Year of Production
DRAM ½ Pitch (nm)
1999 2000
2001
180
2002
2003 2004
2005
130
100
180 165 150 130
120 110 100
100
85-90
80 70
65
65
180
160
145 130
115
150
130
120 110
100
MPU Gate Length (nm)
140
120 100
MPU / ASIC ½ Pitch (nm)
230
210
ASIC Gate Length (nm)
180
165
-1
2001 ITRS Timing
-2
Year of Production
DRAM ½ Pitch
2001
2002
2003
130
115
100
MPU/ASIC ½ Pitch
150
130
107
MPU Pr Gate Length
90
75
MPU Ph Gate Length
-4 65
53
65
45
M2 S2
-2
2004
2005
2006
2007
90
90
80
70
80
70
65
65
53
45
40
35
37
32
28
25
P.Gargini
Production Ramp-up Model and Technology Node
Development
200K
Production
10M
20K
1M
100K
2K
Alpha
Tool
Beta Production
Tool
Tool
10K
1K
First Two
Companies
Reaching
Production
First
Conf.
Papers
-24
200
-12
Source: 2001 ITRS - Exec. Summary
0
Months
M2 S2
12
20
2
Volume (Wafers/Month)
Volume (Parts/Month)
100M
24
P.Gargini
3-year cycle
(1977~1995)
Innovation
1.4X
3-year cycle
4X/3 Years
Technology
2X
Manufacturing
1.4X
M2 S2
P.Gargini
DRAM Chip Size Trend
10,000
1T
Chip Size (mm2)
1.4X/3-years
1000
1G
100
10
1980
800mm2 Max Litho Field
(4X)
300mm2
150mm2
75mm2
38mm2
~2X die growth in 6 years
1M
1990
2000
M2 S2
2010
2020
P.Gargini
3-year -> 2-year cycle
(~1995-2010)
Innovation
1.4X
3-year cycle
4X/3 Years
Technology
2X ->2.8X
1.4X
M2 S2
Manufacturing
1.4X ->1.0X
P.Gargini
DRAM Chip Size Trend
10,000
1T
Chip Size (mm2)
1.4X/3-years
1000
800mm2
1G
300mm2
100
10
1980
150mm2
75mm2
38mm2
~2X die growth in 6 years
1M
1990
2000
M2 S2
2010
2020
P.Gargini
TABLES
And
WALLS
M2 S2
P.Gargini
Table’s Structure
• All tables are divided in two parts:
– Near Term
• Six year outlook (e.g., 2001-2007)
• All values are reported on a yearly basis
– Long Term
• Nine year outlook (e.g., 2008-2016)
• Values are reported at 3 year interval
M2 S2
P.Gargini
Tables’ Color Scheme
Solutions Exist
White
Solutions Being Pursued
Yellow
No Known Solutions
Red
• A new category will be introduced starting with
2002ITRS Update
M2 S2
P.Gargini
A Rainbow of Tables
Table46b MPUInterconnect TechnologyRequirements—LongTerm
DRAM Short Term Requirements
Y EA R OF INTRODUCTION
“T ECHNOLOGY NODE”
1999
180 nm
2000
2001
2002
130 nm
2003
2004
2005
100 nm
100
180
165
150
130
120
110
Number of metal levels
3
3
3
3-4
4
4
Contact A/R – s tacked
capacitor
6.3
6.7
7.1
7.5
8.0
Local wiring pitch (nm) noncontacted
360
330
300
260
240
Specific contact resistance
6E-7
DRAM pitch
7E-9
Specific via resistance
180
Interlevel metal insulator -
165
2 MPU Gate Lengtheffective
(nm) dielectric cons140
tant
120
(κ)
3 MPU / ASIC ½ (nm)
230
180
4 ASIC Gate Length (nm)
5 Minimumlogic V (V) (desktop)
Solutions Exist
dd
150
4.1
130
100
85
210
180
165
150
120
4.1
110
4.1
70
65
160
145
130
115
130
120
110
100
32
80
55
3E-7
[4]
2E-7Length (nm)
ASIC Gate
70
50
2E-9
[5]
Minimum logic Vdd (V) (desktop)
0.6–0.9
0.5–0.6
[6]
Tox equivalent (nm)
210
3. 0 - 4.1
3. 0 - 4.1
1E-9
0.6–0.8
40
80
YEAR
5
9
11
Gate delay metric CV/I (ps) high-performance
10 Percent static power reduction necessary due to
innovative circuit/systemdesign
7
8
10
13
16
20 ground
planes/capacitors
MGATE
(For minimum
L device)
6-7
6–7 low power
7
Jmax (A/cm2)—wire (at 105°C)
9.4
8.6
7.3
6.9
6.1
5.7 Imax (mA)—via (at 105°C)
Local wiring pitch (nm)
0
MGATE
7–8
8
8
8–
2
5.6 2
95
1.3E6
2
33
48
55
71
77
81
M&A ½
Local wiring A/R (for Cu)
DRIVER
YEAR 490/230 490/23 490/230 490/230
2008
2011
2014
11 Nominal I at 25 °C(µA/µm)
490/23 490/230 490/230
GATEdishing (nm), 5% × height
CuAlocal
on
70 nm
50 nm
35 nm
T ECHNOLOGY N ODE 0
0
[NMOS/PMOS] lowpower
Intermediate wiring pitch (nm)
70 13
[1] DRAM ½ Pitch (nm)
12 Maximum
5
Ioff at 25 °C(pA/µm)
[2] MPU
Length (nm)
(For minimum
Ldevice)Gate
lowpower
7
8
10
13 Gate delay
CV/I /(ps)
lowpower
18
[3]metric
MPU
ASIC
½ Pitch (nm)
16
13
11.2 8010.7
16
50
35
20 Intermediate wiring A/R (Al)
8.8
8.2
55 Cu intermediate40
dishing (nm),
A GATE
32 Intermediate wiring
22 dual damascene A/R
45
36
55
Minimum logic Vdd (V) (desktop)
off
Solutions
Being Pursued
(For minimum L device)
high-performance
[9] Gate delay metric CV/I (ps) high-performance
[10] Percent static power reduction necessary due to
innovative circuit/system design
[11] Nominal Ion at 25 °C (µA/µm) [NMOS/PMOS] low
power
65 70 80
2.1
0.29
250.27
330 0.02–0.028
295
2.2
**
1.4
1.4
1.5
1.5
1.6
1.6
18
640
16
575
15
520
14
465
13
420
12
375
2.2
2.3
2.4
2.5
2.6
**
2.0/2.1
2.1/2.1
2.2/2.1
2.2/2.1
2.2/2.2
2.3/2.2
64
60
57
51
46
43
41
64
60
57
51
46
43
41
11
34
**
2.4/
85
NoKnown Solutions
3.7
91
490/230
40
[13] Gate delay metric CV/I (ps) low power
[14] Percent static power reduction necessary due to
innovative circuit/system design
5.6
95
[16] S/D extension junction depth, nominal (µm)
2.1
0.6–0.9
[12] Maximum I at 25 °C (pA/µm)
off
(For minimum L device) low power
[15] VT 3s variation (±mV) (For minimum L device)
1.1E6
2
25
0.02–0.028
1050
945
850
765
690
620
56
2
2.1
2.2
2.3
2.4
**
2.2/2.4
2.3/2.6
2.4/2.7
2.5/2.7
2.6/2.8
2.7/2.8
**
116
109
102
95
90
84
76
3.3
3.3
3.3
3.3
3.3
**
**
2.7/
15 micron wide wire, 10% × height
2.6 Conductor effective
2.4 resistivity
(µΩ-cm) Al wiring
M Gate
97
98
Conductor effective resistivity M & A ½
(µΩ-cm) Cu wiring*
A Gate
490/230
490/230
Barrier/cladding thickness
(for Cu wiring) (nm)***
A Gate
80 Interlevel metal160
insulator
17
Solutions
Exist
17
0.01–0.014
4
2.1E6
3.7E6
4.6E6
0.18
0.16
0.11
1999
180 nm
0.5–0.6
230
M Gate
20001.9 20012.1 20022.3 2003
130 nm
9
7
5
210 240 180165 160115 145
MPU gate
length
(nm)
Interm
ediatewiring
dual damasceneA/R(Cu140
wire/via)
M Gate
750/350
Number of metal levels
1202.5/2.3 1002.7/2.4 852.9/2.5
6-7
6–7
0
0
7
30
22
2.6
97
DRAM
18
r effectiv
resistiv
A eGate
160Conducto
Intermediate
wiring
pitch
(nm) ity(µΩ-cm)Cuwiring
640
16
575
1.8
Intermediate
wiring A/Rthickness
(Al) (nm)
Barrier/cladding
2.3
0
Contact A/R – stacked capacitor
2.2
wiring
pitch
(nm)
Intermediate
wiring
dualnon-contacted
damascene A/R
2.0/2.1
3.7
Interlev
el metal
insulato
r—effectivedielectric
constant (κ)2.1/2.11.5
2.4
130
11
70
65
8
8
8–
2
2
13 4
420
10.5
14
465
International Technology Roadmap
for Semiconductors
(ITRS)
Dr. Paolo Gargini
Chairman ITRS
2001 Edition
M2 S2
P.Gargini
Sept-23--2002
What is the ITRS?
• A consensus reference document with a 15
year outlook on the requirements of the
semiconductor industry
– Provides a reference document for Equipment,
Materials and Software Suppliers on the Needs of the
Semiconductor Industry and on Possible Solutions
– Provides a reference document for the researchers on
the challenges of the semiconductor industry in the out
years
M2 S2
P.Gargini
Technology Hierarchy
Example:
p
• aReduce
Signal Propagation Delay of
m
d
a
Interconnections
o
• Technology Needs
R
y
g
o
l
o
n
h Solutions
c
• ePossible
T
in
a
m
o
D
• Metal Potential Solution: Cu Metal
Dielectric Potential Solution: Low K
Dielectric
ion
t
a
t
en
m
e
l
p
m
I
y
• Detailed g
Solutions
•
o
l
o
n
h
c
e
T• Implementation
in
a
•
m
o
D
Use: Cu CVD Seed Layer + Cu
Plating+ CMP+Low K CVD
Establish Supplier Infrastructure
M2 S2
P.Gargini
Roadmap Editions
2002ITRS
Update
http://public.itrs.net
2001 Edition
1997NTRS
2001ITRS
Europe
Japan
1994NTRS
2000ITRS
Update
Korea
1992NTRS
Taiwan
1999ITRS
USA
1991
Micro Tech 2000
Workshop Report
1998ITRS
Update
M2 S2
P.Gargini
International and Domestic Timing
Time
Region A
Region B
1Q
Domestic
Domestic
Europe
2Q
Domestic
Domestic
USA
3Q
4Q
2001
Korea
USA
Japan 1999, 2002
Taiwan 2000
M2 S2
P. Gargini
P.Gargini
2002 ITRS Update:
December 4th, 2002
M2 S2
P.Gargini
Mission of ITRS
IRC
•Coordination
among
Associations
Technology Needs
Potential Solutions
ESIA
TWG
JEITA
（STRJ)
KSIA
•Policy
•Goals
•Schedule
•Coordination
among ITWGs
in
TWG
near & long term
etc
TWG
TWG
SIA
TSIA
ITWG
ITWG
FEP
Test
Design
TWG
M2 S2
P.Gargini
International Technology Working
Groups
ITWG
•
•
•
•
•
•
•
•
Cross ITWG
Assembly & Packaging
Design
Factory Integration
Front End Process
Interconnect
Lithography
PIDS, Emerging Devices
Test
• Environment, Safety,
Health
• Metrology
• Modeling and Simulation
• Yield Enhancement
* PIDS=Process Integration and Device Structures
M2 S2
P.Gargini
ITRS Framework
Interconnect
Design
Factory Integration
ESH
Yield Enhancement
Metrology Modeling
PIDS
Lithography
FEP Isolation
Source / Drain
- Extension
Channel
Assembly
QFP
Test
BGA
PGA
2001 Edition
Contacts
Printed Wiring Board
Wells
Starting Material
M2 S2
P.Gargini
Chapters of ITRS 2001
Glossary
ORTC
http://public.itrs.net
12 ITWGs : Design to Modeling & Simulation
- Scope
- Difficult Challenges
- Technology Requirement
- Potential Solutions
System Drivers
Difficult Challenges
Grand Challenges
Introduction
M2 S2
P.Gargini
Contact Information for the ITRS
¾For general questions or information regarding ITRS publications and
public forums visit the ITRS web site http://public.itrs.net [note that
there is no “www” in our web site address.].
To order a Roadmap through email, use the ITRS email address
[email protected] or access the ITRS web site.
¾Other questions or comments?
call
Linda Wilson
ITRS Information Manager
512.356.3605
Sarah Mangum
ITRS Webmaster
512.356.3558
2001 ITRS Book and CD sales
•$25 for CDs, $35 for CDs shipped outside the U.S.A
•$50 for Books, $65 for ITRS books shipped outside the U.S.A.
¾Back issues of the ITRS are available while quantities last (1999, 1997, 1994) !!
M2 S2
P.Gargini
Composition of the Technology
Working Group (ITWG) in 2001
TWG Members by Regions TWG Members by Affiliations
Korea
64
8%
Japan
222
26%
USA
324
Research Inst. /
Other
Consortia /
1% 10
University
193 23%
39%
54%
22%
19%
Taiwan
161
8%
Europe
68
Equipment /
Materials
Suppliers 185
M2 S2
Chip Makers
445
P.Gargini
Applied Materials
KLA-Tencor
Tokyo Electron America
SEMI
Novellus Systems
Wacker Siltronic Corp.
Agilent Technologies
Winbond Electronics Corp.
Axcelis Technologies, Inc.
Komatsu Silicon
MEMC
Canon Inc.
Dow Chemical
Micronix
ASM Lithography
Nikon Corporation
Photronics, Inc.
Shipley Company, Inc.
Episil Technologies
Metrology Edge
Therma-Wave
Oki Electric Ind. Co., Ltd.
DuPont Company
Silicon Valley Group, Inc
ION Systems
M+W Zandar
Nanya Technology Co.
Compaq Computer Corp
Asyst Technologies, Inc.
Sumitomo Sitix Corp.
Varian
Air Products & Chemicals
Etec Systems, Inc.
n-Line Corporation
K&S
THANK YOU!!!
Advantest
LogicVision
Teradyne
Air Liquide
Metara, Inc.
Millipore
M2 S2
CamLine
Ebara
Rohm
Sanyo
FSI International
Genus
Ibis Technology
Okmetic Ltd.
SiGen
Soitec
Tokin Corp
BOC Edwards
Nortel Networks
Cadence
Intransa
UBC
ATMI
Cabot Corporation
E4 Technologies
Praxair, Inc.
SONY
URS Corporation
P.Gargini
DETAILED SOLUTIONS
And
IMPLEMENTATION
M2 S2
P.Gargini
From Strategy to Implementation
ITRS
Technology Needs
Possible Solutions
Consortia
Researchers
Detailed Solutions
Suppliers
Suppliers
IC Makers
Implementation
M2 S2
OEM
P.Gargini
Use of ITRS as a Global Planning Tool
Internal
R&D
Consortia
External
R&D
Suppliers
M2 S2
SRC
Natl Lab
ISMT
IMEC
LETI
MEDEA
MIRAI
ASET
Selete
P.Gargini
Consortia Locations
JR
MARCO
i
IRAI
PR
M2 S2
P.Gargini
M2 S2
P.Gargini
ITRS GUIDING
PRINCIPLE
M2 S2
P.Gargini
RR
Transistors Shipped per
Year
1018
1017
1016
Units
1015
1014
1013
1012
1011
1010
109
'68 '70
®
'72 '74 '76 '78 '80 '82
'84 '86
'88 '90 '92 '94 '96 '98 '00 '02
Source: WSTS/Dataquest/Intel, 8/02
M2 S2
P.Gargini
R
R
Worldwide Semiconductor
Revenues
1000
$B
100
10
1
'68
'68 ’70
’70 '72 '74 '76
'76 '78 '80
'80 '82 '84 '86 '88
'88 ’90
’90 '92 '94 '96 '98 '00 '02
®
Source: Intel/WSTS, 8/02
M2 S2
P.Gargini
RR
Average Transistor Price
by Year
10
$
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
®
Source: WSTS/Dataquest/Intel, 8/02
M2 S2
P.Gargini
ITRS GUIDING PRINCIPLE
50% TRANSISTOR AREA READUCION
GENERATION TO GENERATION
=> 30% LINEAR FEATURE REDUCTION
50%
M2 S2
P.Gargini
Intel’s Process Technology
Basic Feature Size in microns
0.8µ
0.6µ
0.35µ
Pentium®
Processor
0.25µ
0.18µ
0.13µ
In 26 years, the number of
transistors on a chip has
increased more than 18,000
times, from 2,300 on the
4004 in 1971 to 42 million on
the Pentium® 4 processor.
Pentium® Pro
Processor
Pentium® II
Processor
Pentium® III
Processor
Pentium® 4
Processor
M2 S2
P.Gargini
DEFINITIONS
And
TIMING
M2 S2
P.Gargini
Technology Node Definition
One half of the smallest pitch in the technology,
Typically represented by the first metal layer
of DRAM
M2 S2
P.Gargini
Half Pitch (=Pitch/2) Definition
Poly
Pitch
Metal
Pitch
(Typical
MPU/ASIC)
(Typical
DRAM)
M2 S2
P.Gargini
MOS Transistor Scaling
(1974 to present)
S=0.7
[0.5x per 2 nodes]
Pitch
M2 S2
Gate
P.Gargini
1994 NTRS Roadmap
Year:
95 96 97 98 99 00 01 02 03 04 05 06 07
NTRS’94
1/2 pitch* 350
250
180
130
100
* Dimensions for minimum half pitch and isolated line in nm
Source: National Technology Roadmap for Semiconductors
M2 S2
ITRS
10
P.Gargini
P.Gargini
M2 S2
P.Gargini
WAS
Technology Nodes (nm)
X
IS
Actual
100
130
0.7
91
90
70
90
0.7
64
65
50
65
0.7
45
45
35
45
0.7
31
32
25
32
0.7
22
22
IRC
M2 S2
P.Gargini
1999 ITRS Timing
Year of Production
DRAM ½ Pitch (nm)
1999 2000
2001
180
2002
2003 2004
2005
130
100
180 165 150 130
120 110 100
100
85-90
80 70
65
65
180
160
145 130
115
150
130
120 110
100
MPU Gate Length (nm)
140
120 100
MPU / ASIC ½ Pitch (nm)
230
210
ASIC Gate Length (nm)
180
165
-1
2001 ITRS Timing
-2
Year of Production
DRAM ½ Pitch
2001
2002
2003
130
115
100
MPU/ASIC ½ Pitch
150
130
107
MPU Pr Gate Length
90
75
MPU Ph Gate Length
-4 65
53
65
45
M2 S2
-2
2004
2005
2006
2007
90
90
80
70
80
70
65
65
53
45
40
35
37
32
28
25
P.Gargini
Production Ramp-up Model and Technology Node
Development
200K
Production
10M
20K
1M
100K
2K
Alpha
Tool
Beta Production
Tool
Tool
10K
1K
First Two
Companies
Reaching
Production
First
Conf.
Papers
-24
200
-12
Source: 2001 ITRS - Exec. Summary
0
Months
M2 S2
12
20
2
Volume (Wafers/Month)
Volume (Parts/Month)
100M
24
P.Gargini
3-year cycle
(1977~1995)
Innovation
1.4X
3-year cycle
4X/3 Years
Technology
2X
Manufacturing
1.4X
M2 S2
P.Gargini
DRAM Chip Size Trend
10,000
1T
Chip Size (mm2)
1.4X/3-years
1000
1G
100
10
1980
800mm2 Max Litho Field
(4X)
300mm2
150mm2
75mm2
38mm2
~2X die growth in 6 years
1M
1990
2000
M2 S2
2010
2020
P.Gargini
3-year -> 2-year cycle
(~1995-2010)
Innovation
1.4X
3-year cycle
4X/3 Years
Technology
2X ->2.8X
1.4X
M2 S2
Manufacturing
1.4X ->1.0X
P.Gargini
DRAM Chip Size Trend
10,000
1T
Chip Size (mm2)
1.4X/3-years
1000
800mm2
1G
300mm2
100
10
1980
150mm2
75mm2
38mm2
~2X die growth in 6 years
1M
1990
2000
M2 S2
2010
2020
P.Gargini
TABLES
And
WALLS
M2 S2
P.Gargini
Table’s Structure
• All tables are divided in two parts:
– Near Term
• Six year outlook (e.g., 2001-2007)
• All values are reported on a yearly basis
– Long Term
• Nine year outlook (e.g., 2008-2016)
• Values are reported at 3 year interval
M2 S2
P.Gargini
Tables’ Color Scheme
Solutions Exist
White
Solutions Being Pursued
Yellow
No Known Solutions
Red
• A new category will be introduced starting with
2002ITRS Update
M2 S2
P.Gargini
A Rainbow of Tables
Table46b MPUInterconnect TechnologyRequirements—LongTerm
DRAM Short Term Requirements
Y EA R OF INTRODUCTION
“T ECHNOLOGY NODE”
1999
180 nm
2000
2001
2002
130 nm
2003
2004
2005
100 nm
100
180
165
150
130
120
110
Number of metal levels
3
3
3
3-4
4
4
Contact A/R – s tacked
capacitor
6.3
6.7
7.1
7.5
8.0
Local wiring pitch (nm) noncontacted
360
330
300
260
240
Specific contact resistance
6E-7
DRAM pitch
7E-9
Specific via resistance
180
Interlevel metal insulator -
165
2 MPU Gate Lengtheffective
(nm) dielectric cons140
tant
120
(κ)
3 MPU / ASIC ½ (nm)
230
180
4 ASIC Gate Length (nm)
5 Minimumlogic V (V) (desktop)
Solutions Exist
dd
150
4.1
130
100
85
210
180
165
150
120
4.1
110
4.1
70
65
160
145
130
115
130
120
110
100
32
80
55
3E-7
[4]
2E-7Length (nm)
ASIC Gate
70
50
2E-9
[5]
Minimum logic Vdd (V) (desktop)
0.6–0.9
0.5–0.6
[6]
Tox equivalent (nm)
210
3. 0 - 4.1
3. 0 - 4.1
1E-9
0.6–0.8
40
80
YEAR
5
9
11
Gate delay metric CV/I (ps) high-performance
10 Percent static power reduction necessary due to
innovative circuit/systemdesign
7
8
10
13
16
20 ground
planes/capacitors
MGATE
(For minimum
L device)
6-7
6–7 low power
7
Jmax (A/cm2)—wire (at 105°C)
9.4
8.6
7.3
6.9
6.1
5.7 Imax (mA)—via (at 105°C)
Local wiring pitch (nm)
0
MGATE
7–8
8
8
8–
2
5.6 2
95
1.3E6
2
33
48
55
71
77
81
M&A ½
Local wiring A/R (for Cu)
DRIVER
YEAR 490/230 490/23 490/230 490/230
2008
2011
2014
11 Nominal I at 25 °C(µA/µm)
490/23 490/230 490/230
GATEdishing (nm), 5% × height
CuAlocal
on
70 nm
50 nm
35 nm
T ECHNOLOGY N ODE 0
0
[NMOS/PMOS] lowpower
Intermediate wiring pitch (nm)
70 13
[1] DRAM ½ Pitch (nm)
12 Maximum
5
Ioff at 25 °C(pA/µm)
[2] MPU
Length (nm)
(For minimum
Ldevice)Gate
lowpower
7
8
10
13 Gate delay
CV/I /(ps)
lowpower
18
[3]metric
MPU
ASIC
½ Pitch (nm)
16
13
11.2 8010.7
16
50
35
20 Intermediate wiring A/R (Al)
8.8
8.2
55 Cu intermediate40
dishing (nm),
A GATE
32 Intermediate wiring
22 dual damascene A/R
45
36
55
Minimum logic Vdd (V) (desktop)
off
Solutions
Being Pursued
(For minimum L device)
high-performance
[9] Gate delay metric CV/I (ps) high-performance
[10] Percent static power reduction necessary due to
innovative circuit/system design
[11] Nominal Ion at 25 °C (µA/µm) [NMOS/PMOS] low
power
65 70 80
2.1
0.29
250.27
330 0.02–0.028
295
2.2
**
1.4
1.4
1.5
1.5
1.6
1.6
18
640
16
575
15
520
14
465
13
420
12
375
2.2
2.3
2.4
2.5
2.6
**
2.0/2.1
2.1/2.1
2.2/2.1
2.2/2.1
2.2/2.2
2.3/2.2
64
60
57
51
46
43
41
64
60
57
51
46
43
41
11
34
**
2.4/
85
NoKnown Solutions
3.7
91
490/230
40
[13] Gate delay metric CV/I (ps) low power
[14] Percent static power reduction necessary due to
innovative circuit/system design
5.6
95
[16] S/D extension junction depth, nominal (µm)
2.1
0.6–0.9
[12] Maximum I at 25 °C (pA/µm)
off
(For minimum L device) low power
[15] VT 3s variation (±mV) (For minimum L device)
1.1E6
2
25
0.02–0.028
1050
945
850
765
690
620
56
2
2.1
2.2
2.3
2.4
**
2.2/2.4
2.3/2.6
2.4/2.7
2.5/2.7
2.6/2.8
2.7/2.8
**
116
109
102
95
90
84
76
3.3
3.3
3.3
3.3
3.3
**
**
2.7/
15 micron wide wire, 10% × height
2.6 Conductor effective
2.4 resistivity
(µΩ-cm) Al wiring
M Gate
97
98
Conductor effective resistivity M & A ½
(µΩ-cm) Cu wiring*
A Gate
490/230
490/230
Barrier/cladding thickness
(for Cu wiring) (nm)***
A Gate
80 Interlevel metal160
insulator
17
Solutions
Exist
17
0.01–0.014
4
2.1E6
3.7E6
4.6E6
0.18
0.16
0.11
1999
180 nm
0.5–0.6
230
M Gate
20001.9 20012.1 20022.3 2003
130 nm
9
7
5
210 240 180165 160115 145
MPU gate
length
(nm)
Interm
ediatewiring
dual damasceneA/R(Cu140
wire/via)
M Gate
750/350
Number of metal levels
1202.5/2.3 1002.7/2.4 852.9/2.5
6-7
6–7
0
0
7
30
22
2.6
97
DRAM
18
r effectiv
resistiv
A eGate
160Conducto
Intermediate
wiring
pitch
(nm) ity(µΩ-cm)Cuwiring
640
16
575
1.8
Intermediate
wiring A/Rthickness
(Al) (nm)
Barrier/cladding
2.3
0
Contact A/R – stacked capacitor
2.2
wiring
pitch
(nm)
Intermediate
wiring
dualnon-contacted
damascene A/R
2.0/2.1
3.7
Interlev
el metal
insulato
r—effectivedielectric
constant (κ)2.1/2.11.5
2.4
130
11
70
65
8
8
8–
2
2
13 4
420
10.5
14
465