Sunlin keynote IDF Berlin 043003
Silicon Integration
for Convergence
Sunlin Chou
Senior Vice President
General Manager
Technology and Manufacturing Group
April 2003
1
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
2
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
3
Computing + Communications Vision:
Data Anytime, Anywhere
Cellular: Voice + Data
@ the Office
Everywhere
Else
10/100/GbE
802.11b/a
@ Hotspots
@ Home
802.11b/a
Broadband
10/100
4
802.11b/a
Cellular
Silicon is the Engine
Converged
Computing and
Communications
Microprocessors
Drive convergence
with silicon integration
Memory
5
Silicon Scaling and Integration
Improve Performance, Power, Cost
Relative scale (log)
Scaling effects on transistors
1
Delay
Swi
C os t
tchi
ng e
ner
gy
0.1
0.01
0.001
1993 1995 1997 1999 2001 2003 2005
.5µm
.35µm
.25µm .18µm .13µm
Silicon scaling
Source: Intel
6
90nm
65nm
Cell Phones For Voice + Data
Mb
Flash Memory Density Growth in Japan
200
160
44K COLOR
RICH JAVA APPS.
MP3
PHOTOS
120
80
40
0
1998
VOICE ONLY
1999
PACKETIZED DATA
2000
256 COLOR
2001
4K COLOR
JAVA APPS.
Convergence increases silicon usage
Source: NEC, Intel
7
2002
Converged Cell Phone
Integration Opportunities
Communications
Computing
Memory
Signal
Signal
Radio
Processing
Radio(RF)
(RF) Processing
Rx
Rx
Tx
Tx
PA
PA
DSP
DSP
Core
Core
CPU
CPU
Display
Display
Peripherals
Peripherals
Analog
Analog
Baseband
Baseband
CMOS (Digital, Analog)
GaAs/SiGe (for RF)
USB
USB
Power
Power
Mgmt.
Mgmt.
Flash
Flash
SRAM
SRAM
Bluetooth
Bluetooth
CMOS (Digital)
8
CMOS (Memory)
Integration via Packaging
Under Research
Ultrathin Stacked
Chip Scale Packaging
2003
8 Die Stack
50 µm Die
>150 M Units
Shipped
4 to 5 Die
1 to 1.2 mm
75 µm Die Thinness
2 to 3 Die
1.2mm
125 - 175 µm Die
Thickness
2 Die
1.4mm Package Height
9
Wireless Internet on a Chip
by Flash+Logic Integration
Intel®
MicroSignal
Architecture
Logic
90nm
S
R
A
M
Flash
Power mgmt
& peripherals
90nm Transistor Gate
on 0.13µm Process
0.16µm2 Flash Cell
Cell
phone
stds.
PXA800F Cellular Processor
Integration improves density,
speed, power consumption
Source: Intel
10
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
11
Intel’s Technologies for Convergence:
CMOS Base + Apps-Specific Modules
Logic
Logic
CMOS
CMOSBase
Base
Processor
Flash
FlashMemory
Memory
Memory
Flash
Flash++Logic
Logic
++Analog
Analog
Integrated PCA
(Cellular)
Mixed
MixedSignal
Signal
Ethernet/WiFi
High
High
Frequency
Frequency
Logic
Logic
Optical
Economy of scale (shared base)
+ application
-specific optimization
application-specific
12
Process Modules Available for
Ethernet/WiFi and Optical Comm
Inductor Spiral
MIM Capacitor/Resistor
MIM RES
M7
VIA
MIM CAP
M6
M6 BOTTOM PLATE
SiGe BJT
EMITTER
Poly Si Resistor
CMOS
POLY Si
D
SiGe
BASE
S
STI
COLLECTOR
13
10Gb/s SONET Transceiver
on 90nm Technology
TX
RX
Output @ 10.66Gb/s
Single chip CMOS
Precision passives
(R, L, C)
Source: Intel
14
802.11 (WiFi) Integration
Improves Cost and Power
Today
90nm
Digital Functions
MAC
Baseband
Analog Functions
RF Radio
Analog
Front End
15
Radio Research at Intel
Intelligent
Intelligent
Roaming
Roaming
Silicon
Silicon
Radio
Radio
Smart
SmartAntenna
Antenna
Systems
Systems
Dynamically
Dynamically
Reconfigurable
Reconfigurable
MEMS
MEMS
Components
Components
MEMS: Micro Electro Mechanical Systems
16
MEMS Antenna Switches and Filters
for Multi Band Radios
Antenna
Receive
MEMS Antenna Switch
Transmit
MEMS Filters
MEMS benefits: Low insertion loss
+ component integration
17
Integrated MEMS RF Switches
Drain
Source
Gate
Switch design
Multiple gold RF switches integrated
into one silicon MEMS chip
Fabricated using
silicon processing technology
Source: Intel
18
MEMS Integrated with CMOS
MEMS
Varactor
MEMS Varactor
flip chip bonded
to a CMOS VCO
Source: Intel
19
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
20
Silicon Devices Shrink to Virus Size..
50nm
100nm
Influenza virus
Transistor for
90nm Process
Source: CDC
Source: Intel
..and Nanotechnology Scale
21
Intel in Production with
Nanotechnology (< 100nm)
10000
10
Nominal feature size
1000
1
130nm
90nm
Micron
Nanometer
Gate Length
100
0.1
Nanotechnology
70nm
50nm
10
0.01
1970
1980
Source: Intel
1990
2000
22
2010
2020
Lithography is the Designer’s “Brush”
Lithography is indispensable for
defining locations/configurations
of circuit elements/functions
23
Lithography Gap to Close with EUVL
(Extreme Ultra Violet Lithography)
1000
nm
Feature size
248nm
100
193nm
Gap
Lithography
Wavelength
157nm
13nm (EUVL)
10
’89 ’91 ’93 ’95 ’97 ’99 ’01 ’03 ’05 ’07 ’09 ’11
Initial Production
Source: Intel
24
EUV LLC Consortium Demonstrates
EUVL with Prototype Exposure Tool
Source: Sandia
25
Full Field Images Produced by
EUV Prototype Exposure Tool
80nm elbows 1:1
200mm wafer
24 x 32.5mm2 field
100nm contacts 1:1
Commercial EUVL exposure tool
feasibility demonstrated
Source: Sandia
26
EUV Masks Simpler to Pattern and
Inspect than Optical Masks
EUV Mask
Optical Mask
(45nm Process)
(45nm Process)
Est. Cost/Layer:
< $90K
Est. Cost/layer:
$100K (OPC Only)
$150K (OPC + Comp)
EUVL masks will cost less than
optical lithography masks
27
EUVL Being Developed and
Commercialized Worldwide
Japan
Europe
> 10 Companies
Consortia:
• ASET
• EUVA
• MIRAI
> 50 Companies
Consortia:
• PREUVE
• MEDEA+
• LETI
• IMEC
US
> 40 Companies
Consortia:
• EUV LLC
• I-SEMATECH
• VNL RDC
• SRC
28
Intel’s Transistor Research in
Deep Nanotechnology Space
Experimental transistors for future process generations
30nm
20nm
65nm process
2005 production
15nm
45nm process
2007 production
32nm process
2009 production
Transistors will be improved
for production
Source: Intel
29
10nm
22nm process
2011 production
Intel’s Transistors Run Fast on
90nm Strained Silicon Process
Current Flow
Normal
electron
flow
Faster
electron
flow
Normal Silicon Lattice
Strained Silicon Lattice
A new way to speed up
with nanotechnology
Source: Intel
30
Transistors Improved by Going 3-D
Intel’s experimental Tri-gate transistor
raises performance, lowers off current
Gate
Gate
Drain
Drain
Source
Source
Silicon
New nanotechnology
device options coming
Source: Intel
31
Future Nanotechnology will Ride
on Silicon Technology Base
Silicon
Nanowire*
Carbon
Nanotube
Nanotube/Nanowire
Transistors
Molecular
Electronics
Nanodevices
Silicon
Technology
Base
Innovations expected to overcome scaling limits
*Source: Morales & Lieber, Harvard Univ 32
Nanotechnology Brings
Welcomed Opportunities
y Renewal and extension of silicon technology
– New materials, processes and device structures
– Integrate innovations into silicon technology base
– Break limits of “static” silicon scaling model
y Intel plans to lead in nanotechnology
– Already in production with nanotechnology
– Heavily engaged in nanotechnology R&D
– Best positioned to use nanotechnology innovations
33
Video
Nanotechnology extends Silicon Technology
Dr. R. Stanley Williams
HPL Fellow, Director, Quantum Science Research
Hewlett-Packard Labs
Professor Yoshio Nishi
Professor Electrical Engineering
Director, Stanford Nano Fabrication Facility
34
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
– Use silicon scaling and integration to improve
performance, energy efficiency, cost
y CMOS Base + Application Specific Modules
– Shared CMOS base for economy of scale
– Process modules optimized for each application
y Silicon Technology Base + Nanotechnology
– Nanotechnology innovations will ride on silicon
– Intel leading nanotechnology production, R&D
35
for Convergence
Sunlin Chou
Senior Vice President
General Manager
Technology and Manufacturing Group
April 2003
1
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
2
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
3
Computing + Communications Vision:
Data Anytime, Anywhere
Cellular: Voice + Data
@ the Office
Everywhere
Else
10/100/GbE
802.11b/a
@ Hotspots
@ Home
802.11b/a
Broadband
10/100
4
802.11b/a
Cellular
Silicon is the Engine
Converged
Computing and
Communications
Microprocessors
Drive convergence
with silicon integration
Memory
5
Silicon Scaling and Integration
Improve Performance, Power, Cost
Relative scale (log)
Scaling effects on transistors
1
Delay
Swi
C os t
tchi
ng e
ner
gy
0.1
0.01
0.001
1993 1995 1997 1999 2001 2003 2005
.5µm
.35µm
.25µm .18µm .13µm
Silicon scaling
Source: Intel
6
90nm
65nm
Cell Phones For Voice + Data
Mb
Flash Memory Density Growth in Japan
200
160
44K COLOR
RICH JAVA APPS.
MP3
PHOTOS
120
80
40
0
1998
VOICE ONLY
1999
PACKETIZED DATA
2000
256 COLOR
2001
4K COLOR
JAVA APPS.
Convergence increases silicon usage
Source: NEC, Intel
7
2002
Converged Cell Phone
Integration Opportunities
Communications
Computing
Memory
Signal
Signal
Radio
Processing
Radio(RF)
(RF) Processing
Rx
Rx
Tx
Tx
PA
PA
DSP
DSP
Core
Core
CPU
CPU
Display
Display
Peripherals
Peripherals
Analog
Analog
Baseband
Baseband
CMOS (Digital, Analog)
GaAs/SiGe (for RF)
USB
USB
Power
Power
Mgmt.
Mgmt.
Flash
Flash
SRAM
SRAM
Bluetooth
Bluetooth
CMOS (Digital)
8
CMOS (Memory)
Integration via Packaging
Under Research
Ultrathin Stacked
Chip Scale Packaging
2003
8 Die Stack
50 µm Die
>150 M Units
Shipped
4 to 5 Die
1 to 1.2 mm
75 µm Die Thinness
2 to 3 Die
1.2mm
125 - 175 µm Die
Thickness
2 Die
1.4mm Package Height
9
Wireless Internet on a Chip
by Flash+Logic Integration
Intel®
MicroSignal
Architecture
Logic
90nm
S
R
A
M
Flash
Power mgmt
& peripherals
90nm Transistor Gate
on 0.13µm Process
0.16µm2 Flash Cell
Cell
phone
stds.
PXA800F Cellular Processor
Integration improves density,
speed, power consumption
Source: Intel
10
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
11
Intel’s Technologies for Convergence:
CMOS Base + Apps-Specific Modules
Logic
Logic
CMOS
CMOSBase
Base
Processor
Flash
FlashMemory
Memory
Memory
Flash
Flash++Logic
Logic
++Analog
Analog
Integrated PCA
(Cellular)
Mixed
MixedSignal
Signal
Ethernet/WiFi
High
High
Frequency
Frequency
Logic
Logic
Optical
Economy of scale (shared base)
+ application
-specific optimization
application-specific
12
Process Modules Available for
Ethernet/WiFi and Optical Comm
Inductor Spiral
MIM Capacitor/Resistor
MIM RES
M7
VIA
MIM CAP
M6
M6 BOTTOM PLATE
SiGe BJT
EMITTER
Poly Si Resistor
CMOS
POLY Si
D
SiGe
BASE
S
STI
COLLECTOR
13
10Gb/s SONET Transceiver
on 90nm Technology
TX
RX
Output @ 10.66Gb/s
Single chip CMOS
Precision passives
(R, L, C)
Source: Intel
14
802.11 (WiFi) Integration
Improves Cost and Power
Today
90nm
Digital Functions
MAC
Baseband
Analog Functions
RF Radio
Analog
Front End
15
Radio Research at Intel
Intelligent
Intelligent
Roaming
Roaming
Silicon
Silicon
Radio
Radio
Smart
SmartAntenna
Antenna
Systems
Systems
Dynamically
Dynamically
Reconfigurable
Reconfigurable
MEMS
MEMS
Components
Components
MEMS: Micro Electro Mechanical Systems
16
MEMS Antenna Switches and Filters
for Multi Band Radios
Antenna
Receive
MEMS Antenna Switch
Transmit
MEMS Filters
MEMS benefits: Low insertion loss
+ component integration
17
Integrated MEMS RF Switches
Drain
Source
Gate
Switch design
Multiple gold RF switches integrated
into one silicon MEMS chip
Fabricated using
silicon processing technology
Source: Intel
18
MEMS Integrated with CMOS
MEMS
Varactor
MEMS Varactor
flip chip bonded
to a CMOS VCO
Source: Intel
19
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
y Silicon Technology Base + Nanotechnology
20
Silicon Devices Shrink to Virus Size..
50nm
100nm
Influenza virus
Transistor for
90nm Process
Source: CDC
Source: Intel
..and Nanotechnology Scale
21
Intel in Production with
Nanotechnology (< 100nm)
10000
10
Nominal feature size
1000
1
130nm
90nm
Micron
Nanometer
Gate Length
100
0.1
Nanotechnology
70nm
50nm
10
0.01
1970
1980
Source: Intel
1990
2000
22
2010
2020
Lithography is the Designer’s “Brush”
Lithography is indispensable for
defining locations/configurations
of circuit elements/functions
23
Lithography Gap to Close with EUVL
(Extreme Ultra Violet Lithography)
1000
nm
Feature size
248nm
100
193nm
Gap
Lithography
Wavelength
157nm
13nm (EUVL)
10
’89 ’91 ’93 ’95 ’97 ’99 ’01 ’03 ’05 ’07 ’09 ’11
Initial Production
Source: Intel
24
EUV LLC Consortium Demonstrates
EUVL with Prototype Exposure Tool
Source: Sandia
25
Full Field Images Produced by
EUV Prototype Exposure Tool
80nm elbows 1:1
200mm wafer
24 x 32.5mm2 field
100nm contacts 1:1
Commercial EUVL exposure tool
feasibility demonstrated
Source: Sandia
26
EUV Masks Simpler to Pattern and
Inspect than Optical Masks
EUV Mask
Optical Mask
(45nm Process)
(45nm Process)
Est. Cost/Layer:
< $90K
Est. Cost/layer:
$100K (OPC Only)
$150K (OPC + Comp)
EUVL masks will cost less than
optical lithography masks
27
EUVL Being Developed and
Commercialized Worldwide
Japan
Europe
> 10 Companies
Consortia:
• ASET
• EUVA
• MIRAI
> 50 Companies
Consortia:
• PREUVE
• MEDEA+
• LETI
• IMEC
US
> 40 Companies
Consortia:
• EUV LLC
• I-SEMATECH
• VNL RDC
• SRC
28
Intel’s Transistor Research in
Deep Nanotechnology Space
Experimental transistors for future process generations
30nm
20nm
65nm process
2005 production
15nm
45nm process
2007 production
32nm process
2009 production
Transistors will be improved
for production
Source: Intel
29
10nm
22nm process
2011 production
Intel’s Transistors Run Fast on
90nm Strained Silicon Process
Current Flow
Normal
electron
flow
Faster
electron
flow
Normal Silicon Lattice
Strained Silicon Lattice
A new way to speed up
with nanotechnology
Source: Intel
30
Transistors Improved by Going 3-D
Intel’s experimental Tri-gate transistor
raises performance, lowers off current
Gate
Gate
Drain
Drain
Source
Source
Silicon
New nanotechnology
device options coming
Source: Intel
31
Future Nanotechnology will Ride
on Silicon Technology Base
Silicon
Nanowire*
Carbon
Nanotube
Nanotube/Nanowire
Transistors
Molecular
Electronics
Nanodevices
Silicon
Technology
Base
Innovations expected to overcome scaling limits
*Source: Morales & Lieber, Harvard Univ 32
Nanotechnology Brings
Welcomed Opportunities
y Renewal and extension of silicon technology
– New materials, processes and device structures
– Integrate innovations into silicon technology base
– Break limits of “static” silicon scaling model
y Intel plans to lead in nanotechnology
– Already in production with nanotechnology
– Heavily engaged in nanotechnology R&D
– Best positioned to use nanotechnology innovations
33
Video
Nanotechnology extends Silicon Technology
Dr. R. Stanley Williams
HPL Fellow, Director, Quantum Science Research
Hewlett-Packard Labs
Professor Yoshio Nishi
Professor Electrical Engineering
Director, Stanford Nano Fabrication Facility
34
Silicon Integration for Convergence:
Three Strategic Combinations
y Computing + Communications
– Use silicon scaling and integration to improve
performance, energy efficiency, cost
y CMOS Base + Application Specific Modules
– Shared CMOS base for economy of scale
– Process modules optimized for each application
y Silicon Technology Base + Nanotechnology
– Nanotechnology innovations will ride on silicon
– Intel leading nanotechnology production, R&D
35