Index of /intel-research/silicon
Cont inuing M oore 's La w
Cost Re duc t ion in N on
V ola t ile Se m ic onduc t or
M e m orie s
Stefan Lai, PhD
Vice President, Technology and Manufacturing Group
Intel Corp.
Gordon E. Moore
N O EX PON EN T I AL I S
FOREV ER . . .
2
N O EX PON EN T I AL I S
FOREV ER . . .
BUT
WE CAN DELAY “FOREVER”
Gordon E. Moore
3
FLASH SCALI N G I S
RU N N I N G I N T O LI M I T S
4
FLASH SCALI N G I S
RU N N I N G I N T O LI M I T S
BUT
WE CAN DELAY “THE LIMITS”
5
I nt e l ET OX ® (N OR) T e c hnology
Sc a ling
1986 / 1.5µm
1988 / 1.0µm
1998 / 0.25µm
1991 / 0.8µm
2000 / 0.18µm
1993 / 0.6µm 1996 / 0.4µm
2002 / 0.13µm
2004 / 90nm
5X
5X
Volume Production Year / Technology Generation
y 18+ years & 9 Generations of ETOX® (Intel NOR); High Volume
Production starting for 90 nm
y 7+ years and 5 Generations of Intel StrataFlashTM (Multi Level
Cells 2bit / cell ) memory
6
I nt e l ET OX ® (N OR) T e c hnology
Sc a ling
1986 / 1.5µm
1988 / 1.0µm
1991 / 0.8µm
1993 / 0.6µm 1996 / 0.4µm
1/47
6
1998 / 0.25µm
2000 / 0.18µm
2002 / 0.13µm
2004 / 90nm
5X
5X
Volume Production Year / Technology Generation
y 18+ years & 9 Generations of ETOX® (Intel NOR); High Volume
Production starting for 90 nm
y 7+ years and 5 Generations of Intel StrataFlashTM (Multi Level
Cells 2bit / cell ) memory
7
N V M e m ory T ra nsist ors
y Non volatile memory typically has a 10 year retention spec,
requiring high energy barrier for electrons in floating gate
y To overcome the high energy barrier, NV memory transistor
operates at much higher voltage compared to logic
transistors
¾
~10V gate/ ~5V drain for ETOX®
¾
~20V gate for NAND
y NV transistors run into physical scaling limit earlier
compared to logic transistors
8
N OR Ga t e Le ngt h Sc a ling Lim it
1200
Programming
Hot eover barrier
LG
(nm)
e-
800
3.2 ev
400
45nm
Silicon
0
Floating Gate
Silicon
.80µ 0.60µ 0.40µ 0.25µ 0.18µ 0.13µ 90nm 65nm 45nm 32nm
Litho Node
+Vg
> 3.2 V
For Efficient Programming
Source
LG
~130nm
Drain
9
Floa t ing Ga t e Cha rge St ora ge Sc a ling
Estimated # Electrons Stored vs Litho Node
1000000
100000
10000
# Electrons
NAND # Electrons
NOR # Electrons
1000
1
0.1
100
0.01
Litho Node (Microns)
y Cell capacitance (charge stored) decreases with cell
scaling while leakage mechanism remains the same ->
larger Vt shift per electron
y Smaller NAND cell Æ Fewer Electrons
y MLC Charge Retention 1-2 generations more aggressive
on NAND
10
I T RS Fla sh sc a ling proje c t ion
2002
NOR
Coupling ratio
Tunnel oxide (nm)
2007
NAND
NOR
0.65-0.75 0.65-0.75 0.6-0.7
2010
2016
NAND
NOR
NAND
NOR
NAND
0.6-0.7
0.6-0.7
0.6-0.7
0.6-0.7
0.6-0.7
9-10
7-8
8-9
6-7
8-9
6-7
8
6-7
Interpoly oxide (nm)
12-14
13-15
8.5-10.5
10-13
8-10
10-13
4-6
9-10
Endurance (# cycles)
1E5
1E5
1E5
1E5
1E6
1E6
1E7
1E7
Retention (years)
10-20
10-20
10-20
10-20
10-20
10-20
20
20
NOR Iread (µ A)
35-43
max. # bits per cell
2
29-37
2
4
27-33
4
8
22-28
8
8
8
Taken from the 2002 ITRS update
The major scaling problem is related to the tunnel dielectric
thickness
11
Sc a ling Opport unit ie s
Poly 2
ONO
Electrical
Contact
Electrical
Tunnel oxide
Electrical &
Reliability
Resolution Electrical
Resolution
Alignment
12
Opport unit ie s for 4 5 nm a nd be yond
y Lithography: cornerstone for new technology node
y Tight pitch/high aspect ratio processing
y Tunnel oxide barrier engineering
y ONO dielectric engineering
y Floating gate material engineering
y Channel engineering
y Contact engineering
13
Tox
Poly
ONO
Barrier Eng
TDielectric
Quantum Dot
High k
Re -e ngine e r t he fla sh Ce ll
14
15
N e w N V M e m ory
T e c hnologie s
N e w N V M e m ory T e c hnologie s
y With the perceived difficulties of floating gate flash
memory scaling, many new memory technologies
were reported as possible replacement candidates
y Most involve the introduction of new material and/or
new physical switching phenomena
How to choose between the
technologies?
17
Applied Electric Field
Moves Center Atom
18
Applied Electric Field
Moves Center Atom
19
Winning At t ribut e s
y Memory market is well established, new entrants
must provide incentive for customers to use
something new
y Cost is the most important incentive: but given the
learning curve, new entrants must have significant
node to node advantage to catch up
y Functionality (performance, power etc) is difficult to
quantify: but customers tend to favor cost over
functionality (DRAM difficult to use, biggest memory
market segment)
Cost is the most important factor
20
Cost c onside ra t ion:
a Sim plifie d V ie w
y
Any usable memory has to have mechanisms to read and
write. Two general ways to R/W:
¾
X-Y address in traditional memory architecture, with serial read
(CCD or NAND) as one variation
¾
Seek and scan similar to HDD
y
X-Y addressable memory is limited by lithography and
follows Moore’s Law
y
Seek and scan memory, no lithography, limited by scan
mechanism, size and density of storage areas in storage
medium
21
X -Y Addre sse d Fla sh
y Transistors at cross point
with wordlines and bitlines
for cell selection and
read/write
y NAND memory is smaller
compared to NOR: no
contact but also slower to
read
y Don’t see any new
technology with X-Y
address to be smaller than
NOR/NAND with MLC
22
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be first
limited in scaling -> ETOX, NAND, FeRAM, MRAM; diode
switch scales better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode more
scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest cost for
litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
23
Big
Small
Diode sw it c h be t t e r t ha n
t ra nsist or sw it c h
24
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be
limited in scaling -> FeRAM, MRAM, diode switch scales
better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode more
scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest cost for
litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
25
Sm a ll is not t ha t sm a ll
y X-Y addressable memory is
always limited by the limiting
lithography steps: have to
connect to the real world
circuits
y Either self assembled circuits at
the smaller geometry or new
innovative architecture
26
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be
limited in scaling -> FeRAM, MRAM, diode switch scales
better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode
more scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest
cost for litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
27
M ult i-la ye r is sm a lle r
Single Layer cell area =
4 λ2
Level N+1: Antifuse, P-, P+, conductor, P+
(fill and antifuse made transparent)
Matrix Confidential
Level N+1: Antifuse, P-, P+, conductor, P+
(fill and antifuse made transparent)
Matrix Confidential
Multi Layer cell area =
4 λ2/ N (number of
layers)
28
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be
limited in scaling -> FeRAM, MRAM, diode switch scales
better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode
more scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest
cost for litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
29
Se e k a nd Sc a n ha s be st sc a ling
pot e nt ia l
y With capability of contacting
areas smaller than X-Y cross
points defined by lithography,
very dense memory can be
realized
y The challenge is in the
development of multi-probe
systems as well as new
memory mechanisms
y Still in research stage
30
One Winne r Only?
y With the diverse requirement, NO one memory
technology can meet all the need
y Market segment size tends to be an inverse function
of cost per bit => lower cost, larger market segment
y There are special need that can only be met by
special memories
¾ FeRAM,
¾ MRAM,
lowest power, contactless smartcards
fast read write, unlimited number of cycles
y What is the killer-app that must have the new
memory? Otherwise, must compete on cost!
31
I nt e l Re se a rc h Ex a m ple s
y When flash scaling slows down, ovonics
memory is our choice because of its projected
scaling capability and low cost
y Ferroelectric polymer memory with multilayer
memory stacking has the potential to be very
low in cost
32
Ovonic s U nifie d M e m ory
Data Storage Region
y Operation
y Chalcogenide material
alloys used in rewritable CDs and DVDs
y Electrical energy (heat)
converts the material
between crystalline
(conductive) and
amorphous (resistive)
phases
y Cell reads by
measuring resistance
y Non-destructive read
y ~1012 write/erase cycles
y Medium write power
y Relatively easy
integration with CMOS
Chalcogenide
Amorphous
Poly Crystalline
Heater
Phase Change
Material
Resistive
Electrode
33
Fe rroe le c t ric Polym e r M e m ory
y Operation
Word line
Word line
Polymer Layer
Bit line
Bit line
Bit line
Polymer Layer
Word line
Insulator (polymer)
Word line
Word line
Polymer Layer
Bit line
Bit line
Bit line
Polymer Layer
Word line
y Polymeric Ferroelectric RAM
(PFRAM)
y Polymer chains with a dipole
moment
y Data stored by changing the
polarization of the polymer
between metal lines
y Zero transistors per bit of storage
y Polymer layers can be stacked
Charge Pump
Sense Amps/
Interconnect Interface Logic
CMOS Base Wafer
dipole
moment
34
Displa c e m e nt T im e line Ex a m ple
-- EPROM
EPROM ttoo Fla
Flash
sh --
1st Product
Availability
5 years from first product availability (1988) to revenue crossover (1992).
35
Whe n is t he Right T im e for
Disrupt ive T e c hnology I nse rt ion
Initial
Learning
Cost / Bit
(Log Scale)
New
Memory
When?
Floating Gate
Slow down
NOW
Time
New Memory crosses over
Floating Gate
36
Whe n is t he Right T im e for
Disrupt ive T e c hnology I nse rt ion
Initial
Learning
Cost / Bit
(Log Scale)
New
Memory
When?
Floating Gate
Slow down
NOW
Time
New Memory crosses over
Floating Gate
37
Sum m a ry
y NOR flash scaling will continue through innovation
with increasing difficulty
y Multiple new memory technologies had been
evaluated and two promising candidates identified:
¾ OUM
for code and small data to replace NOR
¾ Polymer
for low cost card memory to compete with NAND
y The customers will ultimately decide which of the
new memory technologies will meet their need
38
Cost Re duc t ion in N on
V ola t ile Se m ic onduc t or
M e m orie s
Stefan Lai, PhD
Vice President, Technology and Manufacturing Group
Intel Corp.
Gordon E. Moore
N O EX PON EN T I AL I S
FOREV ER . . .
2
N O EX PON EN T I AL I S
FOREV ER . . .
BUT
WE CAN DELAY “FOREVER”
Gordon E. Moore
3
FLASH SCALI N G I S
RU N N I N G I N T O LI M I T S
4
FLASH SCALI N G I S
RU N N I N G I N T O LI M I T S
BUT
WE CAN DELAY “THE LIMITS”
5
I nt e l ET OX ® (N OR) T e c hnology
Sc a ling
1986 / 1.5µm
1988 / 1.0µm
1998 / 0.25µm
1991 / 0.8µm
2000 / 0.18µm
1993 / 0.6µm 1996 / 0.4µm
2002 / 0.13µm
2004 / 90nm
5X
5X
Volume Production Year / Technology Generation
y 18+ years & 9 Generations of ETOX® (Intel NOR); High Volume
Production starting for 90 nm
y 7+ years and 5 Generations of Intel StrataFlashTM (Multi Level
Cells 2bit / cell ) memory
6
I nt e l ET OX ® (N OR) T e c hnology
Sc a ling
1986 / 1.5µm
1988 / 1.0µm
1991 / 0.8µm
1993 / 0.6µm 1996 / 0.4µm
1/47
6
1998 / 0.25µm
2000 / 0.18µm
2002 / 0.13µm
2004 / 90nm
5X
5X
Volume Production Year / Technology Generation
y 18+ years & 9 Generations of ETOX® (Intel NOR); High Volume
Production starting for 90 nm
y 7+ years and 5 Generations of Intel StrataFlashTM (Multi Level
Cells 2bit / cell ) memory
7
N V M e m ory T ra nsist ors
y Non volatile memory typically has a 10 year retention spec,
requiring high energy barrier for electrons in floating gate
y To overcome the high energy barrier, NV memory transistor
operates at much higher voltage compared to logic
transistors
¾
~10V gate/ ~5V drain for ETOX®
¾
~20V gate for NAND
y NV transistors run into physical scaling limit earlier
compared to logic transistors
8
N OR Ga t e Le ngt h Sc a ling Lim it
1200
Programming
Hot eover barrier
LG
(nm)
e-
800
3.2 ev
400
45nm
Silicon
0
Floating Gate
Silicon
.80µ 0.60µ 0.40µ 0.25µ 0.18µ 0.13µ 90nm 65nm 45nm 32nm
Litho Node
+Vg
> 3.2 V
For Efficient Programming
Source
LG
~130nm
Drain
9
Floa t ing Ga t e Cha rge St ora ge Sc a ling
Estimated # Electrons Stored vs Litho Node
1000000
100000
10000
# Electrons
NAND # Electrons
NOR # Electrons
1000
1
0.1
100
0.01
Litho Node (Microns)
y Cell capacitance (charge stored) decreases with cell
scaling while leakage mechanism remains the same ->
larger Vt shift per electron
y Smaller NAND cell Æ Fewer Electrons
y MLC Charge Retention 1-2 generations more aggressive
on NAND
10
I T RS Fla sh sc a ling proje c t ion
2002
NOR
Coupling ratio
Tunnel oxide (nm)
2007
NAND
NOR
0.65-0.75 0.65-0.75 0.6-0.7
2010
2016
NAND
NOR
NAND
NOR
NAND
0.6-0.7
0.6-0.7
0.6-0.7
0.6-0.7
0.6-0.7
9-10
7-8
8-9
6-7
8-9
6-7
8
6-7
Interpoly oxide (nm)
12-14
13-15
8.5-10.5
10-13
8-10
10-13
4-6
9-10
Endurance (# cycles)
1E5
1E5
1E5
1E5
1E6
1E6
1E7
1E7
Retention (years)
10-20
10-20
10-20
10-20
10-20
10-20
20
20
NOR Iread (µ A)
35-43
max. # bits per cell
2
29-37
2
4
27-33
4
8
22-28
8
8
8
Taken from the 2002 ITRS update
The major scaling problem is related to the tunnel dielectric
thickness
11
Sc a ling Opport unit ie s
Poly 2
ONO
Electrical
Contact
Electrical
Tunnel oxide
Electrical &
Reliability
Resolution Electrical
Resolution
Alignment
12
Opport unit ie s for 4 5 nm a nd be yond
y Lithography: cornerstone for new technology node
y Tight pitch/high aspect ratio processing
y Tunnel oxide barrier engineering
y ONO dielectric engineering
y Floating gate material engineering
y Channel engineering
y Contact engineering
13
Tox
Poly
ONO
Barrier Eng
TDielectric
Quantum Dot
High k
Re -e ngine e r t he fla sh Ce ll
14
15
N e w N V M e m ory
T e c hnologie s
N e w N V M e m ory T e c hnologie s
y With the perceived difficulties of floating gate flash
memory scaling, many new memory technologies
were reported as possible replacement candidates
y Most involve the introduction of new material and/or
new physical switching phenomena
How to choose between the
technologies?
17
Applied Electric Field
Moves Center Atom
18
Applied Electric Field
Moves Center Atom
19
Winning At t ribut e s
y Memory market is well established, new entrants
must provide incentive for customers to use
something new
y Cost is the most important incentive: but given the
learning curve, new entrants must have significant
node to node advantage to catch up
y Functionality (performance, power etc) is difficult to
quantify: but customers tend to favor cost over
functionality (DRAM difficult to use, biggest memory
market segment)
Cost is the most important factor
20
Cost c onside ra t ion:
a Sim plifie d V ie w
y
Any usable memory has to have mechanisms to read and
write. Two general ways to R/W:
¾
X-Y address in traditional memory architecture, with serial read
(CCD or NAND) as one variation
¾
Seek and scan similar to HDD
y
X-Y addressable memory is limited by lithography and
follows Moore’s Law
y
Seek and scan memory, no lithography, limited by scan
mechanism, size and density of storage areas in storage
medium
21
X -Y Addre sse d Fla sh
y Transistors at cross point
with wordlines and bitlines
for cell selection and
read/write
y NAND memory is smaller
compared to NOR: no
contact but also slower to
read
y Don’t see any new
technology with X-Y
address to be smaller than
NOR/NAND with MLC
22
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be first
limited in scaling -> ETOX, NAND, FeRAM, MRAM; diode
switch scales better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode more
scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest cost for
litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
23
Big
Small
Diode sw it c h be t t e r t ha n
t ra nsist or sw it c h
24
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be
limited in scaling -> FeRAM, MRAM, diode switch scales
better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode more
scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest cost for
litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
25
Sm a ll is not t ha t sm a ll
y X-Y addressable memory is
always limited by the limiting
lithography steps: have to
connect to the real world
circuits
y Either self assembled circuits at
the smaller geometry or new
innovative architecture
26
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be
limited in scaling -> FeRAM, MRAM, diode switch scales
better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode
more scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest
cost for litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
27
M ult i-la ye r is sm a lle r
Single Layer cell area =
4 λ2
Level N+1: Antifuse, P-, P+, conductor, P+
(fill and antifuse made transparent)
Matrix Confidential
Level N+1: Antifuse, P-, P+, conductor, P+
(fill and antifuse made transparent)
Matrix Confidential
Multi Layer cell area =
4 λ2/ N (number of
layers)
28
Bre a k ing t he sc a ling ba rrie r
y Memory technologies requiring transistor switch will be
limited in scaling -> FeRAM, MRAM, diode switch scales
better -> OUM, RRAM
Ä Follows Moore’s Law limited by transistor/diode
y Simple cross point switch with no transistor or diode
more scalable: molecular memories
Ä Continue Moore’s Law beyond transistor age
y Multi-layer memories have the potential to be lowest
cost for litho defined memory
Ä Drop below historical Moore’s Law
y Seek and scan can be the lowest cost but involves new
memory storage and sense mechanism
Ä May go faster then Moore’s Law (e.g. HDD)
29
Se e k a nd Sc a n ha s be st sc a ling
pot e nt ia l
y With capability of contacting
areas smaller than X-Y cross
points defined by lithography,
very dense memory can be
realized
y The challenge is in the
development of multi-probe
systems as well as new
memory mechanisms
y Still in research stage
30
One Winne r Only?
y With the diverse requirement, NO one memory
technology can meet all the need
y Market segment size tends to be an inverse function
of cost per bit => lower cost, larger market segment
y There are special need that can only be met by
special memories
¾ FeRAM,
¾ MRAM,
lowest power, contactless smartcards
fast read write, unlimited number of cycles
y What is the killer-app that must have the new
memory? Otherwise, must compete on cost!
31
I nt e l Re se a rc h Ex a m ple s
y When flash scaling slows down, ovonics
memory is our choice because of its projected
scaling capability and low cost
y Ferroelectric polymer memory with multilayer
memory stacking has the potential to be very
low in cost
32
Ovonic s U nifie d M e m ory
Data Storage Region
y Operation
y Chalcogenide material
alloys used in rewritable CDs and DVDs
y Electrical energy (heat)
converts the material
between crystalline
(conductive) and
amorphous (resistive)
phases
y Cell reads by
measuring resistance
y Non-destructive read
y ~1012 write/erase cycles
y Medium write power
y Relatively easy
integration with CMOS
Chalcogenide
Amorphous
Poly Crystalline
Heater
Phase Change
Material
Resistive
Electrode
33
Fe rroe le c t ric Polym e r M e m ory
y Operation
Word line
Word line
Polymer Layer
Bit line
Bit line
Bit line
Polymer Layer
Word line
Insulator (polymer)
Word line
Word line
Polymer Layer
Bit line
Bit line
Bit line
Polymer Layer
Word line
y Polymeric Ferroelectric RAM
(PFRAM)
y Polymer chains with a dipole
moment
y Data stored by changing the
polarization of the polymer
between metal lines
y Zero transistors per bit of storage
y Polymer layers can be stacked
Charge Pump
Sense Amps/
Interconnect Interface Logic
CMOS Base Wafer
dipole
moment
34
Displa c e m e nt T im e line Ex a m ple
-- EPROM
EPROM ttoo Fla
Flash
sh --
1st Product
Availability
5 years from first product availability (1988) to revenue crossover (1992).
35
Whe n is t he Right T im e for
Disrupt ive T e c hnology I nse rt ion
Initial
Learning
Cost / Bit
(Log Scale)
New
Memory
When?
Floating Gate
Slow down
NOW
Time
New Memory crosses over
Floating Gate
36
Whe n is t he Right T im e for
Disrupt ive T e c hnology I nse rt ion
Initial
Learning
Cost / Bit
(Log Scale)
New
Memory
When?
Floating Gate
Slow down
NOW
Time
New Memory crosses over
Floating Gate
37
Sum m a ry
y NOR flash scaling will continue through innovation
with increasing difficulty
y Multiple new memory technologies had been
evaluated and two promising candidates identified:
¾ OUM
for code and small data to replace NOR
¾ Polymer
for low cost card memory to compete with NAND
y The customers will ultimately decide which of the
new memory technologies will meet their need
38