Optical interconnect press foils
Optical I/O Technology for
Chip-to-Chip Digital VLSI
Ian Young
Intel FellowDirector, Advanced Circuits and Technology Integration Logic Technology Development
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What are We Announcing?
•
Intel has made significant progress demonstrating thefeasibility of optical chip-to-chip interconnect at data rates over 1 Giga-Transfers per second.
•
Optical chip-to-chip interconnect may offer a faster, cheaper, better alternative to metal-based data buses between CPU and it’s supporting chips•
The demonstration was done with 0.18m-CMOStransceiver, with on-chip laser drivers, input amps, and self-test features. The transceiver chip is integrated with the
optical emitters, detectors, and wave-guides in a hybrid package
•
This optical I/O implementation is highly compatible with CPU architecture, process, and packaging•
This announcement is a progress report from Intel’s Component’s Research Lab. Intel has not made a(3)
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Why is this Important?
•
Individual bus speed between microprocessor andchipset will increase an order of magnitude in the next 7-10 years.
•
With such high speeds, Copper interconnects on a mother board will be bandwidth-limited due to:–
Signal attenuation and distortion (signal-to-noise degradation)–
Reflections (signal-to-noise degradation)–
Cross-talk and EMI (electromagnetic interference)•
Optical interconnect achieves higher bandwidth over larger distances than Copper interconnect– Also, components can be spread further apart without impacting Bandwidth, which enables more efficient and cheaper cooling
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Motivation
•
Optoelectronics (OE) replaced Cu in long (SONET) and short (Enterprise) distances.•
Extending OE to thecomputer - Box-to-Box
- Board-to-board - Chip-to-chip - On-chip?
•
May allow interconnects to continue to scale in speed•
However, cost should beacceptable
- Comparable or less than electrical
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0-2 years 2-7 years 7+ years
Chip-2-Chip
(<20”)
Brd-2-Brd
(<30”, with 2 connectors)
Box-2-Box
(<3 meters, with 4 connectors & 3 cables)
High Speed I/O for Processors – Possible
Scenario
Copper
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I/O Architecture Evolution
- Optical I/O will be
necessary, but hard to predict it’s timing of introduction since
Electrical interconnect will continue to innovate
Signaling Signaling Rate Rate (Gb/s) (Gb/s) 15 15 10 10 5 5 1 1 80’s
80’s 90’s90’s 00’s00’s
VESA VESA VL VL EISA EISA MCA MCA PCIx PCIx HT HT HL HL R I/O R I/O AGPx AGPx
1Gb/s Parallel Bus 1Gb/s Parallel Bus
>12 Gb/s Copper Signaling
>12 Gb/s Copper Signaling
Optical Optical Interconnects? Interconnects? Third Generation Third Generation I/O Architecture I/O Architecture
• Full SerialFull Serial
• Point to pointPoint to point
• Max Bandwidth/PinMax Bandwidth/Pin
• Scalable >10 Gb/sScalable >10 Gb/s
• FlexibilityFlexibility
• Multiple marketMultiple market
segment
segment
PCI
PCI UP TO 66 Mb/s
UP TO 66 Mb/s
ISA
ISA 8.33 Mb/s
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7 80 88 80 28 6 80 38 6 80 48 6 P en ti u m ® C P U P en ti u m ® II C P U P en ti u m ® II I C P U P en ti u m ® 4 C P U
CPU Platform Bandwidth History
(CPU interface and Memory)
8b it D R A M 16 b it D R A M 32 b it D R A M 32 b it D R A M 64 b it D R A M E D O 64 b it S D R A M P C 66 /1 00 64 b it S D R A M 10 0/ 13 3 64 b it D D R 33 3 12 8b it D D R 40 0
Bandwidth growing exponentially and is expected to continue
1.0 10.0 100.0 1000.0 10000.0 100000.0
1980 1985 1990 1995 2000 2005 2010
B an d w id th ( M B /s e c) , C P U C o re F re q ( M H z)
CPU I/F and DRAM BW RDRAM BW CPU Core Freq
Optical needed @ 20Gb/s per link
(40GB/s = 320Gb/s 16 pt-to-pt links)
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Noise Floor
Channel Bandwidth -55 Frequency L in e A tt e n u a ti o n ( d B ) Electrical attenuation Optical attenuation
As Frequency increases, optical interconnect
attenuates much more slowly than electrical
Optical attenuation O p ti c z l C o n v e rs io n L o s s
Target Data Rate Signal-to-noise increase
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Summary of Key Points
•
Circuit I/O architecture going from multi-drop bus to apoint-to-point bus for performance
•
Chip-to-Chip I/O speed will become limited by the Copperboard trace resistance / capacitance (attenuation vs frequency)
•
Beyond ~20Gb/s may need to go to a non-copper boardinterconnect – Optical waveguide.
•
Chip-to-Chip Optical Interconnect could be introduced(10)
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Summary of Requirements for Optical Interconnect
for Chip-to-Chip I/O in Computing Systems
•
Electronic- High-speed (>20Gb/s), low power, CMOS circuits
•
Optical- High-speed (>20Gb/s) Vertical Cavity Lasers (VCSEL) and Photodiodes arrays
- Low loss, low cost, optical waveguides (polymer or other)
•
Packaging- Hybrid Integration
- Compatible with IC industry - Passive alignment
•
Low cost approach to testing- Compatible with IC industry (in-line testing) - Self-test circuits
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Key Results for the Optical I/O Technical Paper
at Photonics West 1/29/04
•
Intel researchers built a fully functional chip-to-chip I/O linkworking at 1-3 Giga-Transfers per second (GT/s).
•
8 Gb/s aggregate data rate (8 channels each at >1Gb/s)demonstrated chip-to-chip over the optical link.
•
All the optical electronics (driver, receiver amplifier,testing) built in Intel’s low cost 0.18um CMOS
•
All the assembly packaging based upon Intel’s highvolume OLGA BGA package
•
Optical elements are 1x12 linear array of GaAs PINdetectors, GaAs Vertical Cavity Lasers (VCSEL), and polymer waveguide.
•
Demonstrated at the system level with a completefunctional end-to-end link a highly integrated feasibility prototpye
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Hybrid Integration Approach
•
Key components- CMOS Transceiver Chip
- 1x12 VCSELs, photodetector arrays - 1x12 Polymer waveguide arrays
•
Architecture Advantages:- Parallel architecture increases throughput
- Optical port removes distance limitation between two chips - Leverages microprocessor packaging technology
PCB
Polymer Waveguides VCSELs
Transceiver chip
Photodiodes MT connector
Prototype
Waveguide MT connector
Photodiodes
VCSELs Transceiver chip
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3Gb/s Transmitter Optical Eye
Current System Results
•
Transmitter demonstrated 3Gb/s open eye data transmission.•
>1Gb/s full-link error-free data transmission obtained.PRBS DATA
CLOCK
1Gb/s Full-link Error-Free Transmission
PRBS DATA
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Summary:
•
Intel has made significant progress demonstrating the feasibility of optical chip-to-chip interconnect.•
Optical chip-to-chip interconnect may offer a faster, cheaper, better alternative to metal-based data buses between CPU and it’s supporting chips•
The demonstration was done with 0.18um-CMOStransceiver, with on-chip drivers, amps, and self-test features. The transceiver chip is integrated with the optical emitters, detectors, and wave-guides in a hybrid package
•
This announcement is a progress report from Intel’s Component’s Research Lab. Intel has not made a determination on product plans based upon these results.(15)
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For further information on Intel's silicon technology,
please visit the Silicon Showcase at
(16)
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Computer I/O Architecture
• I/O architecture has moved to point to point
• I/O Bandwidth requirements are likely to exceed more than >10x in next 10 years
• Optical I/O is consistent with this architectural direction
USB2.0 USB2.0 Graphics Graphics Graphics Graphics Memory Bridge Memory Bridge PCI PCI Express Express HDD HDD HDD HDD PCI PCI Memory Memory Memory Memory CPU CPU CPU CPU SIO Serial Serial ATA ATA Gb Ethernet* Gb Ethernet* Add ins Add ins PCI Express PCI Express I/O Bridge I/O Bridge Add ins Add ins Add ins Add ins LPC LPC
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Optical IO Architectures
•
Two main approaches based upon levels of Integration– Hybrid/Heterogeneous Component Integration
External optical components packaged with the microprocessor
– On-Chip Integration
Full integration of optical components on logic process flow except CW laser (optical power supply)
•
This research work focuses on the Heterogeneous/Hybrid approach(1)
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3Gb/s Transmitter Optical Eye
Current System Results
•
Transmitter demonstrated 3Gb/s open eye data transmission.•
>1Gb/s full-link error-free data transmission obtained.PRBS DATA
CLOCK
1Gb/s Full-link Error-Free Transmission
PRBS DATA
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Summary:
•
Intel has made significant progress demonstrating the feasibility of optical chip-to-chip interconnect.•
Optical chip-to-chip interconnect may offer a faster, cheaper, better alternative to metal-based data buses between CPU and it’s supporting chips•
The demonstration was done with 0.18um-CMOStransceiver, with on-chip drivers, amps, and self-test features. The transceiver chip is integrated with the optical emitters, detectors, and wave-guides in a hybrid package
•
This announcement is a progress report from Intel’s Component’s Research Lab. Intel has not made a determination on product plans based upon these results.(3)
1 5
For further information on Intel's silicon technology,
please visit the Silicon Showcase at
(4)
(5)
1 7
Computer I/O Architecture
• I/O architecture has moved to point to point
• I/O Bandwidth requirements are likely to exceed more than >10x in next 10 years
• Optical I/O is consistent with this architectural direction
USB2.0 USB2.0 Graphics Graphics Graphics Graphics Memory Bridge Memory Bridge PCI PCI Express Express HDD HDD HDD HDD PCI PCI Memory Memory Memory Memory CPU CPU CPU CPU SIO Serial Serial ATA ATA Gb Ethernet* Gb Ethernet* Add ins Add ins PCI Express PCI Express I/O Bridge I/O Bridge Add ins Add ins Add ins Add ins LPC LPC
(6)
1 8
Optical IO Architectures
•
Two main approaches based upon levels of Integration– Hybrid/Heterogeneous Component Integration
External optical components packaged with the microprocessor
– On-Chip Integration
Full integration of optical components on logic process flow except CW laser (optical power supply)